Abstract: An RM code soft decision decoding method using decision by majority comprises: (a) performing multiplication on a bit group of a codeword, and calculating an information bit's estimate group; (b) summating elements of the group and obtaining a final estimate of the degree's information bit to perform decision by majority; (c) using the final estimate to generate a codeword corresponding to each degree's information bit final estimate, and removing the generated codeword from the codeword of (a); (d) repeating the step (c) for the final estimates of the remaining degrees' information bits other than zero-order information bit; and (e) summating elements of codewords of results performed on the final estimates of the first-order information bit in (d) to estimate the zero-order information bit's final estimate.

Abstract: A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical instructions communicates transactions to at least one target device, such as input/output device, or another data processing element. The transactions are communicated through the asynchronous switching fabric wherein each of the data processing elements and the target device are connected to the asynchronous switching fabric through a respective channel adapter.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: The present invention is directed to a system and method for data verification in a RAID system. A method of verifying data in a RAID system may include reading a first item of data from a first data storage device and a second item of data from a second data storage device. The first item of data from the first storage device is compared with the second item of data from the second storage device. If the first item of data does not match the second item of data, a third item of data is read from a third data storage device. The third item of data is compared with the first item of data and the second item of data.

Abstract: To improve the probability of error correction, thereby generating correct read data. Data is read from the same sector by a number of times and a majority decision is done in the same address, thereby the most frequently read value is regarded as the true data value in the address. For example, for an address 00, “00” is handled as a true data value.

Abstract: An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals. Glitches are detected in the input data signals by detecting reversals of signal level having a duration less than the input bit period. A glitch time value corresponding to the glitch duration is determined, and then a sampling clock rate is set at a rate determined from the glitch time value. The input data signals are sampled at the sampling clock rate to generate a sequence of input data samples. A voting number of input data samples are monitored and an output signal is provided, representing the value of a majority of the sequential input data samples.

Abstract: There is provided a digital data receiver for recovering at least one message word signal from a digital data frame.

Abstract: A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-zero) number of errors is detected.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: A fault tolerant processing circuit comprising at least three processor groupings, a synchronizing circuit and a fault logic circuit. Each of the processor groupings have a plurality of processor grouping inputs and a plurality of processor grouping outputs. The synchronizing circuit comprises a plurality of output synchronizers, wherein each output synchronizer communicates with a corresponding respective processor grouping for synchronizing the output of each processor grouping. A fault logic circuit communicates with the synchronizing circuit. The fault logic circuit comprises a fault detection circuit and a fault mask circuit. The fault logic circuit compares the plurality of processor group outputs to detect errors in any one of the plurality of processor group outputs. An error is detected when none of the at least three processor groups is in a majority of the processor groups.

Abstract: A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.

Abstract: How a first result of a first operation compares to a second result of a second operation is identified. The identification may be performed without producing the first result or the second result. The first result or the second result may be selected in response to the identification, and the first operation or the second operation may be performed in response to the selection to produce the selected result. Alternatively, the first operation may be performed to produce the first result and the second operation may be performed to produce the second result. The produced first result or the produced second result may be selected in response to the identification.

Abstract: Positions in which errors have occurred are found more accurately and erasure correction is performed more effectively than in cases where TA flags or error flags issued by the R/W channel are utilized as information indicating the positions in which errors have occurred, [this being accomplished] by reading the same sector on the magnetic disk a plurality of times, storing the plurality of NRZ data thus obtained, comparing these NRZ data in byte units, judging that an error has occurred in byte positions where the NRZ data reproduced in each read operation differs, and utilizing these positions as erasure pointers for erasure correction.

Abstract: A system and method for an election and data majority mechanism that solves problems such as bit flipping, mistracking, miscaching, and I/O status errors during real-time operations. Multiple copies of data are stored on various storage media of a data processing system. Errors that occur on the storage media or on other components of the data processing system are resolved by selecting the data with the highest frequency as the data majority. The data majority is propagated throughout the storage media to correct errors.

Abstract: A semiconductor chip of the present invention includes a plurality of first elements each of which diagnoses itself, and a second element which inputs diagnosis results from the first elements and determines whether or not there is a faulty first element in the first elements. A method of the present invention which is performed in a semiconductor chip including a plurality of first elements, includes diagnosing the first elements by itself; and determining whether or not there is a faulty first element in the first elements based on diagnosis results from the first elements.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: An electric circuit for a vehicle electrical system powered by a voltage supply. The circuit includes a control stage having a switching device, a switching module, a signal output, and a connecting line connecting the signal output to the electrical system. The switching device includes a switching element switchable between two switching states for generating respective switching state output signals at the signal output to switch the electrical system between functional states. The switching module includes a non-volatile flip-flop formed by EEPROM cells which are operable for storing the switching state. The switching module maintains the switching state output signal to maintain the functional state of the electrical system until the switching element is switched to a different switching state, and maintains the switching state output signal to maintain the functional state of the electrical system during a voltage supply interruption.

Abstract: In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic.

Abstract: There is provided an image failure detection unit in redundant duplex transmission in which a failure occurring on a regular link is detected at in real time, and the link is instantaneously switched to a normal backup link, thereby preventing any failure from occurring on an output image or reducing the failure. Units for calculation of the image features calculate image features of links A and B, respectively. A comparison unit compares the image features, and then, it is judged that both of the links are normal if there is not difference between the image features. To the contrary, if there is a difference, it is judged that there is a probability of occurrence of a failure on one of the links. Thereafter, a normal/corrupted information memory stores a small region relating to the image features. Units for detection of image feature differences determine image feature differences for the links, respectively.

Abstract: A data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle, in which the first device transfers the data to the second device through the signal path. The first arithmetic unit outputs the first result onto the signal path during an idle cycle in which no data is transferred through the signal path. The second device includes second arithmetic unit and comparator. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result. The comparator compares the first result, transferred through the signal path in the idle cycle, to the second result and outputs a comparison result.

Abstract: A control system for executing an application program is disclosed herein. The control system includes a plurality of main processor modules. The control system further includes a plurality of input/output modules for providing input process data to associated ones of the plurality of main processor modules. A voting system is operative to compare the input process data associated with first and second of the plurality of main processor modules to the input process data associated with a third of the main processor modules. This results in generation of voted input process data utilized by the third main processor module in executing the application program. In certain implementations the system includes a high-speed bus for distributing the voted input process data to the first and second main processor modules, each of which also executes the application program based upon the voted input process data.

Abstract: An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals. The glitches comprise reversals of signal level, having a glitch duration less than the predetermined bit period, on the input data signals. Glitches are detected in the input data signals by detecting reversals of signal level having a predetermined duration less than the predetermined input bit period. A glitch time value corresponding to the glitch duration is determined, and then a sampling clock rate is determined from the glitch time value. The input data signals are sampled at the sampling clock rate to generate a sequence of input data samples.

Abstract: A fault tolerant integrated circuit employs triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The integrated circuit includes three or more registers and a majority voter. The three registers are connected in series to each other with the output of the first register being connected to the input of the second register and the output of the second register being connected to the input of the third register. The majority voter is connected to the output of each register and generates a signal corresponding to the majority of all of the register outputs. The output of the majority voter is connected to the input of the first register, thereby correcting any incorrect data stored in the registers.

Abstract: An arbitration system having a common resource and a first arbitration logic. The first arbitration logic includes a plurality of logic sections. Each one of the logic sections is fed a corresponding one of a plurality of request signals for the common resource. The logic sections produce, in response to request signals, a corresponding one of a plurality of grant signals. Each one of such sections has: a corresponding one of a plurality of first data storage elements, each one of such storage elements storing a corresponding one of the grant signals in response to first clock pulses, such stored grant signals being provided at outputs of the storage elements. The arbitration system includes a plurality of transmission channels, each one having an input coupled to a corresponding one of the outputs of the plurality of first data storage elements. The plurality of transmission channels pass the grant signals stored in the first data storage elements to outputs of the transmission channels.

Abstract: A counting apparatus comprising an execution detection circuit for detecting the execution of a predetermined operation; plural memory circuits for commonly storing the information on the number of execution at each detection of the execution; a destruction detection circuit for detecting, at the storage of the information, whether the information stored in each memory circuit is destructed; and a correction circuit adapted, upon detection that the information of a memory circuit is destructed, to correct the destructed information with the information of another memory circuit.

Abstract: A protection system for a complex process has four redundant protection sets, each of which produces partial reactor trip and partial safeguard actuation signals in pairs of microprocessor-based controllers. Two independent and redundant voting logic trains are provided for the partial reactor trip signals, and two identical, independent and redundant voting logic trains are provided for the partial safeguard actuation signals. Each of the trains includes a pair of redundant microprocessor-based voting logic controllers, each of which receives the partial reactor trip or partial safeguard actuation signals from each of the process protection sets and has a voting processor which generates an intermediate reactor trip or intermediate safeguard actuation signal in response to partial signals from a predetermined number of protection sets. The intermediate signals from the two voting logic controllers in each train are ANDed to generate train signals.

Abstract: Disclosed is an apparatus and method for error detection in a precise system board requiring reliability and safety for controlling a number of processes, in which a failure detector and maintainer is connected to the system board, so as to detect a failure of the system board and normally maintain the operation of the system board even in failure.

Abstract: Methods and systems for fail-safe process execution, monitoring and output control for critical systems operating on an open bus architecture with multiple, independent partitions on a single processor is presented. The control system state variables and their status of critical systems, within the control laws and mode logic, are monitored for process completion and health, and shut down if necessary. The embodiments provide for a dual path for shut down of, for example, flight critical systems so that the failure of one partitioned module does not affect the operation of the remaining partitioned modules. One path involves the CPM and IOM determination of command/response health. If persistent faults are detected, then either the DSP monitoring or the CPM performance monitoring results in a discrete signal being sent to the H-bridge disable to shutdown the current output.

Abstract: A majority decision method for improved frame error rate in the digital enhanced cordless telecommunications (DECT) system. Specifically, one embodiment of the present invention includes a method for improving retransmission efficiency of a data frame within a communication system. The method includes the step of receiving and storing three corrupted versions of a data frame within a memory. Moreover, the method also includes the step of performing a byte-wise comparison of the three corrupted versions of the data frame to locate an inconsistent byte position. In response to locating the inconsistent byte position among the three corrupted versions of the data frame, the method includes the step of performing a byte-wise majority decision among the three corrupted versions of the data frame to select a correct byte value of the inconsistent byte position.

Abstract: The present invention relates generally to the detection of bits which are protected by repetition, and which, along with their repetitions, have associated soft values available which give a measurement of the reliability of their received values. In particular, the present invention may be used in speech encoding in the GSM mobile communications system, and more particularly to the detection of those class 2 bits called pulse5 bits which are not protected with channel coding. In enhanced full rate (EFS) transmission in GSM there are 4 bits called pulse5 bits. These pulse5 bits are duplicated twice, giving three bits for each original bit, for a total of twelve pulse5 bits. These bits have associated soft values, a probability measure of their reliability, that are produced by the equalizer.

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits.

Abstract: The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a word basis of the word output of each of the n modules. The voter is based on a majority voting principle. The advantage of the present invention is that the word voter can be used to design redundant systems, such as, but not limited to, TMR systems, that are protected against common mode and multiple output failures. In addition, another advantage of the present invention is that is provides for a technique to efficiently design a TMR simplex system. The present invention provides a word voter for hardware systems.

Abstract: A redundant latch circuit resistant to SEUs includes a plurality of latches, a majority voting circuit having inputs connected to the latch outputs, and a feedback reset circuit connected to the latch outputs and driving the latch reset inputs. The majority voting circuit indicates a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise. The feedback reset circuit may have inputs connected to the outputs of the latches, and outputs connected to the reset inputs of the latches. The feedback reset circuit may switch at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state to thereby provide resistance to SEUs.

Abstract: A method for performing 3/5 major voting in the TACS/AMPS mobile phone system, in which a word of the message frame is transmitted repeated five times and every bit of the word is given a value at reception by major voting of the five repeats. The number of ones or zeros of a bit C is counted at least to three. This number is saved as a binary two-bit number B′A′ in two memories (2, 3) so that the first (2) contains the least significant bit A′ of the number B′A′ and the second (3) contains the most significant bit B′ of the number B′A′. After the fifth repeat of the bit C, the final number of ones or zeros of the bit C has been counted and saved in the memories (2, 3) and voting is performed on the bit C based on bits A′ and B′ indicating the number of ones or zeros.

Abstract: A multi-chip data decoder implemented for symmetric differential phase shift keying (SDPSK) or symmetric differential quadriphase shift keying (SDQPSK) modulation formats which uses multiple-chip observation intervals to improve performance over conventional symbol-to-symbol differential detection. Input phases &phgr;k, &phgr;k−1, &phgr;k−2, and &phgr;k−3 are detected by comparing a received vector of data bits and parity bits, which contains phase transition information over multiple chips, to the set of ideal vectors of data bits and parity bits, which contain all phase transition possibilities over that set of chips in a noiseless environment.

Abstract: Data are detected and corrected with first and second error detecting and correcting stages. The first stage error detection and correction capabilities are determined by the number of errors it can detect and correct in a predetermined length data stream. The first stage determines the number of known and unknown data stream errors, corrects errors within its capability, and outputs to the second stage error states relative to the data stream. One state indicates no known data stream errors or first stage data stream correction being attained with less than first stage capability. Another state indicates the number of data stream errors exceeds the predetermined capability, resulting in failure to make the correction. A third state indicates correction of all data stream errors using all the first stage capability.

Abstract: A method and apparatus for detecting duplicate messages and correcting garbled messages in a wireless communication device are provided. According to one aspect of the present invention, erred messages received by a wireless communication device are corrected. A first message fragment is received by the wireless communication device. The first message fragment is corrected based upon a second message fragment after it has been determined that the first message fragment contains one or more errors. According to another aspect of the present invention, a wireless communication device includes a receiver configured to receive messages transmitted over a forward channel from a messaging system; a transmitter configured to transmit responses over a reverse channel to the messaging system; and a processor. The processor is coupled to the receiver to receive messages from the messaging system. The processor is further coupled to the transmitter to transmit acknowledgments to the messaging system.

Abstract: In a data transmission method for information data containing additional information data therewith, comprising, at a transmitter side, following steps:

Abstract: Apparatus and method to reduce the duration of timeout periods in fault-tolerant distributed computer systems. When nodes execute a task redundantly and communicate their results over a network for further processing, it is customary to calculate timeouts on a worst-case basis, thereby prolonging their duration unnecessarily. By applying Tchebychev's inequality, which holds for any statistical distribution, to adaptively determine the distribution of the arrival times of the results at the point where further processing of those results takes place, the duration of timeouts is reduced. Successively refining the statistical distribution of the arrival times leads to an improved forecast of future arrivals. Thus timeouts are kept to a minimum without compromising the reliability of the system.

Abstract: A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of the registers for generating an output signal of the logic cell; and a circuit coupled to each latching register for altering selectively the scan chain data signal input thereto. A scan chain test system for and method of testing at least one multiple voted logic cell of the aforementioned type are also disclosed.

Abstract: The present invention uses an acoustic modem embedded in a remote device enhanced with automatic repeat request and forward error correction routines to provide reliable transfer of electronic messages from the messaging server to the remote device. This may provide significantly better error correction than standard PC modems. Also the present invention, may provide a fast, reliable connection sequence by use of a preamble frame. According to an embodiment of the present invention, a method of communicating messages between a messaging server and a remote device is provided. The method includes a variety of steps such as establishing a connection between the messaging server and the remote communication device by transmitting a preamble frame, exchanging data frames between the remote device and the messaging server, detecting and correcting errors in received frames, and re-transmitting received frames, if errors are uncorrectable.

Abstract: A functional entity in a digital switch is triplicated in planes operating in parallel. From each plane, a respective passing data flow is spread to parallel planes. A majority vote function receives the data flows of the planes and compares these on a bit level for creating a majority voted data flow. A plane condition sensing function indicates whether links of the planes have meaningful information and synchronism, and emits, as a result, a link condition indicating signal for each plane. A priority select function is connected for receiving the majority voted data flow and the link condition indicating signals. If the link condition indicating signals indicate a fault condition, the priority select function lets the majority voted data flow through as an outgoing data flow from the functional entity.

Abstract: Communications between an RFID interrogator and an RFID transponder require that no more than one transponder be present in the reading range of the interrogator and transmitting into motion at any given time. If multiple transponders are in the field, then a collision between the return signals of the transponders occurs, rendering the signals unreadable. A method to resolve the collisions and allow for accurate transmission of each transponder's data is given. This method is especially effective over other methods when the transponder is a read-only type of device, whereby there is no communications interrogator on board the read-only transponder.

Abstract: The invention relates to majority voting testing. A number of input signals are monitored individually by separate monitors, one monitor for each signal. Each monitor generates a control signal representing the status of the monitored signal. The generated control signals are sent to a level control unit. The level control unit controls the input levels to a majority voter according to the control signals. Instead of signals that are faulty, the level control unit selects signals of specific logical levels to be forwarded to the majority logic. The logical levels of these so called replacement signals are selected such that the replacement signals do not interfere with the remaining correct signals. Furthermore, the majority voted output signal is monitored so as to selectively generate an alarm. The voting functionality is tested by stopping input signals according to a first procedure, thus generating an alarm. By stopping input signals according to a second procedure, an alarm is avoided.

Abstract: A data storage system having a plurality of addressable memories for storing a global variable. Each one of a plurality of controllers is adapted to request an operation on first and second data stored in the addressable memories. Each one of the addressable memories includes: a control logic for receiving the operation request and addresses of the first and second data from one of the controllers; a random access memory; and a buffer memory coupled between the bus and a random access memory. The buffer memory has a write buffer memory adapted to store the first data in response to the control logic and a read buffer memory adapted to store the second data. The second data is read from the random access memory in response to the control logic. The buffer memory includes an operation selection section having a plurality of operation units configured to perform a different predetermined operation on the first and second data fed to a pair of input ports thereof.

Abstract: The invention relates to majority voting. A number of input signals are monitored individually by separate monitors, one monitor for each signal. Each monitor generates a control signal representing the status of the monitored signal. The generated control signals are sent to a level control unit. The level control unit control the input levels to a majority voter according to the control signals. Instead of signals that are faulty, the level control unit selects signals of specific logical levels to be forwarded to the majority logic. The logical levels of these so called replacement signals are selected such that the replacement signals do not interfere with the remaining correct signals. Furthermore, the majority voted output signal is monitored so as to selectively generate an alarm. The voting functionality is tested by stopping input signals according to a first procedure, thus generating an alarm. By stopping input signals according to a second procedure, an alarm is avoided.

Abstract: First and second instances of a message are received over a wireless connection. It is determined whether the first and second instances of the message contain an error. If both instances contain an error, an error free instance of the message is reconstructed from the two erroneous instances by merging portions of the first and second instances.