Abstract: A system and method for error-resilient data reduction, utilizing a phase detector, a data requestor, a multi-phase trainer, a reconstruction engine, a deconstruction engine, and one or more reference codebooks. A multi-phase trainer may be used to train the reconstruction and deconstruction engines on various phase sourceblocks in order recover quickly from corrupted data files that cause the phase alignment of the sourceblocks to become out of phase. A phase detector may determine when the sourceblocks get out of phase and when the return to in-phase by checking if a predetermined threshold probability of correct encoding is met. Data requestor may request for retransmission only the data that was received out of phase.

Abstract: Aspects of the present disclosure relate to techniques for mitigating inadvertent user information collection in telemetry data. In examples, user information is used to evaluate telemetry data associated prior to transmission to a server device. If an instance of user information is identified within the telemetry data, a warning indication is generated. The warning indication may be transmitted to the server device either instead of or in combination with the telemetry data. As a result of the warning indication, the software may be modified to resolve the issue that caused the introduction of the user information into the telemetry data, thereby avoiding future instances of inadvertent data collection. In response to the warning indication, the server may be configured to reject similar telemetry data from other devices, thereby avoiding collecting such data from the other devices.

Abstract: A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.

Abstract: A data encoding method and apparatus and a data decoding method and apparatus in a passive optical network (PON) system include collecting N data blocks at a physical coding sublayer and generating valid data by combining the N data blocks, generating a payload, where the payload includes the valid data, performing FEC encoding on the payload to generate a check part, and generating a codeword structure. The synchronization header may be located at the head or the tail of the codeword structure.

Abstract: A system and methods for bandwidth-efficient cryptographic data transfer, utilizing an encoding endpoint device, a decoding endpoint device, a reference codebook, and a plurality of data to encode and decode, which may use specific algorithms on top of block cipher encryption to achieve higher data security and ease the burden on users with regards to computational power, complexity, and bandwidth for communication.

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

Abstract: Efficient codeword synchronization methods and systems for fiber channel protocol are disclosed. The method includes identifying a codeword boundary by detecting 100-bit known patterns in a bit codeword in a transmission.

Abstract: An application platform system and method. A data synchronization instance manages a reference state object for a data synchronization system (DSS) account. A first local state object is stored at a first application system. The first application system receives update notifications provided by the DSS. A second local state object is stored at a second application system. The second application system receives update notifications provided by the DSS. An application instruction of the first application system is transformed into a state update, and the first local state object is modified to include the state update. The state update is provided to the DSS via a local update notification. The reference state object is modified to include the state update. The state update is provided to the second application system via a reference update notification. The second local state object is modified to include the state update.

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

Abstract: An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

Abstract: Excess capacity of a database system can be used for learning activities in a controlled computing environment. In this context, excess capacity of a database system can be used as needed and/or on a temporary basis. Furthermore, learning activities can be performed without requiring the use of the capacity that is configured or has been allotted for various other database operations, including those deemed, especially by the users of database system, to serve a main function or a more important purpose. As a result, learning can be performed without adversely affecting other operations deemed to be more critical, especially by the users of databases. Learning activities associated with a database environment can, for example, include learning operations directed to optimization of database queries, for example, by using a basic feedback or an expanded or active learning.

Abstract: Apparatus, systems, and methods may operate to monitor operations of at least one processor to define a set of executed applications executed under a first operating system over a selected time period; and to generate an image of a second operating system having sufficient resources to service a subset of the set of executed applications, the subset determined according to a usage pattern defined by at least a portion of the selected time period, the number of resources provided by the second operating system being less than or equal to the number of resources provided by the first operating system. The images may be loaded based on receipt of a menu selection. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments of the present invention provide an application display method and apparatus. A second application that has an association relationship with an application (a first application) that is currently displayed on a terminal is acquired according to a stored association relationship between applications of the terminal, and the second application is displayed after the first application exits. That is, an application that a user expects to use is predicted according to the stored association relationship between the applications, and a large amount of sensor data of the terminal and external data do not need to be collected, thereby improving processing performance of the terminal.

Abstract: A method of determining a second application related to a first application being executed by using a use log of a portable terminal and executing the second application according to a user input and an apparatus for supporting the same are provided. The portable terminal may determine the second application related to the first application being executed, based on a use log collected in a previous context state identical or similar to a current context state of a user. At this time, in order to determine the current context state of the user, the portable terminal may use information related to a location of the portable terminal and information related to a current time.

Abstract: A video/audio synchronization apparatus includes: a decoder configured to decode a frame contained in encoded video data and determine playback time of the frame based on a first clock signal, and decode encoded audio data and determine playback time of an associated audio signal contained in the decoded audio data and to be played back simultaneously with the frame, based on a second clock signal different from the first clock signal; a silent period detector configured to detect a silent period from within the associated audio signal; and an audio timing adjuster configured to reduce a difference between the playback time of the frame and the playback time of the associated audio signal by skipping or repeating a silent period contained within a period of the associated audio signal.

Abstract: A mobile device includes a storage unit which stores application specification information that specifies an application to be activated in association with movement information that is a combination of a movement source and a movement destination, a position information acquisition unit which repeatedly acquires current position information of a user, and a control unit that calculates a movement direction of the user based on a history of the position information that the position information acquisition unit acquires, selects any one of the movement information that is stored in the storage unit based on the calculated movement direction and the current position information of the user, reads the application specification information associated with the selected movement information from the storage unit, and activates the application associated with the application specification information that is read.

Abstract: Methods and computer products can provide personalized content based on historical interaction with a mobile device. A computing device can receive information about a user interaction with an application running on the mobile device at a first time and location. A type of the application can be identified by parsing a description of the application (e.g., using a natural language processing algorithm). An affinity model can be generated that associates the type of the application with the first time and/or location. At a second time and location, it can be determined that the second time corresponds to the first time and/or that the second location corresponds to the first location. Using the affinity model, the second time and/or location can be associated with the type of the application, and the mobile device may then display content related to the type of the application.

Abstract: A mobile data network supports making subscriber data addressable as devices in a mobile data network. Each data chunk is assigned a device address in the mobile data network. The data chunk can then be addressed as a device in the mobile data network. Data chunks corresponding to a subscriber are distributed across multiple devices in the mobile data network, which may include subscriber devices, network components in the mobile data network, and specialized devices provided by storage providers. A subscriber's historical data usage is monitored and logged, and may be used to predictively move the subscriber's data when needed to improve the subscriber's access to the data.

Abstract: A mobile data network supports making subscriber data addressable as devices in a mobile data network. Each data chunk is assigned a device address in the mobile data network. The data chunk can then be addressed as a device in the mobile data network. Data chunks corresponding to a subscriber are distributed across multiple devices in the mobile data network, which may include subscriber devices, network components in the mobile data network, and specialized devices provided by storage providers. A subscriber's historical data usage is monitored and logged, and may be used to predictively move the subscriber's data when needed to improve the subscriber's access to the data.

Abstract: A device having a storage location for receiving an original data and a corresponding original error correction code (ECC) is provided. The device includes ECC modification pattern generator logic for comparing modified data and the original data for generating a pattern for modifying the original ECC and ECC modification logic for modifying the original ECC based on the pattern.

Abstract: A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal.

Abstract: A system and methods for managing applications on a mobile device. One method includes: receiving context data related to the mobile device; assigning a situational utility score to one or more applications available in an application repository by analyzing the context data and tags associated with the one or more applications to determine which applications have situational usefulness; and when a first application has a situational utility score greater than a first threshold value, displaying a prompt on the mobile device to install the first application.

Abstract: High speed communication networks divide data traffic into multiple physical lanes. For example, the IEEE standard 40 G/100 G supports sending Ethernet frames at 40/100 gigabits per second over multiple 10/25 Gb/s lanes. Techniques are disclosed for aligning the data across the physical lanes.

Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

Abstract: A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data.

Abstract: New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

Abstract: A method includes receiving a first clock signal from a first clock source at a clock monitoring unit. The method also includes counting a first number of pulses in the first clock signal during a specified time period. The method further includes identifying a fault with the first clock source when the first number does not have an acceptable value. In addition, the method includes testing the clock monitoring unit by determining whether the clock monitoring unit identifies an artificial clock fault. The time period could be defined by receiving a second clock signal, counting a second number of pulses in the second clock signal, and signaling when the second number meets or exceeds a threshold value. In response to the identified fault with the first clock source, a second clock source could be used to provide a second clock signal.

Abstract: Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.

Abstract: Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting may be performed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization may be effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a phase-controlled clock signal to achieve phase-locking with a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking with the reference clock signal. The processor is also configured to monitor a deviation between the frequency and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with, or on the basis of, the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

Abstract: Embodiments of the present invention provide a system for secure error detection and synchronous data tagging for high-speed data transfer (e.g., utilizing a set of SSD memory disk units). Specifically, in a typical embodiment, the system comprises a SSD memory disk unit in communication with a device driver. A first encoded communication stream will be generated with the device driver and sent via PCI-based channel (e.g., full duplex) to the SSD memory disk unit. The stream is received, synchronized, and decoded on the SSD memory disk unit. In turn, the SSD memory disk unit can generate and send a second encoded communication steam to the device driver.

Abstract: Error concealment guided robustness may include identifying a current portion of a current video stream. Identifying the current portion may include identifying a feature, or a vector of features, for the current portion. An estimated vulnerability metric may be identified based on the feature and an associated learned feature weight. An error correction code for the current portion may be generated based on the estimated vulnerability metric. Error concealment guided robustness may include generating learned feature weights based on one or more training videos by generating vulnerability metrics for the training videos and identifying relationships between features of the training videos and the vulnerability metrics generated for the training videos.

Abstract: A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

Abstract: A nonvolatile semiconductor memory outputs the first parity flag corresponding to the error-corrected read data from the second input/output pin in synchronization with the error-corrected read data in the data buffer outputted from the first input/output pin.

Abstract: New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

Abstract: A system including a padding field generator and an encoder. The padding field generator is configured to generate a first padding field for a frame. The frame includes (i) a preamble field, (ii) a syncmark field, and (iii) a data field. The first padding field is located between (i) the preamble field and (ii) the syncmark field. The preamble field, the first padding field, and the syncmark field precede the data field. The encoder is configured to encode, using an error-correcting code, (i) the first padding field, (ii) the syncmark field, and (iii) the data field; and to generate, based on the encoding performed using the error-correcting code, one or more parity bits. The one or more parity bits are stored in a parity field of the frame. The parity field is located subsequent to the data field in the frame.

Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

Abstract: A communication apparatus realizes an FEC function. In the communication apparatus, a T_FEC-pattern comparing unit calculates a code distance between a pattern of an input FEC frame falling in a certain detection window and the pre-defined T_FEC pattern for each of the detection windows one after another. Moreover, a code-distance comparing unit compares the code distances with each other to detect a code for boundary identification T_FEC between an IEEE802.3 frame and a FEC parity. Finally, a boundary-signal generating unit generates, based on the detected code for boundary identification T_FEC, a T_FEC boundary signal that indicates a detection position of the T_FEC in the input FEC frame.

Abstract: A device (102) supports error correction. A receiver (120) is configured to receive data over a communications link. A decapsulator (122) is coupled to the receiver and configured to create datagrams. A decoder (124) is coupled to the decapsulator and configured to store the datagrams in a table and to create codewords, the decoder storing the datagrams in table columns to create codewords in table rows. A user interface (126) is coupled to the decoder and configured to render images corresponding with the datagrams on the user interface. Advantages of the invention include efficient signal processing and prolonged battery life in mobile wireless devices.

Abstract: Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: An endoscope apparatus has a transmission device of an endoscope and a reception device of a processor. The transmission device calculates a DC balance value of input data, compares the DC balance value and a cumulative value thereof, and compares the sign of the DC balance value and the sign of the cumulative value. When the signs are the same sign, the transmission device generates intermediate data by exchanging a first value and a second value with each other for all the bits of the input data, and generates predetermined information indicating that all the bits have been inverted. When the signs are different signs, the transmission device performs a process of setting the input data as the intermediate data and transmits the intermediate data by a serial signal.

Abstract: For use in a wireless communication network, a transmitter is configured to encode information. The transmitter includes a cyclic redundancy check (CRC) encoder configured to encode a physical broadcast channel (PBCH) message using a cyclic redundancy check. The transmitter also includes a timing dependent cyclic shift block configured to encode information in the PBCH message. The transmitter further includes a quasi-cyclic low-density parity-check (QC-LDPC) encoder configured to encode the PBCH message using a QC-LDPC.

Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise: a function module to operate according to a clock signal; a clock manipulation module to manipulate an edge of the clock signal responsive to occurrence of a predetermined condition; and a report module to indicate a clock cycle number of the edge of the clock signal responsive to occurrence of an error in the function module.

Abstract: A transmitting and receiving system includes first and second transmitting and receiving apparatuses. The first transmitting and receiving apparatus includes a generating unit and a transmitting unit. The generating unit generates a packet for transmission by attaching packet identification information to transmission data to which an error detection code is attached, and uses, as the packet identification information, a code that is capable of detecting a 1-bit error caused by transmission of the packet for transmission. The transmitting unit converts the number of bits of the packet for transmission and transmits the converted packet. The second transmitting and receiving apparatus includes a receiving unit and a correcting unit. The receiving unit subjects the transmitted packet to inverse conversion of the number of bits. The correcting unit detects a 1-bit error in the packet identification information of the inverse-converted packet, and corrects the error.

Abstract: A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor.

Abstract: A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit.