Abstract: A system and method for correcting so-called “lip sync” errors is provided, using a synchronization test signal comprising a video signal including a colourbar signal that is periodically interrupted by a series of consecutive defined black frames and an audio signal comprising a tone periodically interrupted by a period of silence beginning at the same time as the first of the series of consecutive defined black frames. The synchronization test signal is configured to survive encoding, decoding, conversion, and compressing processes used in a typical digital broadcast system environment and thus provide a means of measuring the relative audio and video timing of a processed signal.

Abstract: Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.

Abstract: The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the sampling method as a function of the error-check on the sampled signal.

Abstract: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock signal, and an error detection-&-correction circuit configured to detect and correct an error in data stored in the flip-flops, and to produce one of the error-detection signals indicative of the detection of the error upon the detection of the error.

Abstract: A method for generating parallel codes is provided that includes generating a plurality of pairs of outputs for each clock cycle using a single code generator and generating a code based on each pair of outputs using the single code generator.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

Abstract: An FEC apparatus and method is provided that uses turbo codes. An input frame is iteratively decoded until an iterative decoding stop command is received under a predetermined control, and the absolute reliability of each symbol in the frame is output. The minimum of the absolute reliabilities is detected as a measurement, and a threshold is detected using the a-priori information and extrinsic information of the each symbol. The measurement is compared with the threshold, and the iterative decoding stop command is output according to the comparison result.

Abstract: Disclosed is a method for reducing power consumption of a user terminal when synchronization between a user terminal and a base station is disrupted in a broadband wireless access communication system.

Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.

Abstract: In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal transition location is converted to a delay value. The delay value is converted to an edge position output, and a value of the edge position output is detected.

Abstract: A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.

Abstract: A system tests an integrated circuit at operational speed. The system includes a high frequency clock converter that receives test clock signals at a speed lower than operational speed of the integrated circuit to be tested. The high frequency clock converter generates test clock signals for operational speed testing of the integrated circuit.

Abstract: A synchronization variable intended for a second clock signal is generated from a first clock signal and a phase variation signal. A first approximation of the second clock signal is determined, and other approximations close to the first approximation are also determined. An error is calculated for each of the approximations, and the best approximation is taken as the second clock signal.

Abstract: The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a recovered clock. In order to identify data transitions, the received serial data stream is sampled N times per ideal bit time, where the minimum value for N must be greater than 2/(1?(2*jitter_ratio)) and jitter_ratio is the fractional representation of the portion of the ideal bit time during which transitions can be expected or estimated to occur. On identifying a transition, a toggle phase is set. In order to avoid stale clock phase selection resulting from jitter and the like, one phase after the toggle phase is blocked or prevented from being selected for the clock. Finally, a clock phase is selected N/2 phases from the toggle phase and a recovered clock is generated by combining the individually selected clock phases.

Abstract: A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings of defined times between edges in cycles even in a case where a capacity is large as in a test pattern for the semiconductor test equipment or a case where the cycles are away from each other.

Abstract: A backup system includes a first storage device having first storage areas in which an update log of recorded data is stored; a second storage device having second storage areas which are paired with the first storage areas respectively and in which a copy of the update log is stored; and a disk controller. The state of a pair of first and second storage areas is changed from a non-pair state in which the update log is not stored in the pair of first and second storage areas to a pair state. The state of another pair of first and second storage areas is changed from a pair state to a non-pair state. The disk controller includes first and second disk controllers for controlling the first and second storage devices, respectively. The changes of pair/non-pair states are executed by the first disk controller.

Abstract: An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement circuit includes a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of the programmable delay generator and receiving an output from the programmable delay generator for providing a value corresponding to the measured chip specific delay element timing, the characterization circuit being enabled by a control signal from the analyzer during a setup phase of the measurement cycle thereby enhancing the accuracy of the measurement for both skew measurement and timing parameter characterization.

Abstract: Synchronization errors in a received pulse train are detected by detecting rising or falling transitions in the pulse train, generating numbers in a repeating cycle having a length corresponding to the pulse rate, selecting the number generated when each transition is detected, and performing a predetermined operation on the selected numbers. The predetermined operation may include, for example, comparing the average values of the selected numbers in successive groups of transitions. Alternatively, the predetermined operation may include taking a difference between consecutively selected numbers to measure pulse widths in the pulse train. Synchronization error detection can be used to supplement data error detection and correction methods such as forward error correction and cyclic redundancy checks.

Abstract: A communication system comprising a transmitter that is adapted to transmit a data signal that is broken into a plurality of time slots. The transmitter inserts communication data into a subset of the plurality of time slots and to create null data representative of information about the communication system. The null data is inserted into a subset of the plurality of time slots not occupied by communication data. A communication system comprising a receiver that receives a data signal that is broken into a plurality of time slots. The receiver identifies correlation peaks in the data signal that correspond to a subset of the plurality of time slots, the subset of the plurality of time slots including null data representative of information about the communication system. The receiver may associate logical values with the correlation peaks and decode the logical values to obtain the information about the communication system.

Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.

Abstract: In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

Abstract: A block synchronization detection apparatus and method. Block synchronization for discriminating one error correction code (ECC) block from another is detected, even when a first sector of the ECC block is not detected in a system having a decoder that decodes an ECC in units of ECC blocks. The block synchronization detection apparatus includes an operator performing an operation on a predetermined last sector number, an n-th sector number, and an (n?1)-th sector number contained in a block, based on a predetermined operation relation; and a comparator comparing a result of the operation output from the operator with a predetermined threshold value and outputting the result of the comparison as a block synchronization signal.

Abstract: An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.

Abstract: A code sequence start position detection method and apparatus, and a decoding method and apparatus, which can quickly detect the start position of a code sequence by a simple processing arrangement, and can decode the code sequence on the basis of the detected start position, are provided. In order to detect a start position of a cyclic code sequence with a code length n, the cyclic code sequence with the code length n is input in turn, and a multiplier g, register r, and adder+generate a syndrome for a coded word from the first start position ci?1 (i=1, 2, . . . ) to the first end position ci?1+n in the register r. A multiplier w and adder+correct the generated syndrome using data based on a coded word which is stored in an n-bit buffer and starts from the second start position ci+n, and a NOR detects the start position of the cyclic code sequence with the code length n on the basis of the modified syndrome.

Abstract: A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.

Abstract: A signal constellation is optimized for trellis coded modulation in fast fading channels, where the receiver does not have perfect knowledge of the channel parameters. Specifically, the signal constellation is partitioned into 2n mutually exclusive subsets, each preferably defining two points. Points within each subset are separated from one another by a distance between conditional distributions, preferably a Kullback-Leibler (KL) distance. For a block m=k1+k2 of information bits input into a trellis coder 30, the k1 bits are trellis encoded into n bits (n>k1) and used to select a subset of the constellation. The k2 bit(s) is/are used to select a particular point within the subset. Because the inter-subset distance between points is a KL distance that is effectively greater than a Euclidean distance, error at the receiver is substantially reduced, especially at higher SNR. Using a KL distance ensures statistics of channel fading are inherent within the signal constellation.

Abstract: A data recovery device for precisely recovering a transmission signal even if the signal having phase variations is provided. The device comprises a demodulator for demodulating a transmission signal, a plurality of symbol recovery units, each generating a corresponding synchronous signal and a lock signal, wherein the lock signals are selectively enabled to select one of the synchronous signals, based on pattern variations of the transmission signal detected by the symbol recovery units, and a data decision unit for performing a data recovery operation using the selected synchronous signal to recover original data of the transmission signal.

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Abstract: The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiver circuitry. Data generated by a BERT is transmitted in an electrical form to a DUT and a master device. The DUT transmits data received in an electrical form to the master device in an optical form and the master device transmits data received in an electrical form to the DUT in an optical form. The master device and the DUT then transmit data received in an optical form back to the BERT in an electrical form. The data received from the DUT and the master device, respectively, is separately tested for bit errors. Do so enables to calculation of bit error rates for two distinguishable data paths through the DUT.

Abstract: A data transmission system is formed by a transmitter (50) for processing useful data for the purpose of forming series of information signals, and a receiver (51) for receiving and processing the transmitted series of information signals. In this system, integrity verification is provided for conditionally producing an error indication for the transmitted series of information signals whereby the transmitted series of information signals can be validated even in the case where the error indication appears. Thus, it is possible to transmit image data in a system that has a small bandwidth.

Abstract: In a data transfer apparatus 10, first, second, third data transmitters 141, 142, 143 are located in a data transmission device 11. Data which must not be influenced by delay of transmission timing of the other data are stored in first, second, third data transmitters 141, 142, 143. The data selector 16 selects these at a predetermined order or frequency to be transmitted to a data reception device 12. As a result, when an uncorrectable trouble is detected by a trouble detecting section 27, a re-issue instruction 21 is issued at a predetermined timing based on information stored in an information round robin section 36. The corresponding data from the corresponding data transmitter 141, 142, or 143 is selected by the data selector 16 and then re-sent.

Abstract: A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control of the transmission medium on which the data is to be transmitted. The refetch logic changes sources and propagates to the link controller data from a second source if necessary. At the same time, the refetch logic also causes the link controller to discard the first packet and generate a second packet from data provided by the second source.

Abstract: A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element.

Abstract: Data synchronization detection is provided between data identification and code demodulation in a data reproduction system, which performs data synchronization detection using code-modulated data. A specified bit pattern generated in a data codeword is calculated in each phase (bit), using a specified bit sequence pattern that is not generated in a specified phase of the data codeword. For example, a specified bit sequence pattern is generated only in a specified phase of the codeword). The positions of the data codeword partitions are thereby identified. Scrambling is then applied to the write data as required in order to ensure accurate synchronization detection.

Abstract: An EFM data decoding method and apparatus thereof for optical disk system is provided. According to the method, a 14-bit data complying with the EFM modulation criteria but failing to correspond to a 8-bit data based on an EFM decoding table is transformed successfully by looking up an expanded EFM decoding table. The expanded EFM decoding table includes probable 8-bit data corresponding to the erroneous data complying with the EFM modulation criteria. Reliability of data reading is thus enhanced in the present invention.

Abstract: Systems, methods, and computer program products for deleting objects from device stores without deleting corresponding objects from one or more synchronization partners. A device has a device sync module for each synchronization partner and each device sync module maintains tracking data. Alternatively, a single device sync module manages the tracking data of each synchronization partner. When an object does not meet parameters of a synchronization filter, a soft delete request is made to the wireless device. A sync manager receives the soft delete request and determines from the other device sync modules that have registered with the sync manager whether they continue to synchronize the object. If none of the other device sync modules protest, the object is deleted. If one of the device sync modules objects to the delete request, then the delete is denied. The tracking data for all of the device sync modules is appropriately modified.

Abstract: User information is recorded in each physical sector of an information storage medium in such a style after it is modulated according to a predetermined modulation rule. The physical sector is comprised of plural sync codes. The sync code contains a common fixed code region and variable code regions which are different depending on each sync code. The fixed code region has a sync position detecting code and this code includes a pattern in which “k+2” “0”s continue and a pattern in which 2 “0”s continue.

Abstract: Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.

Abstract: In order to precisely detect latent defects where a data-synchronizing signal is to be stored despite changes in the rotation of an information storage medium, a region data detection is used during a defect detection mode that is longer in the back-and-forth direction than a data-synchronizing signal used during a normal operation mode. The data detection region may be increased by the amount of change in the rotation. Thus, latent defects that may, due to a change in the rotation of the storage medium, come into agreement with the position of a data-synchronizing signal utilized during a normal mode of operation may be reliably detected, maintaining a high precision by taking a change in the rotation of the storage medium into consideration.

Abstract: An apparatus for monitoring asynchronous transfer mode cells in the communication system is proper for recognizing state information of asynchronous transfer mode cells transceiving between a base transceiver station and a base station controller. Accordingly, the apparatus enables to monitor the contents of the cell by comparing VPI/VCI of the ATM cells inputted to the multiplexing/demultiplexing part to the other VPI/VCI latched hardware, have the cell bus RX I/F count the number of the error-occurring ATM cells by carrying out header error checks of the ATM cells inputted to the cell bus RX I/F itself, and find out how long the cell transferring time takes for transceiving loop is found out by transceiving the test ATM cells between the multiplexing/demultiplexing part being the ATM low rate subscriber multiplexing/demultiplexing board assembly (ALMA) and the base transceiver station.

Abstract: An optical disk can detect reliable address data without the need of checking the validity of synchronous detection of segment numbers. The optical disk has one or more tracks, and address data is arranged in a distributed manner on the tracks. A generating polynomial that generates an error detection code of a segment number included in the address data, which represents location information in the disk rotatory direction, is made different from a generating polynomial that generates an error detection code of a track number included in the address data, which represents location information in the disk radial direction.

Abstract: A system and method is provided for using phase adjustment in non-causal channel equalization in a communications system. The method comprising: receiving a serial data stream input; comparing a bit value in the serial data stream determined at a first phase with respect to a clock, to a bit value determined at a second phase; determining the optimal phase for the determination of bit values; and, using the optimal phase to determine subsequently received bit values. Typically, the serial data stream is encoded with forward error correction (FEC). Then, the method further comprises: FEC decoding the bit values determined at a plurality of phases. Determining the optimal phase for the determination of bit values includes calculating an error rate associated with the phases and, defining the optimal phase as the phase associated with a low error rate.

Abstract: An asymmetric error correction apparatus and method, and clock recovering apparatus and data recovering apparatus for a system for reading data from an optical recording medium such as a CD or DVD that has a multi-level input signal and irregular characteristic of zero-crossing transition. The signal inputted from the optical recording medium is digitized, and a zero-crossing detector extracts four sequential samples and detects a zero-crossing point from the two intermediate samples. An asymmetric error detector judges an asymmetric state and asymmetric polarity of the digital signal from a sum of the two side samples among the four samples if the zero-crossing point is detected. A correction section accumulates the judged asymmetric polarities, judges an asymmetric error of the digital signal if the accumulated value exceeds a predetermined threshold, and corrects the asymmetric error of the read signal caused by an inaccurate pit length.

Abstract: A test data generating system and method to conduct high-speed operation (actual operation) test of an LSI using a tester. The system converts existing simulation data to high-speed operation verifying test data which is formed to obtain a predetermined output expectation value after a clock signal is stopped for a predetermined period. The test data generating system includes a selecting device to select first output expectation values from simulation data and an inserting device to insert output expectation values, which are identical to a predetermined number of the first expectation values, after the first output expectation values. The system also inserts an input pattern, which is identical to a predetermined number of the input patterns, after the input pattern corresponding to the first output expectation value.

Abstract: The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Abstract: A path error monitoring method is provided for monitoring for an error in a communication path in a synchronous network by using an error detection code inserted into a first predetermined byte in the overhead of transmitted information. The method includes the steps of: performing an error detection code operation for a predetermined range of the transmitted information in a sender side; inserting the obtained error detection code into a second predetermined byte different from the first predetermined byte in the overhead of the transmitted information and sending the inserted transmitted information; performing an error detection code operation for a predetermined range of the inserted transmitted information received in a receiver side; and monitoring for an error in a communication path between the sender side and the receiver side by comparing the obtained error detection code with the second predetermined byte in the inserted transmitted information.

Abstract: A semiconductor apparatus is composed of a signal providing circuit and a data analyzer. The signal providing circuit provides an input signal set including at least one input signal. The data analyzer outputs a digital result signal in synchronization with a clock signal. The data analyzer inverts the digital result signal at a timing indicated by the clock signal while the input signal set is in a predetermined state, and does not invert the digital result signal while the input signal set is not in the predetermined state.

Abstract: A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality of deskew subsystems. The deskew controller automatically computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.