Abstract: A data dependent descrambler for a communications channel that receives a scrambling seed and a scrambled user data sequence with N symbols each with M bits comprises a first decoder that analyzes adjacent symbols of the scrambled user data sequence, that performs G-constraint decoding on the adjacent symbols when a first of the adjacent symbols is an all-one symbol and that does not perform G-constraint encoding when the first of the adjacent symbols is not an all-one symbol. A first descrambler communicates with the first decoder and generates a user data sequence based on the scrambled user data sequence and the scrambling seed.

Abstract: Provided is a quantum cryptography communication apparatus capable of preventing a go photon pulse from being phase modulated and also capable of freely selecting any repetitive frequency of a light source.

Abstract: Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination.

Abstract: Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically and automatically, to provide accurate and high performance memory operations. For example, timing settings for the control signals can be determined such that data written/read from the memory are accurate. The timing setting can also be changed to provide faster memory operations while still providing accuracy. A feedback system using a control block and a dummy mimicking concept are also provided.

Abstract: A communications line monitoring system of the present invention comprises a plurality of relay apparatus and a communications line monitoring apparatus for monitoring a line quality of a communications line of relayed data, and each of the relay apparatus comprises error detecting unit for detecting errors in received data, previous error detection determination unit for determining whether or not error detection has already been performed in other apparatus based on previous error detection information of the received data, and initial error detection process unit for, only when an error is detected and the error was undetected in other apparatus, autonomously notifying error detection information to the communications line monitoring apparatus, and for adding previous error detection information to data for transmission.

Abstract: In a quantum key distributing method of the present invention, a communication apparatus on a reception side performs error correction using parity check matrixes for an LDPC code that have an extremely high error correction ability. In the quantum key distributing method of the present invention, a cyclic code syndrome generated by a communication apparatus on a transmission side and an estimated cyclic code syndrome generated based on an estimated word after error correction are compared to perform error detection for the estimated word.

Abstract: A method is provided for formatting a message, with a first plurality of bits forming a data component, and a second plurality of bits forming a reserved component, for transmission in a vehicle. The method comprises the steps of calculating an initial checksum from the data component, calculating a revised checksum at least from the initial checksum, and storing the revised checksum in the reserved component. The number of bits in the reserved component is less than the number of bits in the data component.

Abstract: The present invention relates to a system and an apparatus for synchronization between heterogeneous periodic clock domains, a synchronization failure detecting circuit, and a data receiving method. The synchronization system between heterogeneous periodic clock domains including a sender and a receiver operated according to heterogeneous periodic first clock and second clock, respectively, includes: a sender that outputs a prediction clock obtained by delaying the first clock for a first time; and a receiver that predicts success and failure of synchronization between the first clock and the second clock by using the prediction clock and selectively delays the second clock for a second time according to the predicted results to synchronize the second clock with the first clock.

Abstract: Data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a data input, a data output and a processing path arranged between the data input and the data output. The processing path comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal; and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_OK primitive (reception with no error primitive) and sets a error flag to report to the application layer of the receiver to eliminate the interference.

Abstract: A method is provided of data storage by encoding a bit stream on a surface. The method involves printing coded data on the surface which encodes the bit stream, and printing alignment data on the surface which is indicative of a position of the coded data on the surface. The alignment data has a first registration structure indicative of a plurality of reference points indicative of a position of the coded data in an alignment direction, and a second registration structure indicative of a plurality of reference points indicative of a position of the coded data in a direction perpendicular to the alignment direction.

Abstract: An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at that module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at that module, indicate to the other module that that module is ready to exit reset mode and exit the reset mode when the other module has also indicated that the other module is ready to exit reset mode.

Abstract: A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are successively transferred to each of a plurality of serial transfer channels that a high-speed serial transfer device has. A basic pattern setting unit sets a basic pattern while considering a byte order method and an RD value of code conversion in the high-speed serial transfer device. A basic pattern resetting unit resets the basic pattern in accordance with a channel usage method of a bit transfer order in the high-speed serial transfer device. A basic pattern rearranging unit performs rearrangement such that the basic pattern is transferred to each of the channels in accordance with the number of used channels and a channel usage method such as bit transfer order in the high-speed serial transfer device.

Abstract: A bit error probability (BEP) estimation method includes de-shaping a coded block to obtain a channel hard output block comprising a header hard output and at least one data hard output, de-puncturing and decoding the header hard output to obtain a decoded header part, determining whether the decoded header part has errors, selecting the decoded header part or a decoded whole block as a selected part based on the determination result, wherein the decoded whole block comprises the decoded header part and a decoded data part obtained by de-puncturing and decoding the data hard output, re-encoding the selected part to obtain a re-encoded decision, and comparing the re-encoded decision to the header hard output or the channel hard output corresponding to the selected part to obtain the BEP of the coded block. A receiver employing the BEP estimation method is also provided in the invention.

Abstract: Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.

Abstract: PCR jitter is improved when writing an input stream TS having a packet with a PCR in a memory 10 and reading it at a high speed. An oscillator 44 oscillates a local clock signal having a frequency of a reference clock for the input TS and a counter 46 counts the local clock signal. When a PCR detection section 38 detects the PCR in the input TS, a latch circuit 42 latches a counted value of the counter and a PCR exchange section 40 exchanges the original PCR with a result of subtracting the latched count value from the PCR of the input TS.

Abstract: Systems and methods for synchronizing redundant data in a storage array are disclosed. In accordance with a method, a pointer indicating the amount of data synchronized between a first storage resource to a second storage resource may be maintained and a power event may be detected. In response to the detection of the power event, an attempt may be made to flush a write cache associated with the second storage resource to transfer data from the write cache to a non-volatile storage area of the second storage resource. A determination may be made whether the attempt to flush the write cache is successful. In response to determining that the attempt to flush the write cache is successful, a flag may be set to indicate that the pointer accurately indicates the amount of data mirrored from the first storage resource to the non-volatile storage area of the second storage resource.

Abstract: The invention relates to a system and a method for transmitting telegrams. The system has at least one first communication means provided for sending telegrams and at least one second communication means provided for receiving telegrams, with a telegram having a check value that can be determined from a useful data component of the telegram, with the first communication means having a first telegram counter provided for assigning a count value to a telegram in accordance with a send sequence. To improve error detection during the transmission of telegrams it is proposed that the count value for determining the check value be a constituent of the useful data component is, that information signaling a change in the count value be a constituent of the useful data component when the telegram is transmitted, that the second communication means have a second telegram counter, and that means be provided for synchronizing the first and second telegram counter.

Abstract: A debug network on a multiprocessor array having multiple clock domains includes a backbone communication channel which communicates with information nodes on the channel. The information nodes store and access information about an attached processor. The nodes are also coupled to registers within the attached processor, which operate at the speed of the processor. A master controller solicits information from the information nodes by sending messages along the backbone. If a message requires interaction with a processor register, the node performs the action by synchronizing to the local processor clock.

Abstract: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.

Abstract: The analyzer according to the present invention is an analyzer having a scan test function, and including scan paths each having flip-flops which function as a shift register when a scan test is performed, and a switching unit operable to switch between a first connection state, and a second connection state where the scan paths are connected in series to each other and further an output from the last stage of the scan path is connected to the input of the first stage of the scan path.

Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.

Abstract: Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.

Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: A testing circuit includes a signal generator operative to provide a control signal in response to a reference clock signal. The control signal may include both alignment and timing information operative to synchronize the timing and output of the signal generator with a device under test. A clock recovery instrument is electrically coupled to the signal generator. The clock recovery instrument generates the reference clock signal in response to a clock signal from the device under test. The reference clock signal is synchronized with the clock signal from the device under test such that signal generator operation is synchronized with the device under test independent of the behavior of the device under test.

Abstract: A system, method, and processor executable instructions to isochronously communicate in standard USB mode laser printer scan data from a host computer to a laser printer. The host computer transmits a data stream that includes data packets having laser printer scan data, error detection information, and correction packets such as parity packets for use to reconstruct packets having an error. The laser printer receives the data stream, processes the error detection information, data packets and parity packets, and provides a continuous stream of laser printer scan data for printing.

Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

Abstract: A mobile station device that communicates with a base station device, including: a downlink synchronization error detecting portion that detects the occurrence of a downlink synchronization error from the measurement result of a transmission signal of the base station device; a synchronization monitoring portion that sets information showing the occurrence of a downlink synchronization error into a random access channel based on the downlink synchronization state or both the downlink and uplink synchronization states of the mobile station device; and a downlink synchronization error notifying portion that transmits the random access channel to the base station device.

Abstract: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock signal, and an error detection-&-correction circuit configured to detect and correct an error in data stored in the flip-flops, and to produce one of the error-detection signals indicative of the detection of the error upon the detection of the error.

Abstract: A terminal device includes: a time information receiving unit which receives measured time and an estimated error of another terminal device; an estimated error calculating unit which calculates an error containing the estimated error of another terminal device received by the time information receiving unit as an updating-use estimated error; and a time updating unit which, when the updating-use estimated error calculated by the estimated error calculating unit is smaller than an estimated error stored in an estimated error memory unit, stores the updating-use estimated error calculated by the estimated error calculating unit in the estimated error memory unit thus updating the estimated error stored in the estimated error memory unit, and adjusts a measured time measured by a time measuring unit in response to the measured time of another terminal device received by the time information receiving unit.

Abstract: First, a yield is calculated by employing conventional SSTA. Next, an independent LL set is determined, the independent LL set being a subset having sets of delay element sets that only include gates and nets not being shared by two or more paths. Next, a yield is calculated by employing SSTA while using only the independent LL set. Thereby, it is understood that the actual yield is between the yield obtained by employing the conventional SSTA and the yield obtained by employing the SSTA using only the independent LL set.

Abstract: Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.

Abstract: To reduce pseudo errors. A stationary signal is propagated through the circuit to be checked. A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register. From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked. A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values “1” and “0” of the stationary signal. It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated. Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer, thereby reducing pseudo errors.

Abstract: A method for detecting an erroneous sequence number in a status report in a wireless communications system includes receiving a status report sent from a receiver of the wireless communications system, detecting whether a negatively acknowledged sequence number is within a range that is larger than or equal to the sequence number following the sequence number of the last in-sequence acknowledged packet and smaller than the sequence number of the next packet to be transmitted for the first time, and detecting that the status report includes an erroneous sequence number when a negatively acknowledged sequence number is not within the abovementioned range.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.

Abstract: A method for puncturing a low density parity check (LDPC) code that is decoded through a parity check matrix expressed by a factor graph including check nodes and bit nodes connected to the check nodes through edges. The method includes classifying the bit nodes mapped to a parity part of a codeword into hierarchical groups according to their decoding facilities when the bit nodes are punctured, determining puncturing order of the groups, and sequentially performing puncturing on the bit nodes from a bit node belonging to a corresponding group according to the puncturing order of the groups to acquire a codeword with a desired coding rate.

Abstract: According to methods and apparatuses for performing error detection and error correction for a synchronization frame in embodiments of the present invention, a transmitter acquires a transmitter check sequence according to contents of a synchronization frame sequence; and a receiver acquires a receiver information sequence related to the check sequence. When performing error detection, the receiver acquires a receiver check sequence according to the receiver information sequence and a generator polynomial and determines whether the synchronization frame transmission is valid according to the receiver check sequence and the transmitter check sequence; when performing error correction, the receiver acquires a syndrome sequence according to the receiver information sequence, acquires an error pattern according to the syndrome sequence and acquires a result of error correction according to the error pattern and the receiver information sequence.

Abstract: A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between a data transmitter and a data receiver, the data transfer method including: transferring the data flowing in the serial bus in the slave unit from the data transmitter to the data receiver without performing an error check or error correction; performing an error check of the data in a circuit provided in the slave unit aside from a circuit in which the data flow; and informing a result of the error check to the master unit individually by the slave unit, which has performed the error check of the data.

Abstract: An agent of a storage area network generates a first checksum value for a first set of zone configuration data used to at least initially configure the storage area network. At a later time, after a potential change to the first zone configuration data of the storage area network, the agent generates a checksum value based on current zone configuration data presently used to configure the zone in the storage area network. The agent then compares the first checksum value and the second checksum value to identify whether there has been a change to the first zone configuration data. That is, if the first checksum value does not equal the second checksum value, the agent flags that there has been a change to zone configuration data of the storage area network. Users can control behavior of zoning importation and activation depending on whether current zone configuration data has been changed.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

Abstract: For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is interpreted as an error in case the derived value does not substantially match with the corresponding value of the arbitrary test signal.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A system and method of widening the synchronization range for a discrete multitone multicarrier single pilot tone system includes detecting a first phase error in a received pilot tone; detecting a second phase error in a received second two bit constellation data channel; converting the second phase error to a first quadrant angle between 0-90° and combining the first phase error and the converted phase error to obtain the actual phase error up to and beyond 360°.

Abstract: A data transmitting/receiving system adds identifying information to a data packet based on characteristics of the data. The identifying information can be a data type of a payload data of an IP/UDP/RTP packet and/or a temporal data sequence of the payload data. The IP/UDP/RTP packet added with the identifying information is segmented into an IP/UDP/RTP header and IP/UDP/RTP data. The segmented IP/UDP/RTP header and the IP/UDP/RTP data can be transmitted through different channels. A receiver sends retransmission control information based on the added identifying information extracted by the receiver, the retransmission control information providing retransmission time and priority information. A transmitter retransmits reception error occurring IP/UDP/RTP data according to the retransmission control information received by the transmitter.

Abstract: The present invention is provided for producing check data or recovery data in a disk array. According to the present invention, a plurality of buffers receives and stores the data respectively for a plurality of operation units to perform operations to produce check data. An output selector selects one of the buffers and sends the check data to the coupled disk drive. When recovering the data in a disk drive, by using the buffers coupled to the other disk drives, the data or the check data stored in the other disk drives are sent to the operation units to perform operations on the data and the check data to produce recovery data. The recovery data is then sent to the disk drive to be recovered by selecting the buffer coupled to the disk drive to be recovered via the output selector. In addition, the buffers can be coupled to a plurality of input selectors, which are used for selecting to send data in one of the buffers to the coupled operation units.

Abstract: A communication control apparatus transmits data to an other communication control apparatus and receives a notification as to whether the data has normally been received or not from the other communication control apparatus. The communication control apparatus includes setting changing means for changing setting of a transmission circuit when reception error which is a notification that the data has not normally been received is received from the other communication control apparatus.

Abstract: A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The particular buffer into which the memory device signal is latched is determined by a write pointer, which is incremented by the first clock signal. The outputs of the buffers are applied to a multiplexer, which is controlled by a read pointer to couple a memory device signal from one of the buffers to the memory device. The read pointer is incremented by a second clock signal having a timing that is adjustable and may be different from the second clock signal used to increment the read pointer in a clock domain crossing circuit for a different memory device signal.