Abstract: An integrated circuit precharges a node 6 to a precharge voltage using precharging circuitry 4. During a discharge phase discharging circuitry 8 selectively discharges that node 6 is to represent a data/signal value. Sensing circuitry 10 detects a discharge characteristic to identify the data/signal value being represented. During the subsequent precharging operation of the node 6 back to the precharge voltage, validating circuitry 12 detects a precharge characteristic, such as the precharge current, the charge transferred, changes in the node voltage or a like, and compares this to the detected discharge characteristic corresponding to the data/signal value sensed by the sensing circuitry. If there is a mismatch, then an operation error signal is generated. The operation error signal may be used to adjust operation parameter, such as the operating voltage/frequency, the timing of the operation of a portion of the integrated circuit or another parameter.

Abstract: A control unit extracts partial information containing embedded information from a partial area of a content, and controls decoding of the embedded information. A decoding unit performs a decoding process of decoding a plurality of code words contained in the embedded information from the partial information. When the decoding process is successfully performed, the decoding unit notifies the control unit of completion of the decoding process so that each of the control unit and the decoding unit perform a parallel processing in an asynchronous manner. The control unit repeatedly extracts the partial information and sends extracted partial information to the decoding unit until the decoding process is successfully performed.

Abstract: A node comprises a host computer operable to execute application tasks and to transmit data; a local time-triggered Ethernet switch operable to enforce temporal constraints on time-triggered data; and a time-triggered Ethernet controller coupled to the local time-triggered Ethernet switch and operable to be coupled to a time-triggered Ethernet switch in each of a plurality of other control nodes. The time-triggered Ethernet controller is further operable to communicate with the plurality of other control nodes to synchronize a local clock to establish a global time base and to provide a signal to the host computer for the host computer to synchronize execution of the application tasks by the host computer with the execution of application tasks in each of the plurality of other control nodes.

Abstract: A cluster comprises a plurality of end nodes that communicate with one another over at least one communication channel. Each end node is assigned a time slot for transmission of frames; wherein each node comprises a local guardian configured to prevent transmission of timing-related frames sourced from the respective end node. The cluster also comprises a special node that communicates with the plurality of end nodes, wherein the special node establishes a time base and sources timing-related frames to the plurality of end nodes. The transmission schedule includes at least one common scrubbing time slot during which each of the plurality of end nodes is configured to generate a timing-related frame. The special node is configured to determine if the local guardian in any of the plurality of nodes failed to prevent transmission of the respective generated timing-related frame during the common scrubbing time slot.

Abstract: A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for resolving a data conflict. These mechanisms and methods for resolving a data conflict can enable an improved user experience, increased efficiency, time savings, etc.

Abstract: A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant.

Abstract: A method of communicating information includes receiving a data stream from the host computer, the data stream including a plurality of bytes, one or more bytes of the plurality of bytes being associated with obtaining medical related information, and parsing one or more bytes in the data stream at the sensor device. As a result of parsing the one or more bytes, the method includes identifying a type of medical related information, obtaining the medical related information from the sensor device, and sending the medical related information to the host computer. The parsing of the one or more bytes in the data stream is performed using a single pass through the data stream, one or more data validity checks being performed during the single pass, the medical related information being obtained after the data stream is parsed in the single pass through the data stream.

Abstract: The packet interleaving method includes selecting successive input sets of consecutive input packets (X1 . . . XNin) received from a forward correction module (14), each input packet (Xj) being a vector of constellation points of a predetermined constellation diagram. For each input set, it further includes generating an output set of output packets (O1 . . . ONout), each output packet (Om) being a vector of constellation points, by distributing the constellation points of each input packet (Xj) of the input set, and sending the output packets (O1 . . . ONout) of the output set to a modulator (18). The input set including Nin input packets (X1 . . . XNin) and each of the Nin input packets (X1 . . . XNin) including a same number Lin of constellation points, the number Nout of output packets in the output set is related to Lin by the relation Lin=A×Nout, where A is a fixed whole number.

Abstract: According to methods and apparatuses for performing error detection and error correction for a synchronization frame in embodiments of the present invention, a transmitter acquires a transmitter check sequence according to contents of a synchronization frame sequence; and a receiver acquires a receiver information sequence related to the check sequence. When performing error detection, the receiver acquires a receiver check sequence according to the receiver information sequence and a generator polynomial and determines whether the synchronization frame transmission is valid according to the receiver check sequence and the transmitter check sequence; when performing error correction, the receiver acquires a syndrome sequence according to the receiver information sequence, acquires an error pattern according to the syndrome sequence and acquires a result of error correction according to the error pattern and the receiver information sequence.

Abstract: The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The checker circuit is characterized by a compact circuit design that is associated with reduced susceptibility to circuit errors and a significantly reduced spatial requirement. The invention also relates to a method for checking the execution of the handshake protocol.

Abstract: A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit.

Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Abstract: An apparatus for efficiently transmitting and receiving uncompressed AV data by using UEP during high-frequency wireless communication, as well as a transmission frame structure to which the UEP is applied are provided. A method of transmitting uncompressed AV data includes determining whether a transmission efficiency of uncompressed AV data drops below a threshold while the uncompressed AV data is transmitted; deciding whether to use a UEP mode if it is determined that the transmission efficiency has dropped below the threshold, the UEP mode indicating a manner of dividing bits, the bits constituting the uncompressed AV data, into significant bits and non-significant bits; and retransmitting the uncompressed AV data by using the UEP mode based on decision regarding use of the UEP mode.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A method for generating a data frame for data transmission includes using a processor to generate a first padding field. The method also includes using the processor to generate one or more parity bits by encoding an input comprising the first padding field, a syncmark and data to be transmitted. The method also includes using the processor to add the one or more parity bits to the data frame. The method also includes using the processor to add a second padding field after the one or more parity bits.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.

Abstract: A terminal device includes: a time information receiving unit which receives measured time and an estimated error of another terminal device; an estimated error calculating unit which calculates an error containing the estimated error of another terminal device received by the time information receiving unit as an updating-use estimated error; and a time updating unit which, when the updating-use estimated error calculated by the estimated error calculating unit is smaller than an estimated error stored in an estimated error memory unit, stores the updating-use estimated error calculated by the estimated error calculating unit in the estimated error memory unit thus updating the estimated error stored in the estimated error memory unit, and adjusts a measured time measured by a time measuring unit in response to the measured time of another terminal device received by the time information receiving unit.

Abstract: A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present.

Abstract: Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first CSUM; error checking the received data block in a second sequence using a second polynomial, using the first CSUM as a second predetermined initial error checking state, producing a second CSUM; comparing the second CSUM to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial.

Abstract: An RDS compatible receiver has a demodulator which demodulates RDS data, a register which converts the demodulated RDS data to block data and outputs the block data, an offset generating unit which predicts and outputs an offset word of the block data based on values of a pattern match flag signal and a synchronization flag signal, an error correction processing unit which performs error correction of the block data using the predicted offset word, compares the number of error corrections with a predetermined correction threshold, determines whether the predicted offset word is right or not based on the comparison result, and outputs the pattern match flag signal based on the determination result, and a synchronization determining unit which detects whether or not the predicted offset word determined to be right matches a predetermined offset sequence pattern, determines whether RDS block synchronization is established or not, and outputs the synchronization flag signal based on the determination result.

Abstract: A system, computer program, and/or method for encoding data that can correct r/2 errors. The original symbols are transformed using a Fourier transform of length p. Generator polynomials are used to encode the p blocks separately, and an inverse Fourier transform is applied to obtain the redundant symbol. In a decoding system, Fourier transforms are applied to every set of p consecutive symbols of the received vector, to obtain p blocks of symbols which in total have the same size as the received vector. Next, a syndrome calculator is applied to each of these blocks to produce p syndromes. The syndromes are forwarded to a Berlekamp-Massey unit and an error locator polynomial is decimated into p parts and a Chien search is applied concurrently. A Fourier transform of length p is applied to values calculated by the Chien search, and the positions of the zeros obtained are error positions.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: A wireless communication system includes a first communication station configured to operate according to a first communication protocol, and a second communication station capable of operating according to both the first communication protocol and a second communication protocol. When the second communication station transmits a packet according to the second communication protocol, at least a first signal field compliant with the first communication protocol and a second signal field compliant with the second communication protocol are attached to a header of the packet, and the first signal field includes a parity bit. When the second communication station receives a packet from another communication station, the second communication station performs a parity check on the first signal field of the packet, and when no parity error is detected, the second communication station further checks whether content of the first signal field is compliant with the first communication protocol.

Abstract: A digital broadcast transmission apparatus includes a Reed-Solomon (RS) encoder to perform RS encoding of data to obtain RS-encoded data formatted in data packets each including a predetermined number of bytes; a sync byte inserter to insert sync bytes indicating a start point of one of the data packets in a predetermined location of the RS-encoded data; an interleaver to interleave the RS-encoded data after the sync bytes have been inserted in the RS-encoded data to obtain interleaved data; and a data stuffer to sequentially insert complete packets of the interleaved data each including the predetermined number of bytes in a field, and insert an initial portion of a final packet of the interleaved data beginning in the field in residual bytes of the field that are less than the predetermined number of bytes.

Abstract: A method for low density parity check (LDPC) encoding comprises concatenating a predetermined number of zero bits to a scrambled input data word to generate a concatenated binary sequence; computing parity bits to be added to the concatenated binary sequence, wherein the computing is performed using an LDPC encoder; producing an encoded codeword that consists of the concatenated binary sequence and the parity bits; and replacing the predetermined number of zero bits in the encoded codeword with a scrambled binary sequence, thereby discarding the zero bits.

Abstract: Systems and a method for storing data are provided. The protected memory system includes a memory array including a plurality of memory modules each separately located with respect to each other and a memory controller configured to receive data to be stored from the data acquisition unit, store the received data in corresponding memory locations in each of the plurality of memory modules wherein the stored data including error checking information, read data from a first one of the plurality of memory modules until a data error is detected at a first memory location, read data from a second memory location of a second one of the plurality of memory modules wherein the data read from the second memory location corresponds to the data read from the first memory location, and replace the data read from the first memory location with the data read from the second memory location.

Abstract: An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.

Abstract: A transformation processing system input data including a data record area for storing target date and a transformation processing identification information record area for storing transformation processing identification information about transformation processing executed upon the target data.

Abstract: The present invention discloses a solution for automatically replacing a media files upon a device able to identify problems with locally stored media files. Initially, an automated process or user of a media playing device can initially identify a media file, which the media playing device is unable to play. The media playing device can be connected to an external device associated with a media store including a set of source media files. The source media files of the media store can be automatically queried for a corresponding one of the detected media file. A copy of a source media file resulting from the query can be automatically conveyed from the media store to the media playing device.

Abstract: A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for resolving a data conflict. These mechanisms and methods for resolving a data conflict can enable an improved user experience, increased efficiency, time savings, etc.

Abstract: A method and apparatus for performing a self-test of a plesiochronous link. A pseudorandom serial bit pattern is generated by the transmitter from a linear feedback shift register (LFSR) based on a primitive polynomial of a specific order and transmitted across a plesiochronous link. Bits of this transmitted pattern are received and deserialized into n parallel bits. In the receiver, given the current n bits in the bit pattern, the next n bits that are expected in the bit pattern are computed in advance. The next n compare bits thus generated are delayed and compared when the next n bits from the transmitted pattern arrive at the receiver and an error is signaled in the case of a mismatch. The method further repeats the receiving, deserializing and computing the next expected bits for each n bits of the received pattern.

Abstract: Methods for detecting and correcting data errors in an RF data link include identifying valid data frames and corrupted data frames by measuring a data corruption level for each transmitted data frame, comparing the measured data corruption level for each corrupted data frame to a data corruption threshold, reconstructing the corrupted data frames having a data corruption level below the data corruption threshold, reconstructing the data block using data from valid and reconstructed data frames, and/or verifying the data in the reconstructed data block.

Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.

Abstract: A system, method, and processor executable instructions to isochronously communicate in standard USB mode laser printer scan data from a host computer to a laser printer. The host computer transmits a data stream that includes data packets having laser printer scan data, error detection information, and correction packets such as parity packets for use to reconstruct packets having an error. The laser printer receives the data stream, processes the error detection information, data packets and parity packets, and provides a continuous stream of laser printer scan data for printing.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A system and method for correcting so-called “lip sync” errors is provided, using a synchronization test signal comprising a video signal including a colorbar signal that is periodically interrupted by a series of consecutive defined black frames and an audio signal comprising a tone periodically interrupted by a period of silence beginning at the same time as the first of the series of consecutive defined black frames. The synchronization test signal is configured to survive encoding, decoding, conversion, and compressing processes used in a typical digital broadcast system environment and thus provide a means of measuring the relative audio and video timing of a processed signal.

Abstract: A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.

Abstract: Obscuring information in messages to be exchanged over a communications network. In one aspect, the information comprises path name information and parameters for use in a Uniform Resource Locator (“URL”). In another aspect, the information comprises links and parameters used in forms, where hidden parameters are removed from a form and used as URL parameters. A compression dictionary is used to create a compressed form of the information. An identifier of the dictionary and an error detection code (such as a checksum) computed over the compressed information are concatenated with the compressed information, and this is encoded for sending on an outbound message. The original information is then recovered from an inbound message which contains the obscured information by reversing the processing used for the obscuring.

Abstract: A memory module having error detection and correction mechanisms. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal. A buffer device for a memory module. A method of operating a memory module. A memory including a plurality of registers arranged in a pipeline for storing a plurality of copies of the input signals and communicating the stored copies of the input signals as an output signal to an external device.

Abstract: Techniques are disclosed for detection of performance conditions in processing systems. For example, a method of detecting a performance condition in at least one particular processing device of a processing system having a plurality of processing devices includes the following steps. Data is input to a data structure associated with the particular processing device, over a given time period. The input data may be a buffer or a bucket. The input data represents data associated with the execution of at least one function performed by the particular processing device. The given time period includes the time period between consecutive heartbeat signals transmitted by the particular processing device. At least a portion of the input data is removed from the data structure associated with the particular processing device, near the end of the given time period. The removed input data is compared to an expected function execution level.

Abstract: A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string corresponding to the transmitted bit string; a storing unit arranged to store an error rate table wherein said received bit string is correlated with an error rate of post-data which is data of one bit or greater received following the received bit string being in error; and an error correcting unit arranged to perform error correcting of the post-data of the received bit string.

Abstract: A method is provided for formatting a message, with a first plurality of bits forming a data component, and a second plurality of bits forming a reserved component, for transmission in a vehicle. The method comprises the steps of calculating an initial checksum from the data component, calculating a revised checksum at least from the initial checksum, and storing the revised checksum in the reserved component. The number of bits in the reserved component is less than the number of bits in the data component.