Abstract: A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.

Abstract: A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.

Abstract: The invention concerns a method for processing a signal using an approximate MAP (maximum a posteriori) algorithm for determining a likelihood ratio ?kX of a set of states X of a lattice at a time k, with each of said states being associated at least one intermediate variable belonging to a group comprising a so-called forward variable and a so-called backward variable, propagated by said MAP algorithm and recursively calculated respectively in a direct orientation and in an indirect orientation at said time k relative to said lattice. The invention is characterized in that said process comprises a step which consists in reducing the number of selected states by said MAP algorithm so as to calculate said likelihood ratio, and, for at least some unselected states, in assigning to said forward variable and/or said backward variable at least one specific value, to calculate an approximate likelihood ratio.

Abstract: The present application relates to a method of at least substantially synchronizing data output from at least first and second graphics cards (1, 2). A synchronization difference between the first graphics card (1) and the second graphics card (2) is determined and a correction signal (41) generated based on the synchronization difference. The correction signal (41) is supplied to the second graphics card and the operating frequency of the second graphics card (2) is adjusted in response to the correction signal (41). The application also relates to a system (100) for processing images.

Abstract: A multi-channel data verifying apparatus and method are provided. The apparatus includes a receiver receiving N data channels and a deskew channel generated by sequentially extracting a predetermined data bit from the each of N data channels, and a deskew channel error detector detecting whether the deskew channel received by the receiver corresponds to an expected deskew channel generated and stored based on the test signal or generated based on the previously received deskew channel. Accordingly, data channels, a deskew channel and the entire data capacity can be verified and thus the cause of a problem in the transmission and reception of multi-channel data can be identified in advance.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and upon signal delay information obtained by static timing analysis (STA), expected value comparison times (strobe times) of a test pattern are extracted, or expected value verification as to whether values of an actually produced signal match the expected values is performed. In this manner, the inventive method allows the test pattern to be prepared with consideration given to variation in the LSI process, temperature, voltage and the like and to constraints of the test apparatus.

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: Systems, methods, and computer program products for deleting objects from device stores without deleting corresponding objects from one or more synchronization partners. A device has a device sync module for each synchronization partner and each device sync module maintains tracking data. Alternatively, a single device sync module manages the tracking data of each synchronization partner. When an object does not meet parameters of a synchronization filter, a soft delete request is made to the wireless device. A sync manager receives the soft delete request and determines from the other device sync modules that have registered with the sync manager whether they continue to synchronize the object. If none of the other device sync modules protest, the object is deleted. If one of the device sync modules objects to the delete request, then the delete is denied. The tracking data for all of the device sync modules is appropriately modified.

Abstract: A method of calibrating once-around and harmonic errors of encoded nips is provided. An encoder with an index pulse is used to measure the velocity and rotation of the driven wheel or idler. The geometry of the drive train and wheel and idler is chosen so that their once around and harmonic frequencies are unique such that no other drive errors will generate these frequencies. The method includes running the idler or wheel at substantially constant velocity for N revolutions. Each index triggers the collection of velocity data, which is averaged for N revolutions. This process detects drive train motion errors that are periodic with respect to the timing of the index pulse (i.e., once per revolution of the wheel or idler). Once the velocity errors have been measured, corrections are made. This method may be incorporated in xerographic machines as part of a setup or calibration procedure.

Abstract: There is provided a threshold voltage control apparatus that controls a threshold voltage for a level comparing section that detects a logic pattern of an input signal by comparing a level of the input signal with the threshold voltage.

Abstract: A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

Abstract: The invention includes a method and apparatus for aligning a plurality of data channels using a deskew bitstream. The method includes receiving the deskew bitstream, identifying an aligned deskew frame by processing the deskew bitstream, identifying a data channel alignment position associated with each of the plurality of data channels by comparing a deskew channel comparison bit from the aligned deskew frame to a data channel comparison bit from each of the plurality of data channels, and selecting the plurality of data channel alignment positions associated with the respective plurality of data channels for aligning the plurality of data channels. The plurality of data channels are aligned in a manner for substantially reducing skew associated with the data channels. The deskew bitstream comprises a plurality of data bits associated with the data channels and a plurality of parity bits generated using at least a portion of the data bits.

Abstract: A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.

Abstract: The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and a library for performing a logic synthesis of the circuit operation information and converting to a net list; and a display unit. The information processor hierarchically arranges statement by statement the circuit operation information that is stored in the storage unit, and then refers to the library, performs a logic synthesis of the circuit operation information that has been hierarchically arranged and converts to a net list. The information processor then detects redundant fault sites, which are sites that are logically redundant from the net list, and displays information showing the redundant circuits that contain the redundant fault sites on the display unit.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: Techniques are disclosed for detection of performance conditions in processing systems. For example, a method of detecting a performance condition in at least one particular processing device of a processing system having a plurality of processing devices includes the following steps. Data is input to a data structure associated with the particular processing device, over a given time period. The input data may be a buffer or a bucket. The input data represents data associated with the execution of at least one function performed by the particular processing device. The given time period includes the time period between consecutive heartbeat signals transmitted by the particular processing device. At least a portion of the input data is removed from the data structure associated with the particular processing device, near the end of the given time period. The removed input data is compared to an expected function execution level.

Abstract: A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous packet transmission unit. The bulk packet generation unit generates a bulk packet (or a control packet) which is a USB packet and has a predetermined structure including a first data area by describing data which is taken as an object of transfer in the first data area. The isochronous packet transmission unit generates an isochronous packet which is a packet in USB isochronous transfer and has a predetermined structure including a second data area by incorporating at least one bulk packet into the second data area, and isochronously transfers the isochronous packet to the mobile telephone over the USB interface.

Abstract: Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage slew, capacitive load, supply voltage or temperature. Error values are generated indicative of error between the measured data points and the full-space polynomial model. The error values are used to partition the modeling space into domains. For at least a given one of the domains, a first polynomial model is generated based on a subset of the measured data points and at least one additional data point determined by interpolation from the measured data points in the subset. Error values are generated indicative of error between the measured data points of the subset and the first polynomial model.

Abstract: A method for recoding an input sequence of words, including assigning a respective bit-grade to at least one of the bits in a first word in the input sequence, deriving candidate words from the first word in response to the respective bit-grade, and inserting one of the candidate words into each of a plurality of candidate sequences, so that each of the candidate sequences contains one of the candidate words. The method further includes adding subsequent words to the candidate sequences, the subsequent words consisting of a further candidate word derived from a further word in the input sequence, computing respective sequence parameters for the candidate sequences, based on a relation between the candidate words and the subsequent words in the candidate sequences, selecting one of the candidate sequences in response to the sequence parameters, and outputting one of the candidate words contained in the selected candidate sequence.

Abstract: The present invention relates generally to a data recovery algorithm and a serial link data receiver adopting the same. The data recovery algorithm includes receiving a serial data stream and a reference clock signal from a transmitting end, generating a plurality of overclock signals based on the received reference clock signal, oversampling the received serial data based on the plurality of overclock signals, and comparing values sampled by the respective overclock signals and outputting the most effective value as a data value that corresponds to the reference clock signal while considering a transition position of a data bit.

Abstract: Systems and methods for maintaining data stream synchronization are provided. A system comprises one or more radio head interface modules and a call processing software module each adapted to communicate with each other. The call processing software module performs modulation and demodulation of voice and data streams using one or more air interface standards. The call processing software module communicates a forward data stream to a first radio head interface module. The forward data stream comprises a plurality of data samples representing voice and data streams and a plurality of fixed synchronization words. When the first radio head interface module does not observe the receipt of a first fixed synchronization word of the plurality of fixed synchronization words word from the call processing software module when expected, the first radio head interface module concludes that it has lost synchronization with the call processing software module.

Abstract: In order to carry out in a communication system (1) a temporal synchronization of clocks in a particularly rapid and efficient manner, a method is proposed which has the following steps: acquiring state values which are dependent on a time base (10); filing each acquired state value at a position in a first list L comprising (k+1) positions, if the acquired state value is smaller than or equal to the (k+1) smallest element of the list L, where k is a predefinable error tolerance; filing the acquired state value at a position in a second list H comprising (k+1) positions, if the acquired state value is greater than or equal to the (k+1) greatest element of the list H; forming a mean value from the (k+1) smallest element of the list L and the (k+1) greatest element of the list H, if the number of acquired state values is greater than or equal to (2k+2); determining a correction value as a function of the mean value; and correcting a current state value of the clocks that are to be synchronized.

Abstract: A method and system for error detection in programs with collective synchronization and/or procedures are provided. In one aspect, the method and system may use interprocedural analysis for matching synchronizations in a program in order to detect synchronization errors, and, if no such errors exist, may determine the synchronization phases of the program. The method and system in one aspect may use a combination of path expressions and interprocedural program slicing to match the synchronization statements that may execute along each program path. If the synchronization matching succeeds, the method and system in one aspect may determine the sets of synchronization statements that synchronize together. A matching failure may indicate the presence of a synchronization error and the method and system in one aspect may construct a counter example to illustrate the error.

Abstract: A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.

Abstract: An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: A method to synchronize Fault Code Memory between at least a first module and a second module in an engine controller unit; each said module in electronic communication with each other and having volatile and non volatile memory; said modules in electronic communication; when compatibility of versions of static fault codes between the modules is established, the first module downloads and saves the static fault code table resident on the second module in nonvolatile memory for access by a diagnostic tool.

Abstract: The present invention offers an advanced control software verification technology, particularly, an assertion-based verification technology, by providing a control microcomputer verification device and vehicle-mounted control device that exhibit improved verification efficiency. Assertion-based verification is performed with a verification device that has a hardware configuration in which the verification device is independent of a CPU core of a microcomputer but operates in parallel with the CPU core of the microcomputer, which sequentially executes control software. The hardware to be employed to achieve the above purpose is a finite state machine based on microprogrammed control. An interrupt factor is branched immediately before an interrupt controller for the microcomputer and used as a transition input. When an abnormal transition is detected, a warning is output to the microcomputer as an interrupt or output to the outside in the form of a signal.

Abstract: A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.

Abstract: A process control system includes a plurality of input/output (I/O) devices and a controller in communication using a bus. Each I/O device has an interface for communicatively linking the I/O device with the bus, and includes a device processor which, upon detection of a potential I/O device fault, severs the communication link provided by the interface with the bus to thereby remove the I/O device from the bus and to prevent the I/O device from keeping other I/O devices on the bus from communicating over the bus.

Abstract: A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: This invention describes a method for a redundancy version implementation of an uplink (UL) enhanced dedicated channel (E-DCH) in mobile communication systems by calculating a redundancy version number (RVN) as a function of a connection frame number (CFN), a maximum number of processed HARQs (hybrid automatic repeat requests) NARQ, and a number of redundancy versions NRV. Instead of signaling a RV parameter outband in UL, the RVN is determined by the network element using simple rules which ensures that the same RVN is never used successively for the same HARQ process, and that all possible RV numbers are used for one HARQ process.

Abstract: Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. A first endpoint may mark the beginning of the synchronization period by specifying a processing point at which other processors and the first endpoint are to coordinate from the perspective of the first endpoint. Synchronization is performed using local state information about the processing state of each endpoint as reported by each endpoint. The first endpoint waits for successful synchronization within a timeout period in accordance with the first endpoint's local state information. If successful synchronization does not occur prior to the timeout period, the first endpoint broadcasts a message with a new synchronization point to other endpoints.

Abstract: An erroneous synchronization preventing device includes a pattern detector detecting a sync pattern from received data with a broader sync window to output a sync detection notice and a sync timing. On receipt of the notice, a packet header detector checks an error in a header field of the received data, and, if detecting no error, outputs a header-normally-received notice, on receipt of which the timing corrector makes the inner timing synchronous with the sync timing to output a timing correction end notice. The mode manager in turn outputs a change notice. The pattern detector then detects the sync pattern with a narrower sync window. Unless the end notice is received within a predetermined period as from receipt of the change notice, a detection period monitor outputs an out-of-synchronism notice. The mode manager then outputs a restoration command for instructing detection of the sync pattern with the broader sync window.

Abstract: Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.

Abstract: A measurement system recovers a clock signal from an applied signal that includes a repeating bit pattern, provides a trigger signal synchronized to occurrences of the repeating bit pattern, acquires a set of data samples time-referenced to the trigger signal, and acquires a set of phase error samples of a phase error signal provided by a clock recovery system, wherein the acquired set of phase error samples is also time-referenced to the trigger signal.

Abstract: The subject invention facilitates the efficient operation of the disassembly of the microprocessor bus by providing an apparatus and method for detecting and correcting a strobe phase inversion and predrive filtering in a 2× source synchronous data transfer bus. Apparatus according to the subject invention detects a data strobe inversion in a source synchronous 2× data bus and corrects for this inversion by reordering the received data as well as filtering predrive effects in real time. Specifically, this apparatus according to the subject invention monitors bus traffic in a multiprocessor environment and correctly captures all double data rate exchanges regardless of the source IC or destination IC in the system.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

Abstract: A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.

Abstract: A serial link system is provided for determining a worst-case cumulative data eye. The system includes a transmitter, a receiver, and a channel between the transmitter and receiver such that data sent by the transmitter is received by the receiver through the channel. The channel includes a plurality of connections including a victim and at least first and second aggressors, with the victim being disposed between the first and second aggressors. The system also includes a controller constructed and arranged to determine a worst case cumulative data eye based on a data pattern of the victim, jitter on the victim, an effect a data and jitter pattern on the first aggressor has on the victim and an effect a data and jitter pattern of the second aggressor has on the victim and to combine the effects of the data pattern of the victim, the jitter on the victim and the effects of the first and second aggressors on the victim into a single pattern to determine cumulative data eye for use in a simulator.

Abstract: A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.

Abstract: A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor.

Abstract: In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Abstract: A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals traversing from one clock domain to another clock domain across a synchronization circuit. The register is programmed with a latency value that corresponds to a correct synchronization timing for the clock domain crossing. Other bit entries in the register provide setting of other debug parameters and indications of monitored results.

Abstract: A clock management system receives an input clock signal having rising edges and falling edges, a first set of data values associated with the rising edges of the input clock signal, and a second set of data values associated with the falling edges of the input clock signal. The clock management system provides a first clock and a second clock in response to the input clock signal. The first clock has a first set of edges that are synchronous with the rising edges of the input clock signal. The second clock has a second set of edges that are synchronous with the falling edges of the input clock signal. The first set of data values are latched in response to the first set of edges of the first clock. The second set of data values are latched in response to the second set of edges of the second clock.

Abstract: There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an oscillating signal corresponding to a given reference signal, a variable delay circuit for outputting said clock signal in which said oscillating signal is delayed, a low-frequency application section for applying low-frequency component of said phase jitter component to said oscillating signal by controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data and a high-frequency application section for applying high-frequency component of said phase jitter component to said clock signal by controlling a delay in said variable delay circuit based on the high-frequency component of said jitter data.