Abstract: A system and method for demultiplexing and distributing transport packets, such as MPEG-2 transport packets, by generating and associating a locally-generated header with each of the transport packets to create a self-contained modified packet which incorporates essential distribution information therein. The method for enhancing transport packet demultiplexing and distribution in a digital transport demultiplexing system that inputs a stream of digital multimedia transport packets is provided. Each of the transport packets includes a packet identifier (PID) to identify the digital program or elementary stream to which it corresponds. Local packet information is generated for each of the transport packets, which is used in identifying and distributing the transport packets. A local header is created that includes the generated local packet information, and the local header is linked to its corresponding transport packet to create a modified transport packet.

Abstract: A diagnostics/prognostics system and related method for collecting and processing data relating to a plurality of subsystems of a dynamic system includes a plurality of sensors, each sensor gathering data and generating a data signal indicative of the health of a corresponding one of the subsystems. In addition, the diagnostics/prognostics system includes a plurality of subsystem modules coupled to corresponding ones of the sensors for generating a subsystem health signal in response to corresponding ones of the data signals. Further, a master diagnostics module is coupled to the subsystems to generate an overall system health signal in response to the subsystem health signals. Preferably, the master diagnostics module includes a memory having an embedded model to facilitate generating the overall system health signal and a related trend analysis.

Abstract: Systems, methods, and computer program products for deleting objects from device stores without deleting corresponding objects from one or more synchronization partners, A device has a device sync module for each synchronization partner and each device sync module maintains tracking data. Alternatively, a single device sync module manages the tracking data of each synchronization partner. When an object does not meet parameters of a synchronization filter, a soft delete request is made to the wireless device. A sync manager receives the soft delete request and determines from the other device sync modules that have registered with the sync manager whether they continue to synchronize the object. If none of the other device sync modules protest, the object is deleted. If one of the device sync modules objects to the delete request, then the delete is denied. The tracking data for all of the device sync modules is appropriately modified.

Abstract: A rolling mill system uses a number of autonomous control units, each associated with one piece of equipment of the rolling mill system. The autonomious control units include data indicating not only their constraints of operation, but also reflecting the constraints of operation of machines to which they are attached and with which they share common operating parameters. An autonomous control unit associated with a machine having operating parameters in common with another machine of the rolling mill system adopts the intersection of the ranges of the machine constraints of the two machines. Machine constraints are preserved to the extent possible as ranges, so as to permit flexibility in selecting and seeking goals by the individual autonomous control units.

Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Abstract: A device using information about the extent of errors in a signal is shown. The device includes an input signal containing at least one constraint and any errors introduced into the input signal during transmission and/or sensing. A detector receives and is responsive to the input signal for generating an error signal containing information about the extent of error and for extracting an information signal from the input signal as an output signal. A control device is operatively coupled to the detector for receiving and responding to the error signal containing information about the extent of errors for generating a control signal used to reduce the extent of errors in the input signal based on information about the extent of errors contained in the error signal. A method for using information about the extent of errors is shown.

Abstract: A circuit comprising a receiver configured to receive a first signal having a first phase, a second signal having a second phase opposite the first phase and an output configured to present either the first or second signals. A state machine may be configured to receive the output of the receiver circuit and to provide a control signal configured to select the first or second signals.

Abstract: Data synchronization detection means 3 is provided between data identification means 1 and code demodulation means 6 of the data reproduction system, which performs data synchronization detection using the code-modulated data itself; a specified bit pattern generated in the data codeword is calculated in each phase (bit), using a specified bit sequence pattern that is not generated in a specified phase of the data codeword, by the conversion law during code modulation (or there is a specified bit sequence pattern that is generated only in a specified phase of the codeword); the positions of the data codeword partitions are thereby identified. Scrambling is then applied to the write data as required in order to ensure accurate synchronization detection. In addition, the data position is specified by detecting the pattern correlation between the PLO_SYNC section and GAP section.

Abstract: An apparatus for detecting a sync signal in a digital data record/replay device having a parallel clock generator, a parallel data generator, and a window unit comprises: a sync signal detector for comparing a pattern matching sync signal output from a sync pattern detector with an output signal of the window unit and detecting a sync signal according to clocks of the parallel clock generator; a latch unit for latching the sync signal detected by the sync signal detector and outputting the sync signal as a sync position signal according to clocks of the parallel clock generator; an identification error correction code (ID ECC) controller for generating an ID ECC control signal according to the sync position signal of the latch unit; an ID ECC decoder for decoding ID areas of parallel data generated by the parallel data generator; and a sync signal checking unit for outputting the sync position signal of the latch unit as a final sync signal and, when errors are detected as a result of the ID ECC decoding, sen

Abstract: Methods and systems are provided for receiving a modulated signal including symbols representing both encoded and unencoded bits from a data (e.g., speech) frame where a received slot is first demodulated and the encoded bits are decoded. The decoded bits are then utilized to constrain demodulation during a second demodulation of a received slot. The encoded bit positions from the constrained second demodulation are, in turn, encoded to generate bit estimates for the received slot. This information is combined with the output of the constrained second demodulation for unencoded bits to provide a received data frame estimate which has been shown to have improved reliability for both encoded and unencoded bits. The methods and systems further provide for recursively repeating the demodulation and decoding steps until a counter expires or a desired reliability is obtained.

Abstract: A sound reproducing system that decodes audio data in a frame with which detection of a syncword fails, if a syncword included in a subsequent frame is detected, if correctness of bit stream information in the subsequent frame is proved, and if no CRC error is detected (when CRC is included). This makes it possible to solve a problem involved in a conventional system in that when a unit frame without an error check pattern is input and a synchronization detector produces a synchronization detection error signal, unpleasant sound interruption can take place even if the audio data is correct, because the correctness of the audio data cannot be checked, and hence the audio data cannot be decoded in this case.

Abstract: A communication processing control apparatus for controlling data transmission between an arithmetic processing control apparatus and a network includes first and second communication processing sections, and a data control section. The first and second communication processing sections are made duplex and inserted into a duplex data transmission route to perform the same processing. The data control section adds CRC data to input data, and outputs the data to the first and second communication processing sections, and simultaneously checks the CRC data contained in output data from the first and second communication processing sections to detect a fault in the first and second communication processing sections.

Abstract: For the purpose of error masking, binary representations of parameter values are precoded at the transmitting end by a linear block code before transmission over a faulty channel, and the redundant information added in this way is not used at the receiving end for error detection within the binary parameter representations, but is utilized in the course of a parameter estimation to improve the quality of the estimated parameter values.

Abstract: In an error detecting method and device for calculating a phase error in a PSK modulated signal having a predetermined modulation phase number, and so configured that a received phase of the modulated signal is mapped on a complex plane by allocating an inphase signal and a quadrature signal generated from the modulated signal as values of the axis of abscissas and the axis of ordinates, and a phase error between the received phase of the modulated signal thus mapped and a reference phase in each of a plurality of signal areas. The phase error between the received phase of the modulated signal mapped on the complex plane and a reference phase in each of the plurality of signal areas, is calculated as a distance between the mapped position of the modulated signal and a reference straight line, from at least one of the inphase signal and the quadrature signal, so as to obtain a plurality of phase errors.

Abstract: A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.

Abstract: An adaptive region-based, multi-scale, motion compensated video compression algorithm design for transmission over hostile communication channels. The algorithm is embodied in a video encoder that extracts spatial information from video frames to create video regions that are then decomposed into sub-bands of different perceptual importance before being compressed and transmitted independently. The system further uses unequal error protection, prioritized transmission and reconstruction to guarantee a minimum spatial and temporal resolution at the receiver. In particular, the region segmented frames bound both spatial and temporal error propagation within frames. A connection-level inter-region statistical multiplexing scheme is also employed to ensure optimal utilization of reserved transmission bandwidth.

Abstract: In a data recording system utilizing multiple channels and data blocks wherein the data blocks are read subsequent to being written so as to check for errors, the data blocks are rewritten according to a method to provide for rewriting only the defective data blocks. The blocks may be rewritten on other than their original channels. Channels for rewriting are determined by selecting a channel with a highest current block number so that data is rewritten in a channel which has been able to write and verify the most of its original blocks. Error checking is continued in a channel even after finding of an error in that channel. Data blocks of the frames may be skewed between the channels at a beginning of the frame. A ring counter output is applied to break a deadlock where a block is continously rewritten on a failing channel.

Abstract: Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched.

Abstract: A coded frame synchronization method for decoding coded information sent every frame includes the steps of: (a) receiving a coded frame having error detection or correction codes, each of which is provided every predetermined number of bits, error detection or correction codes being added to the coded frame in accordance with a predetermined pattern; (b) pulling the coded frame in synchronization by performing an error detection process every predetermined number of bits to be compared with results of the error detection process and thus detecting a phase of the error detection or correction codes; and (c) recognizing a leading end of the coded frame on the basis of the phase of the error detection or correction codes.

Abstract: The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Abstract: In base station side equipment, a control channel for transmitting control information and a communication channel for transmitting information to each mobile station are spread with different synchronizing codes before being superposed by operating a switch to switch the output of an adder over to the output of a synchronizing code generator. Further, a synchronizing code is periodically inserted in a signal by one symbol length and the signal is transmitted over the superposed channel. In a plurality of base station side equipment, moreover, the synchronizing code and its transmission period are equal and the transmission timing is asynchronous and independent.

Abstract: The present invention relates to a circuit of reception of bits transmitted on an asynchronous signal, including a circuit for providing a clock reconstructed from the asynchronous signal, this clock being used to sample the asynchronous signal to form a synchronous output signal, and a reception error detection circuit. The reception error detection circuit includes an edge detector providing a detection pulse for each edge of predetermined direction of the asynchronous signal; and an alarm circuit activating an alarm signal when an edge of predetermined direction of the synchronous signal occurs outside a detection pulse.

Abstract: A process and apparatus for synchronizing the block counter of an RDS radio data receiver is described. According to the process, the bits stored in a 26-bit shift register, are cycled at least n times in said register, n being the number of allowable offset words, and the shift register content is X-OR gated with another offset word in a given sequence for each cycle. The gating result is received by a syndrome detection circuit, which triggers a sync pulse when the zero syndrome is detected, and the sync pulse resets the bit counter to zero and sets the block counter to the address counter status assigned to the offset word in the offset word generator.

Abstract: A method for repeating data transmitted incorrectly (ARQ) between subscribers having in each case at least one transmit section, and at least one receive section. A data stream at the transmitting subscriber's end is subdivided into data words having a predetermined length. The data stream is combined to form data words where the individual data words are temporarily stored in a transmit buffer. The individual data words are transmitted, if necessary via a transmit unit, and are received by the receiving subscriber, if necessary in a receive unit. After temporary storage in a receive buffer the received data word is output.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. The bridge also includes a memory subsystem and a bridge control mechanism. The bridge control mechanism is operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to be responsive to detection of a lockstep error to cause the bridge to be operable in an error mode in which write accesses initiated by the processor sets are buffered in a bridge buffer pending resolution of the error mode. A respective buffer region is provided for each processing set. In an initial error mode, any complete device write accesses initiated by the processing sets are stored in a posted write buffer. Where data is in transit through the bridge on entry to the error mode, the data is diverted to one or more disconnect registers.

Abstract: An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated. A data valid signal is transmitted synchronous to the data signal and the clock signal.

Abstract: A de-framer (72) in a communications gateway (22) translates videoconferencing information from a circuit-switched format to a packet-switched format. A demultiplexor (78) extracts a bitstream containing video information that includes error-correction-code fields disposed at predetermined locations with respect to synchronization bits spaced by a synchronization interval and forming a predetermined synchronization sequence. A frame checker (88) for checking the error-correction code finds codeword boundaries by comparing the predetermined synchronization sequence with sequences of synchronization-interval-spaced video-bitstream bits until it finds a match. To do so, the frame checker (88) takes a group of video-bitstream words offset from each other by the synchronization interval. It compares each word in the group with a respective synchronization word consisting of a word-width replication of a respective synchronization bit.

Abstract: In order to find the position of the boundary between transmitted codewords, in a receiver a reliability measure for two possible positions are compared. If a relative difference measure of these reliability measure exceeds a predetermined threshold value, the reliability measure indicating the largest reliability corresponds to the correct position of the boundary between the codewords.

Abstract: A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal.

Abstract: A digital signal transmission apparatus, wherein at the time of normal data transmission, an output circuit of a transmitter unit selects transmission data SDAT and converts it to a differential signal for output to the transmission line, while a clock recovery circuit of the receiver unit generates a clock signal LCK matching the frequency of the transmission clock signal TCK and receives the signal based on the same. When the clock signal LCK and the received signal deviate in frequency, the clock reproduction circuit outputs a common mode reference clock request signal to the transmission line. In accordance with this, the transmitter unit selects the reference clock signal RCK for output to the transmission line. The clock recovery circuit of the receiver unit uses this to make the frequency of the clock signal LCK match the transmission clock signal.

Abstract: A multiplexing system which detects multiplexing errors, includes PES packetizing modules that packetize elementary streams (ES) to produce packetized elementary streams (PES), and a TS/PS packetizing module that multiplexes packetized elementary streams (PES) to produce transport streams (TS) or program streams (PS). Comparators are provided each to compare a non-packetized elementary stream (ES) or a packetized elementary stream (PES) stored in a FIFO memory with the packetized elementary stream (ES) or packetized elementary stream (PES) from the packetizing modules. Based on the comparison result, a control module detects errors in the packetizing modules.

Abstract: The partial decoding algorithm for decoding the partially damaged differential satellite positioning system (SATPS) messages is disclosed. The algorithm is based on the modified parity test. The information included in the decoded messages can be used for the high level differential SATPS testing.

Abstract: A disk sequencer, which is loaded with control words from a format table and a frame number associated with the first control word loaded, automatically cycles through loaded control words and finds a control word that corresponds to the current position of a data sector. The disk sequencer includes a first counter that is initialized according to a frame number read from a servo sector or according to an index mark and incremented for each end-of-servo pulse so that the first counter accurately indicates the current position of a data head to a data frame granularity. A second counter is loaded with a data frame number associated with the control words, and the second counter is incremented each time the last control word for a data frame is discarded. For automatic alignment, the disk sequencer cycles through and discards control words until comparison of the counts in the two counters indicates the control words are properly aligned.

Abstract: A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a "check stop" signal. Once frozen, the shift register can be scanned for fault isolation analysis.

Abstract: A data transfer system providing parity uses a method and apparatus for transmitting a data clocking signal in a parity bit location along a data bus to latch an accompanying data byte at a receiving device. A transmitting device, coupled to the receiving device through the data bus, generates a data clock signal and latches the clock signal into the parity bit location of the data bus. The clock signal and data byte are then transmitted along the data bus to the receiving device. The receiving device uses the clock signal to latch the data byte from the data bus. Thus, the data transfer system uses the data clock signal transmitted in the parity bit location of the data bus to validate and synchronize the accompanying data byte at the receiving device.