Abstract: A data recovery circuit for use in a data receiving system to recover an m-bit data stream from an n-bit data stream. The data recovery circuit comprises an n-bit data reconstruction circuit for selecting a data boundary in response to a boundary selection signal and producing a reconstructed n-bit data stream based on the boundary data, a FIFO buffer circuit for temporarily storing the reconstructed n-bit data stream and reading out the m-bit data stream, and a detection circuit for detecting whether the m-bit data stream from the FIFO buffer circuit conforms to a predetermined format and thereby producing a boundary selection signal for controlling the data boundary selection of the n-bit data reconstruction circuit.

Abstract: Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur when transmissions occur. After determining the high and low operable limits of the deskew values, an optimum deskew setting may be determined and set for the system. The present invention may be used as a design verification technique, for optimizing a system after integration, or for further optimization of the deskew value after performing a training pattern for optimizing transmission performance.

Abstract: An IC including duplicated primary components which can be operated microsynchronously has at least one synchronization device for synchronizing asynchronous signals to the primary clock. An asynchronous signal intended for the primary components is routed via the synchronization device, synchronized and supplied to the inputs of the primary components. With duplicated asynchronous components, an output signal from just one asynchronous component is synchronized and is supplied to the primary components.

Abstract: A method for receiving data by an integrated circuitry chip includes receiving data signals and a first clock signal sent by a sending chip. The data signals are received by data receivers and the clock signal is received by at least one clock receiver of the receiving chip. A reference voltage is derived by reference voltage circuitry for the receiving chip responsive to the first clock signal. Logical states of the received data signals are detected. The detecting includes the data receivers comparing voltage levels of the received data signals to the derived reference voltage.

Abstract: The invention is related to methods and apparatus that recover usable video data from partially corrupted data. Embodiments inspect corrupted data packets and identify the location or locations of an error, whether the corrupted data packet contains data expected to be error-free, and whether the error-free data should be used. Decoding of a packet in both the forward direction and the backward direction can be used to locate a position of an error. Intra-coded macroblocks can also be recovered. A decoder can elect to use or to drop an intra-coded macroblock recovered from a corrupted data packet according to further criteria that is applied to the recovered intra-coded macroblock. One embodiment inspects video bitstream data that has been encoded with an optional data partitioning feature enabled, and retrieves specified data in areas of a corrupted packet that are expected to be free from error.

Abstract: The frame synchronizing circuit establishes frame synchronization by detecting a sync pattern laid in an incoming frame. The frame synchronization circuit comprises a first frame synchronizing unit and a second frame synchronizing unit. The first and second synchronizing units synchronize with a first pattern, a second pattern at a first position and a second position, respectively. Thereafter, when the first position used for the synchronization by the first frame synchronizing unit is found to be in error, the first frame synchronizing unit synchronizes with the second pattern at the second position used by the second frame synchronization unit.

Abstract: Encoded data using reversible variable length code words is input to a forward decoder (123) to be decoded in the forward direction. When an error is detected in the encoded data in the forward decode processing, backward decode processing is started by a backward decoder (126). A decode value determination unit (125) determines a decode value by using the forward and backward decode results and the error detection positions in the encoded data in units of bits and syntax which are respectively detected in the forward decoding and the backward decoding.

Abstract: A telecommunications system and method which includes a transmitter, a first code generator for generating a noise code and a second code generator for generating a string-based code, wherein data which is transmitted by the transmitter is coded by the first and second code generators before transmission. One of the code generators preferably comprises a pseudorandom noise generator, and the other code generator preferably comprises a cyclic redundancy checking coder for assisting in deskewing of data. The telecommunications system allows the transmitter to dynamically request additional bandwidth from the telecommunications provider in order to efficiently transmit data. The present telecommunications system also substantially reduces skew experienced between the transmitter and the receiver.

Abstract: A method and system for packaging frames or packets encoded in a variety of formats, for example, Frame Relay, Ethernet, ATM, or TCP/IP. The method includes: accumulating first and second packets; determining the length of each packet; and storing the lengths into a header associated with the first packet. By using the length field, frame synchronization can be efficiently achieved and maintained for the packets encoded using the method.

Abstract: A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Abstract: A circuit which recovers a synchronization code, and a method thereof. Where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery candidate patterns are compared with an original synchronization pattern, and location data to produce an optimal synchronization pattern is determined and generated on the basis of a result of the comparison. The synchronization code is recovered to a location corresponding to the location data. Alternatively, where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery candidate patterns are error-corrected, and location data to produce an optimal synchronization pattern is determined and generated on the basis of a result of the error correction. The synchronization code is recovered to a location corresponding to the location data.

Abstract: This specification provides a burst synchronization and error detection device, which can generate in the synchronization module of the burst synchronization and error detection device a syndrome shared with the error detection module so as to decrease the computation time of the syndrome, shortening the processing time of error detection. The present invention also provides a burst synchronization and error detection method.

Abstract: A glitch detection circuit is described for detecting a glitch on a strobe signal transmitted over a single strobe interface. The glitch detection circuit includes a first input terminal to receive a single strobe signal and a second input terminal to receive a protocol control signal. The glitch detection circuit uses a double edge detection circuit to detect two consecutive rising or falling edges on the strobe signal. The double edge detection circuit becomes initialized by an initializing circuit each time the logical state of the control signal changes from a first state to a second state. The glitch detection circuit is configured to output a glitch detection signal when two consecutive rising or falling edges are detected by the double edge detection circuit before being initialized by the initializing circuit.

Abstract: A method for error detection and error correction in the monitoring of measurement values is disclosed, in which the value to be tested is checked for plausibility in an evaluation device, for example a computer, and in the event that an implausibility is identified, the existence of an error is determined. If a further check finds that the error no longer exists, then an error correction takes place. A prerequisite for the error correction, however, is that the range of the value to be monitored in which the error has occurred is also the range in which a current error is no longer occurring. In an expanded method, a differentiation is also made between different errors and an error correction is only possible if it involves the same type of error.

Abstract: An apparatus and method for error correction encoding a datastream of information into blocks of error correction encoded information. An input terminal receives the datastream. An error correction encoding unit performs an error correction encoding on portions of the datastream. A block of error correction encoded information includes n sync blocks, each sync block including a sync word and a portion of the error correction encoded information, where n exceeds 3. An output terminal supplies the blocks of error correction encoded information. The error correction encoding unit supplies one of m mutually different sync words to each n sync block, such that the sequence of two sync words of corresponding two sync blocks of the n sync blocks is unique with respect to the bit patterns within the two sync words, m satisfying 2<m<n.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A system and method for enabling an optical network unit (ONU) in a passive optical network to scramble data and send the scrambled data upstream to an optical line termination unit (OLT). In passive optical networks the clocks in the OLT and ONU are synchronized by recovering the clock from the data signal. However, the clocks may drift when no data transitions occur on a long string of data. In addition, the OLT may require data transitions to ensure proper adjusting of its receive threshold. In either circumstance, collectively called Loss of Synchronization, the data may not be received correctly by the receiver and the transmitter will need to resend the data. In the present invention, the transmitter will vary the seed used in the scrambling operation. The use of a different seed per each transmission significantly reduces the chances that a loss of synchronization will occur.

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A telecommunications system and method which includes a transmitter, a first code generator for generating a noise code and a second code generator for generating a string-based code, wherein data which is transmitted by the transmitter is coded by the first and second code generators before transmission. One of the code generators preferably comprises a pseudorandom noise generator, and the other code generator preferably comprises a cyclic redundancy checking coder for assisting in deskewing of data. The telecommunications system allows the transmitter to dynamically request additional bandwidth from the telecommunications provider in order to efficiently transmit data. The present telecommunications system also substantially reduces skew experienced between the transmitter and the receiver.

Abstract: A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded the on the receive side with at least two different generating polynomials. Based on the results of the twin decoding, the present method can determine which of the generating polynomials was used to encode the message and respond accordingly. For instance, if the a particular generating polynomial was used, then this may be use to indicate that a second channel has been superimposed onto the primary channel and that second channel may be extracted. On the other hand, if another generating polynomial, such as the default generating polynomial, was used, this may be used to indicate that no second channel has been superimposed.

Abstract: The present invention provides methods for analyzing measurement errors in measured signals obtained in an experiment, e.g., measured intensity signals obtained in a microarray gene expression experiment. In particular, the invention provides a method for transforming measured signals into a domain in which the measurement errors in the transformed signals are normalized by errors as determined from an error model. The methods of the invention are particularly useful for analyzing measurement errors in signals in which at least portion of the error is dependent on the magnitudes of the signals. Such transformed signals permit analysis of data using traditional statistical methods, e.g., ANOVA and regression analysis. Magnitude-independent errors can also be used for comparing level of measurement errors in signals of different magnitudes.

Abstract: The present invention aims to reduce the operating costs for obtaining the lock data required for an exception handling, and to reduce the affect of the exception handling on the operating costs. When an execution program is to be compiled, based on information for the inlining of a function in this program, data concerning is generated for a lock for a resource due to the inlined function. Further, based on the lock data, the data concerning a lock count set upon the execution of code for the target program is added to this program. Then, when an exception has occurred during the execution of the program, the data concerning the lock count is employed to obtain the lock count at the time of execution of the code whereat the exception occurred, and the lock count set at the time of execution of an exception handler for this exception. After the locks for the resource have been released in a number equivalent to a difference between the two lock counts, the process for this exception is initiated.

Abstract: A system that includes one or more priority failure detectors may be included that detect node or process failures in the distributed computer network. The system has a fault-tolerant, client-server architecture where a client process presents a particular consensus problem to one or more server processes to solve such a consensus based problem. The system assigns priority levels to processes involved in a consensus session and controls the frequencies of their heartbeat status messages based on their respective priority levels. By controlling the frequencies, the reliability of the network is enhanced and the overall message load on the even bus is reduced to a minimum number. The system also discloses a name service that assigns unique logical identities to all processes in a consensus session. Further, by tagging all involved processes appropriately, multiple consensus based problems can be dealt with on a set of consensus server processes simultaneously.

Abstract: Re-synchronization of sets of transmit and receive state variables in a communication system is achieved when an error is detected, without disrupting the connection. Each of first and second transceivers, connected by a communications channel, have a common set of transmit and receive state variables supporting a data encoding algorithm function. The transmitter of one of the first and second transceivers fist encodes data to be transmitted and updates the transmit state variables according to the data encoding algorithm and the receiver of the receiving transceiver validates whether or not each data block has been received correctly. During the process of decoding the data, the receive state variables are updated according to the same algorithm used to update the transmit state variables, thereby keeping the two sets of state variables in synchronism with each other.

Abstract: A signal processing circuit for processing a read signal corresponding to data read from a recording medium, such as a magnetic disc. The signal processing circuit detects a preamble data signal of the read signal. A decision feedback equalizer (DFE) generates a computation read signal by performing a predetermined computation on the read signal in accordance with a clock signal. The DFE generates first code data using the computation read signal. A code data generating circuit connected to the DFE compares the computation read signal with a first reference signal and generates second code data, which corresponds to the preamble data signal. A phase error detection circuit detects a phase error between the clock signal and the read signal using one of the first and second code data. A timing recovery PLL is connected to the phase error detection circuit and uses the detected phase error to generate the clock signal such that the phase of the clock signal matches the phase of the preamble data signal.

Abstract: A received frame is provided to a first decoder and a first time reverse unit. The first decoder decodes the provided frame and outputs the decoded frame. The first time reverse unit reverses bits of the provided frame in time direction and outputs the time reversed frame. The time reversed frame is provided to a second decoder. The second decoder decodes the time reversed frame. This decoded frame is then provided to a second time reverse unit. The second time reverse unit reverses bits of the decoded frame in time direction and outputs the frame. The frame is outputted from the first decoder is compared with the frame is outputted from the second time reverse unit by comparator. If any difference exist between the two frames then the received frame is judged as unreliable.

Abstract: A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.

Abstract: A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal.

Abstract: Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an interpolation coefficient, and a feed-forward equalizer having at least three taps. Each tap consists of a multiplier which is coupled to multiply a respective input sample by a respective adaptive equalization coefficient. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer receives and equalizes the interpolated-data so as to generate equalized-data from the interpolated-data. The apparatus also includes a timing sensor which adjusts the interpolation coefficient responsive a third adaptive equalization coefficient comprised in the equalization coefficients.

Abstract: The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Abstract: An adaptive forward error correction technique based on noise bursts and the rate at which they occur is disclosed. The forward error correction parameters are determined using statistics describing the noise burst duration and period. The occurrence, duration and period of the noise burst are determined by the error vector magnitude calculated during the decoding process.

Abstract: A semiconductor integrated circuit having a latch including a data input terminal and a timing input terminal, has a first input terminal connected to the latch data input terminal and a second input terminal connected to the latch timing input terminal. A delay circuit, connected between the first and second input terminals, receives a test signal being supplied to a selected one of the first and second input terminals and supplies a delayed test signal to the nonselected one of the first and second input terminals.

Abstract: A transmitter 12 and a receiver 35 are connected to a network 20 for transferring data of moving image code as a packet between the transmitter 12 and the receiver 35. The transmitter 12 prepares a packet of moving image code from moving image data and outputs the packet to the network 20. In the receiver 35, a moving image reception section 31 receives a packet 61 input via the network 20, extracts the data bits of the moving image code sandwiched between synchronous codes from the received packet 61, and outputs the extracted bits of the moving image code to a moving image decoder 30. The moving image decoder 30 decodes the input moving image code into a digital moving image and outputs the provided digital moving image to a display 33, which then displays the input digital moving image on a display screen.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A signal estimator is provided that can track a large frequency offset. A received signal distorted in a transmission path is phase-rotated by the phase rotator (102) and is then estimated by the maximum likelihood sequence estimator (MLSE) (103). The phase detector (105) detects a phase difference between a signal obtained by delaying the phase-rotated signal and information about a minimum path metric in the Viterbi algorithm operation by the MLSE. After the phase difference signal is filtered, the voltage-controlled oscillator (VCO) receives the filtered signal. Then, the phase rotation is controlled with the output of the VCO.

Abstract: A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output buts corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bits stream jitter and intersymbol interference.

Abstract: Broadband modems using data compression insure the physical connection between modems is solid prior to initiating error recovery procedures since its error detection runs on the compressed data. Escape sequences applicable to Transparent Mode of the Compression function enable both duplex and simplex compression functions and provide a more reliable mechanism for completion of error recovery procedures in the presence of subsequent line disturbances. Transparent Mode is used during the re-synchronization procedure. No special compression code words are required to accomplish the procedure, and there is no reduction in the number of code words available for actual compression encoding. The procedure works regardless of whether compression is being used in both directions, only one direction, or neither direction. A new Transparent Mode Command to request that the remote modem send a RESET Command is defined. The new command is termed RRESET.

Abstract: A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least one recording surface, a decoder circuit which receives coded data from the at least one head, decodes the coded data to parallel data, and outputs the parallel data, and a disc control unit which receives the parallel data from the decoder circuit and outputs the parallel data outside the disc storage apparatus. The apparatus may further include a host interface control unit coupled to a host computer and the disc control unit, wherein the disc control unit outputs the parallel data to the host computer via the host interface control unit, and a buffer memory which stores the parallel data to be outputted to the host computer.

Abstract: The present invention is a method of determining codeword boundary without marker bits by receiving transmission bits; determining a dual code of a code used to generate the transmission bits; selecting a vector from the dual code; initializing n scoring variables; initializing i=1; initializing z=1; selecting n bits from the transmission bits starting at bit position i; performing a bit-wise AND operation on the vector and the n selected bits; if the result of the bit-wise AND operation contains an even number of ones then assigning a value of zero to the result, otherwise assigning a value of one to the result; setting Sz equal to Sz plus the result of the last step; if z is less than n, incrementing z and i each by 1 and returning to the seventh step, otherwise proceeding to the next step; if z=n, i<L, and it is desired to process additional transmission bits then incrementing i by 1, and returning to the sixth step, otherwise proceeding to the next step; identifying the scoring var

Abstract: An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.

Abstract: One aspect of the invention provides a novel scheme to improve channel jitter tolerance and perform data recovery across a serial data channel. In one implementation, the invention samples each data unit in the data channel multiple times and, using two data cycles, selects one of the samples as representative of the data unit. According to one aspect, the invention performs edge detection between adjacent data samples to determine the location of transitions between data units (bits). A representative data sample is chosen which is as far away as possible from the detected edge and the next expected edge and yet adjacent to, or equal to, the ideal current sample point. According to another aspect of the invention, as between two equally possible samples, the algorithm selects the sample which is furthest from the distribution of prior cycle edges.

Abstract: A method and apparatus for Viterbi detection to detect a code sequence containing a sync word, from an output sequence on a transmission path, by using a trellis detection that has a time-variant structure. The apparatus comprising a base counter for measuring time during the trellis detection, a comparator for comparing the time when the sync word is detected and outputting a coincidence/non-coincidence signal, and a selector for selecting either an output of an ACS (Add Compare Select) circuit or a predetermined initial metric value. The likelihood of a state in which the sync word starts or ends in the trellis detection is initialized only if the time the sync word is detected does not coincide with a time extrapolated before the sync word is detected.

Abstract: The probability of frame destruction is lowered while suppressing the redundancy of the transmission data. On the transmitting side, a predetermined unique word is contained in a frame n for storing the n-th data, and header information n, frame length information and header information n−1 of the frame n−1 one frame before the frame n are subjected to error-correcting coding, contained in the frame n, and transmitted. On the receiving side, the header of the frame n is received. When the frame length information is transmitted with error, the timing is specified by detecting the unique word and header information in the next frame n+1. When the header of the frame n is not successfully decoded, the information data of the frame n is decoded by using the header information n inserted into a predetermined position of the frame n+1.

Abstract: A method for controlling the saving of information regarding printer operating conditions to its nonvolatile memory is provided. The method decreases the data save time to the printer's nonvolatile memory, and minimizes the effect that saving to the nonvolatile memory has on printer operation. The method groups printer status data relating to the printer's operating conditions into different groups or blocks of data and allocates each block to a different storage area in the printer's volatile memory and its nonvolatile memory. A particular data group stored in its assigned storage area in the volatile memory is saved to the corresponding storage area in the nonvolatile memory when one or more trigger events related to printer control to which that particular data group is responsive occur.

Abstract: Test circuit for testing a synchronous circuit (3) which is clocked with an operating clock signal with a high operating clock frequency, having:

Abstract: A method and system for automatic negotiation of maximal shared data transmission and reception rates by fibre channel nodes in a fibre channel arbitrated loop. An auto-speed-negotiation function is included in the fibre channel arbitrated loop initialization procedure. A fibre channel node undergoing initialization turns off its transmitter in order to elicit a loss of synchronization condition in the next fibre channel node of the arbitrated loop. Upon detection of loss of synchronization, each subsequent fibre channel arbitrated loop node invokes the auto-speed-negotiation function. The fibre channel node then turns its transmitter back on at the highest possible data transmission rate, sets the data reception rate of the fibre channel node's receiver to the lowest possible data reception rate, and then waits to detect word synchronization by the receiver.

Abstract: The present invention aims to reduce degradation in image quality due to residual magnetization. In a pulse sequence of a high-speed spin echo process, a pre-pulse is applied before an excitation pulse, and a correction pulse for correcting a phase error caused by the pre-pulse is applied before an initial inversion pulse.

Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.