Abstract: System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed at either end of a communication channel (e.g., at a transmitter end when performing encoding and/or at a receiver end when performing decoding). By combining different coding types within a communication system, the error correcting capabilities of the overall system is significantly improved. The appropriate combination of turbo code and/or LDPC code along with RS code allows for error correction or various error types including random error and burst error (or impulse noise).

Abstract: System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed at either end of a communication channel (e.g., at a transmitter end when performing encoding and/or at a receiver end when performing decoding). By combining different coding types within a communication system, the error correcting capabilities of the overall system is significantly improved. The appropriate combination of turbo code and/or LDPC code along with RS code allows for error correction or various error types including random error and burst error (or impulse noise).

Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Abstract: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess (e.g., weak, medium or strong). The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.

Abstract: An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store object or file data in a set of autonomous storage devices forming a RAID group. The storage devices independently receive storage requests from a client over a network, and one or more of the storage devices are designated as parity-mirror storage devices for a stripe. The striping association module calculates a stripe pattern for the data. Each stripe includes N data segments, each associated with N storage devices. The parity-mirror association module associates a set of the N data segments with one or more parity-mirror storage devices. The storage request transmitter module transmits storage requests to each storage device. Each storage request is sufficient to store onto the storage device the associated data segments. The storage requests are substantially free of data.

Abstract: An apparatus for operating on a received signal that includes a noise-free signal that has been corrupted by a channel is disclosed. A memory stores a channel corruption function specifying the probability that a symbol having a value I was converted to a symbol having a value J by the channel, and a degradation function measuring the signal degradation that occurs if a symbol having the value I is replaced by symbol having a value J. The controller parses one of the received signal or the processed signal into phrases, and replaces one of the symbol having a value I in a context of that symbol in the received signal with a symbol having a value J if the replacement would reduce the estimated overall signal degradation in the processed signal. The context of a symbol depends on the phrase associated with the symbol.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness.

Abstract: Integrated circuits have expanded a set of custom registers and a read mechanism for control registers. One embodiment includes a circuit having a first set of registers; a second set of registers to be written via one or more write operations addressed to one or more registers of the first set; and a read controller coupled with the first and second sets of registers, the read controller to selectively output a portion of data stored in the first and second sets of registers based on data stored in one or more registers of the second set. In one embodiment, the circuit further includes a logic block; and a multiplexer to select from an output of the logic block and an output of the read controller as an output of the circuit based on the data stored in the one or more registers of the second set.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness.

Abstract: A system and method detects an uplink error during the transmission of visual data in a mobile communication system. When such an error is detected in data which has passed an uplink radio section, a specific CRC code causing a ‘CRC fail’ is inserted into a corresponding data block. Accordingly, an error detection available region can be extended and a picture quality of a mobile image of a mobile communication terminal can be substantially improved.

Abstract: A method includes separating resource elements from multiple code blocks into different groups, and decoding the code bits of the resource elements within each group without waiting for a completed reception of a transport block to start decoding. A method includes separating coded bits from multiple code blocks into different groups, and decoding the code blocks containing coded bits within each group. A first CRC is attached to the transport block and a second CRC is attached to at least one code block from the transport block. An improved channel interleaver design method including mapping from coded bits of different code blocks to modulation symbols, and mapping from modulation symbols to time, frequency, and spatial resources, to make sure each code block to get roughly the same level of protection.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one Values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: A system of applying a parity bit to protect transmitting and receiving data includes a transmitting-end device and a receiving-end device. The transmitting-end device includes a parity generator, a first parity location generator and a parity inserting unit which, when transmitting data, inserts a parity bit in the data to thus generate an encrypted data. The receiving-end device includes a second parity location generator and a parity removal unit that receives the encrypted data and removes Nth bit of the encrypted data in accordance with an inserting position N generated by the second parity location generator.

Abstract: A data communication method for puncturing of parity bits defining all parity data for a minimum code rate generated by an encoder is disclosed. The method initializes an accumulator associated with the parity bits to an initial value, and for each parity bit increments the accumulator by a increment value and determines if the accumulator has overflowed. If the accumulator overflows, at least one of the parity bits is selected for transmission.

Abstract: A method of encoding data for transmission from a source to a destination over a communications channel is provided. The method operates on an ordered set of input symbols and includes generating a plurality of redundant symbols from the input symbols. The method also includes generating a plurality of output symbols from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number of the output symbols.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.

Abstract: A forward error correction encoder encodes input data words into code words that comprise a parity matrix. In one aspect, the encoder is optimized based on the properties of the parity matrix in order to reduce routing overhead size.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base parity check matrices of different dimensions and a set of lifting values of different powers of two. A base parity check matrix G of dimension mB×nB may be used to encode a packet of kB=nB?mB information bits to obtain a codeword of nB code bits. This base parity check matrix may be “lifted” by a lifting value of L to obtain a lifted parity check matrix H of dimension L·mB×L·nB. The lifted parity check matrix may be used to encode a packet of up to L·kB information bits to obtain a codeword of L·nB code bits. A wide range of packet sizes may be supported with the set of base parity check matrices and the set of lifting values.

Abstract: An error correction method for optical discs, and more particularly, an error correction method appropriate to high density discs is provided. The error correction method adds inner parity and outer parity to an error correction block of size n byte×m×o. The method comprises the steps of obtaining a plurality of inner parity blocks (PI blocks) by segmenting the error correction block in the inner parity (PI) direction into x segments; generating e-byte PI for each of the plurality of PI blocks generated by segmenting, and adding the e-bytes to the PI blocks PIs to the PI direction; and generating f-byte outer parity (PO) in the PO direction of the error correction block, and adding the POs to the PO direction. The error correction method enhances error correction capability while maintaining a redundancy of parity signal on a level similar to conventional DVDs.

Abstract: A method for identifying anomalies in time series data, the method comprising the steps of computing parity vectors for one or more data points in a predetermined sample of data points in the time series, the parity vector representing redundancy between an estimated true value and an error term for each of the said one or more data points, evaluating the parity vectors to determine a set of the parity vectors in a selected direction; and evaluating a statistical distribution of the set according to a predetermined criterion to determine a data point to be corrected whose parity vectors satisfy the criterion in the distribution.

Abstract: A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

Abstract: Storing parity information in an external storage with multiple disk drives by determining the number of the storage blocks used as data blocks and the number of the storage blocks used as parity blocks; forming a three-dimensional block matrix of virtual data blocks corresponding to the determined number of the storage blocks; allocating virtual parity blocks to the virtual data block planes; allocating the virtual data blocks and the virtual parity blocks to the storage blocks; calculating parity information based upon data bits respectively stored in the storage blocks corresponding to the virtual data blocks of every virtual data block plane; and storing the calculated parity information in the storage blocks corresponding to the virtual parity blocks. The stored parity information allows any number of error blocks to be recovered, and more particularly allow three or more error blocks per one parity group to be recovered.

Abstract: A method for organizing and distributing parity blocks among storage devices of an array coupled to a storage system is disclosed. First the array is configured with a predetermined number of devices. Each device is divided into blocks. The blocks are organized into stripes, wherein each stripe contains at least one first device that holds at least one row parity block, at least one second device that holds at least one diagonal parity block, and a plurality of devices that hold data blocks. An extra parity block is appended within each stripe. Each data block is assigned to one row parity set and one diagonal parity set, such that any one or any combination of two devices can fail concurrently and data on the failed devices can be reconstructed.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.

Abstract: An error correction method for optical discs, and more particularly, an error correction method appropriate to high density discs is provided. The error correction method adds inner parity and outer parity to an error correction block of size n byte x m x o. The method comprises the steps of obtaining a plurality of inner parity blocks (PI blocks) by segmenting the error correction block in the inner parity (PI) direction into x segments; generating e-byte PI for each of the plurality of PI blocks generated by segmenting, and adding the e-bytes to the PI blocks PIs to the PI direction; and generating f-byte outer parity (PO) in the PO direction of the error correction block, and adding the POs to the PO direction. The error correction method enhances error correction capability while maintaining a redundancy of parity signal on a level similar to conventional DVDs.

Abstract: Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.

Abstract: A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

Abstract: Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords (e.g., an MLC block) are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks that corporately form an MLC block. Encoded bits from levels of the MLC block are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

Abstract: An error correction method for optical discs, and more particularly, an error correction method appropriate to high density discs is provided. The error correction method adds inner parity and outer parity to an error correction block of size n byte x m x o. The method comprises the steps of obtaining a plurality of inner parity blocks (PI blocks) by segmenting the error correction block in the inner parity (PI) direction into x segments; generating e-byte PI for each of the plurality of PI blocks generated by segmenting, and adding e-bytes PIs to the PI blocks in the PI direction; and generating f-byte outer parity (PO) in the PO direction of the error correction block, and adding the POs to the PO direction. The error correction method enhances error correction capability while maintaining a redundancy of parity signal on a level similar to conventional DVDs.

Abstract: An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag parity value in a RAM portion of a TLB, using the CAM key input to generate a tag parity check value for a matched entry, and comparing the generated tag parity check value to the stored tag parity value to determine if there is a parity match or error.

Abstract: A method of converting a parity check matrix for low density parity check coding comprising moving rows and columns of the parity check matrix such that the parity check matrix includes a lower triangular submatrix. A calculation load for creating parity information can be reduced by using the converted parity check matrix including the lower triangular submatrix.

Abstract: A fault tolerance system for one or two failed disks in a disk array includes a CPU, a disk array, and a bus. The disk array includes disks, each of which is logically divided into multiple blocks, wherein the blocks include data blocks, P parity blocks and Q parity blocks. The CPU, which is connected to the disk array through the bus, includes: an exclusive-or (XOR) unit for performing XOR operations on blocks of the disk array when generating P/Q parities or reconstructing failed data; a modulus operation unit for performing modulus operations; a shift operation unit for performing shift operations on the blocks of the disk array; and an address conversion unit for converting a logic address into a physical address. Related methods are also provided.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: Various systems and methods for code dependency reduction are disclosed herein. For example, one method includes receiving an un-encoded data set that is represented as an array of columns and rows. In addition, two groups of data bits traversing the un-encoded data set at respective angles are formed. Based at least in part on the aforementioned groups of data sets, an angle at which a third group of data bits will traverse the un-encoded data set is identified, and a third group of data bits traversing the un-encoded data set at the third angle is formed.

Abstract: A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, and a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product.

Abstract: A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb. Base matrix Hb comprises a section Hb1 and a section Hb2. Section Hb2 comprises column hb having weight wh>=3 and H?b2 having a dual-diagonal structure with matrix elements at row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The 1's of hb and Hb1 are arranged such that one or more groups of the rows of Hb can be formed so that the rows of Hb within each group do not intersect. Further more, the rows of base matrix Hb can be permuted such that every two consecutive rows do not intersect.

Abstract: The present invention includes a technique for updating messages that originate at the constraint nodes of bi-partite graphs in Low Density Parity Check codes. The technique computes only two outgoing magnitudes at each constraint node and exhibits no measurable performance loss as compared to exact belief propagation which computes a unique magnitude for each departing edge from a given constraint node. The technique eliminates the need for memory based table look-up in the constraint node processing and has been implemented, in one embodiment, using only shift, add, and comparison operations.

Abstract: A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circuit. In succeeding iterations, the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block decoder from an immediately preceding iteration. The storage system includes a threshold check circuit to select (i) an output of the soft linear block code decoder if the number of parity-check violations has a first relationship with respect to a threshold, or (ii) an output of the channel decoder if the number of violations has a second relationship with respect to the threshold. The storage system includes a decoder to decode an output of the threshold check circuit.

Abstract: Provided are a method, system, and article of manufacture for providing data integrity for data streams. Input data streams are received. A parity data stream is generated by computing parity data from the input data streams, wherein the parity data stream comprises data blocks. Data integrity fields are computed for the data blocks, wherein a data integrity field is used to ensure the integrity of a data block for which the data integrity field is computed. The computed data integrity fields are added to the data blocks to generate an output stream.

Abstract: A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data from among the data stored based on a predetermined priority, extract the desired data from a corresponding register, and outputs the desired data to the output unit; a detecting unit that detects an error in the desired data; a diagnostic-data writing unit that writes diagnostic data for diagnosing failure of the register in the register from which the desired data is extracted; and a diagnostic-data error detecting unit that detects an error in the diagnostic data.

Abstract: A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) data on the array, the file system determines which disks contain free blocks in a next allocated stripe of the array. There may be multiple blocks within the stripe that do not contain file system data (i.e., unallocated data blocks) and that could potentially store parity. One or more of those unallocated data blocks can be assigned to store parity, arbitrarily. According to the dynamic parity distribution technique, the file system determines which blocks hold parity each time there is a write request to the stripe. The technique alternately allows the RAID system to assign a block to contain parity when each stripe is written.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A recovery enabling system for storage arrays is a high distance generalization of RAID-5 with optimal update complexity and near optimal storage efficiency. The recovery enabling system utilizes presets, data cells with known values that initialize the reconstruction process. The presets allow resolution of parity equations to reconstruct data when failures occur. In one embodiment, additional copies of the layout of the recovery enabling system are packed onto the same disks to minimize the effect of presets on storage efficiency without destroying the clean geometric construction of the recovery enabling system. The recovery enabling system has efficient XOR-based encoding, recovery, and updating algorithms for arbitrarily large distances, making the recovery enabling system an ideal candidate when storage-efficient reliable codes are required.

Abstract: Provided are a techniques for receiving a modification to at least one data block. Parity blocks that are to be computed for the at least one data block are determined. At least one common term for computations for the determined parity blocks is determined. A first parity block from the determined parity blocks is computed that generates intermediate parity results for the common term. A second parity block from the determined parity blocks is computed using the intermediate parity results.

Abstract: A device and method of applying a parity to encrypt data for protection is disclosed. A parity generator generates a parity bit in accordance with a data to be outputted. A first parity location generator generates an inserting position N for the parity bit in accordance with a predetermined algorithm. A parity-inserting unit inserts the parity bit in a position between (N?1)th- and Nth-bit of the data in accordance with the inserting position N, thereby generating an encrypted data.

Abstract: One embodiment of the disclosures made herein is an apparatus adapted to facilitate error detection for Content Addressable Memory (CAM) modules. The apparatus includes an input error detection module and an output error detection module. The input error detection module includes a parity word generator that generates a key-based parity word after receiving a key. The key-based parity word and the key jointly define a comparand that is provided to the CAM module. The output error detection module includes a protection word generator that generates a key-based protection word after receiving the key and memory. The output error detection module includes a comparator connected to the protection word generator and to the memory. The comparator enables the predetermined protection word to be compared with the key-based protection word for facilitating issuance of an output error indication when the predetermined protection word is different than the key-based protection word.

Abstract: A data modulation method to suppress a DC component using parity information of a synchronization codeword, and an apparatus for executing the method. Input data is multiplexed according to multiplexing information, the synchronization codeword including the multiplexing information for a multiplexed data stream is inserted, modulation is performed and plural modulated data streams are output, and a respective one of the modulated data streams having a DC component, which is smallest is selected from among the modulated streams. The synchronization codeword has a bit to control the parity of the codeword, and the input data is multiplexed according to whether a parity of the synchronization codeword is even or is odd. Thus, the DC component included in the modulated codeword stream may be more effectively suppressed without a decrease in a code rate.

Abstract: (3n+1)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a first memory 102, (3n+2)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a second memory 103, and (3n+3)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a third memory 104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108, a first parity bit queue 109, and a second parity bit queue 110, respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.