Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.

Abstract: The present invention relates to a low density parity check (LDPC) encoding method and an apparatus thereof. In the LDPC encoding method, a matrix multiplication corresponding to ET?1 and T?1 is eliminated according to a structural characteristic in an encoding process. Accordingly, shift weights that are not ?1 among shift weights corresponding to partial blocks A, B, and C of a parity check matrix are used to perform an encoding operation, and a cyclic shift operation of an information unit block is performed in parallel so that a first parity block and a second parity block may be simultaneously generated.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: A DTV transmitter includes a pre-processor pre-processing supplemental data, a multiplexer multiplexing pre-processed data with main data, and a byte-symbol converter converting each data byte of the multiplexed data into a symbol. It further includes a symbol processor processing each supplemental data symbol outputted from the byte-symbol converter. It encodes one of upper and lower bits of each supplemental data symbol into first and second data bits, post-decodes the first data bit, and outputs the post-decoded data bit and the second data bit as a symbol. The DTV transmitter further includes a symbol-byte converter converting each symbol outputted from the symbol processor into a data byte.

Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Abstract: An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling.

Abstract: A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to program a nibble more than once with non-zero data between erase cycles.

Abstract: Embodiments of the present invention provide a method, system, and computer program product for optimizing I/O operations performed by a storage server operating on behalf of multiple clients to access data on a plurality of storage devices (disks). Embodiments of the present invention eliminate the need for selected read operations to write new data to physical data blocks by zeroing the physical data blocks to which new data will be written. Additionally, the need for reading old parity to compute new parity is eliminated. Instead, new parity is computed from the data to be written without the need of old parity or the storage server sends a command to a disk that stores parity. A module implemented at the disk that stores parity executes the command without reading, by the storage server, old parity. Eliminating the need for reading old data and for reading old parity eliminates some rotation latency and improves overall system's performance.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(v)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: A transmission device according to the present invention splits information bits, calculates two parity bit sequences from the split information bits, combines the parity bit sequences with information bits (encoded information bit) such that the calculated two parity bit sequences are not added to the same information bits. Then, the transmission device changes the order of the combined information, distributes each of the reordered information to levels L0 and L1, and performs multi level modulation, thus making the reliability of each bit constant.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

Abstract: A data communication method for puncturing of parity bits defining all parity data for a minimum code rate generated by an encoder is disclosed. The method initializes an accumulator associated with the parity bits to an initial value, and for each parity bit increments the accumulator by a increment value and determines if the accumulator has overflowed. If the accumulator overflows, at least one of the parity bits is selected for transmission.

Abstract: A method for detecting topology changes of a computer network, includes the following steps of acquisition of the raw data from the configuration tables of the network elements during successive primary pollings, the following steps being carried out between two successive primary pollings: calculation and storage of a checksum value for each network element having raw data which are considered to be sensitive, at least one secondary polling, allowing the sensitive data to be retrieved again from each corresponding element, comparison of the previously-stored checksum value, at each secondary polling and for each element termed sensitive, with a new checksum value calculated with the new sensitive data, for each sensitive element, when the two checksum values differ, updating in a topology database only the topology data relative to the corresponding element.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: A transmission system carrying out sending and receiving of OTU frames has a first transmission device carrying out the sending of an OTU frame, and a second transmission device carrying out the receiving of the OTU frame. The first transmission device calculates BIP-8 for an objective calculation range preset in the OTU frame, inserts the calculation result into the OTU frame, and sends the same. The second transmission device calculates BIP-8 from the received OTU frame for the same objective calculation range as the first transmission device, compares the calculation result with the BIP-8 sent from the first transmission device, and detects any presence of transmission error. The calculation range is set in terms of one of an area including OPU only and an area at least including an arbitrary byte of OTU/ODU overhead.

Abstract: A network component comprising a processor configured to implement a method that comprises applying a forward error correction (FEC) algorithm to a plurality of data blocks to generate a plurality of redundancy data, encapsulating an integer number of the data blocks and the redundancy data in an FEC codeword, and transmitting the FEC codeword, wherein the codeword is about evenly aligned with a transmission clock time quanta to have a transmission rate. A method comprising selecting an FEC algorithm that generates a plurality of redundancy data from a plurality of data blocks, selecting an EEC codeword that encapsulates an integer number of the data blocks, and selecting a synchronization pattern to add to the FEC codeword such that an integer number of the FEC codewords are evenly aligned with an integer number of transmission clock time quanta.

Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by incorporating results from a previous decoding iteration. In one embodiment, a final multiplexer selects between the final detector output or a previous detector output based on the absence or presence of defective data. In another embodiment, the branch metrics for the defective data, which otherwise would be combined with a priori LLRs from an outer decoder of a prior stage, are ignored so that the a priori LLRs themselves are used alone. The two embodiments can be used together.

Abstract: Provided are a method of detecting and isolating fault in sensors and a method of accommodating fault in sensors using the same. In the method of detecting and isolating fault in sensors, a one reduced-order parity vector is obtained by excluding the output of one sensor selected from n sensors, a two reduced-order parity vector is obtained by excluding output of two sensors selected from the n sensors, and when there are a plurality of parity vectors obtained at plural points of time, one reduced-order parity vectors are averaged to obtain an averaged one reduced-order parity vector and likewise, two reduced-order parity vectors are averaged to obtain an averaged two reduced-order parity vector. Therefore, a decrease in fault detection and isolation (FDI) performance can be hindered, and even when double faults occur, sensors to be excluded can be selected. Thus, a system including sensors has high reliability and high accuracy.

Abstract: For detecting an error of an A/D converter, which is designed to generate at least one digital output signal, which includes a quantity of output data bits, based on at least one analog input signal, and during a conversion, to generate a thermometer code which includes a quantity T of output data values, the detection method includes: ascertaining a first parity directly for the output data bits of the output signal; making a prediction for the output data bits on the basis of the T output data values of the thermometer code; ascertaining a second parity, which is a reverse of the first parity, for the predicted output data bits; and detecting an error for the A/D converter when both the first and second parities are identical.

Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.

Abstract: Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.

Abstract: A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

Abstract: A multicarrier data transmission scheme is provided. According to the provided scheme, a radio transmitter encodes data bits with different degrees, the degree of an encoded data bit being defined by the number of parity check equations protecting the data bit. The data bits are preferably encoded with an irregular low-density parity check (LDPC) code. The encoded data bits are then mapped to symbols. The symbols are allocated to subcarriers of a multicarrier radio signal on the basis of channel state information obtained from the radio receiver and the degree used with respect to each symbol. On the basis of the channel state information, a number of subcarriers are truncated due to high attenuation, and the number of subcarriers to be truncated relative to the total number of subcarriers is substantially fixed. The available transmit power to the non-truncated subcarriers. The multicarrier signal comprising symbols on the non-truncated subcarriers is then transmitted to the radio receiver.

Abstract: An optical disc using super-resolution effects that achieves higher-density recording exceeding the optical resolution suffers from the signal-quality degradation caused by the normal resolution component included in the reproduction signal. To address this problem, a data reproduction method is provided. In the method, characteristic error patterns are identified and parity check codes in conformity with run-length limited coding are used to carry out efficient and reliable error correction. Error patterns caused by the normal resolution crosstalk are localized in the leading edges of a mark following a long space and in the trailing edges of a long mark. Whether an error exists in the data is determined by use of the parity check codes. When an error occurs, a pattern in which an error is most likely to occur is selected from the above-mentioned patterns by taking account of the edge shift direction, and then the error therein is corrected.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: A method of transmitting data that includes controlling generation of bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks; and performing multi-level modulation for transmission based on the generated bit sequences.

Abstract: A low density parity check (LDPC) coding method, and more particularly, a method of executing LDPC coding using a parity check matrix is disclosed. The present invention comprises providing an information bit stream for channel encoding, and encoding the information bit stream by using a first parity check matrix including at least one row generated by combining at least two rows of a second parity check matrix.

Abstract: A transmitting apparatus, that includes a means for generating bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks and a modulator for performing multi-level modulation for transmission based on the generated bit sequences.

Abstract: A method and system for encoding a segment of user data words into a segment of code words so that both modulation constraints and a predetermined parity-check constraint are satisfied. Each segment of the user data is partitioned into several data words, and encoded separately by first and second types of component code, which are referred to as the normal constrained code and the parity-related constrained code, respectively. The parity-check constraint over the combined code word is achieved by concatenating the sequence of normal constrained code words with a specific parity-related constrained code word chosen from a candidate code word set. Both the component codes are finite-state constrained codes, which are designed to have rates close to the Shannon capacity. Furthermore, they are based on the same finite state machine (FSM), which enables them to be connected seamlessly, without violating the modulation constraints.

Abstract: Aspects of the embodiment include providing a semiconductor memory comprising; a plurality of memory blocks that includes a plurality of regular memory cells; a plurality of first parity blocks that are disposed in accordance with the plurality of memory blocks, wherein the plurality of first parity blocks include a first parity memory cell holding a first parity code; a second parity block that includes a second parity memory cell holding a second parity code having a parity bit corresponding to the first parity code; a parity error correction unit that corrects an error of the first parity code using the second parity code; and a data error correction unit that corrects an error of the data stored in a regular memory cell using the first parity code corrected by the parity error correction unit.

Abstract: The present invention relates to a method and a system for transmitting and receiving control information of an Multi-Input Multi-Output (MIMO) system, wherein the control information consists of information bits and parity bits. A base station transmits the control information including the location information for where the control information of the other terminal is transmitted. A terminal receives the control information of the other terminal based on the location information for where the control information of the other terminal is received. Therefore, the precoding matrix of the other terminal can be obtained from the received control information. The invention enables the removal of interference through the obtained precoding matrix when receiving a data symbol in an environment where a channel is not in a good state.

Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one access request involving a redundant array of independent disks (RAID) storage. The storage may be capable of accessing, in response, at least in part, to the at least one request an encryption and/or parity information. The encryption may be of at least one portion of the data and/or the parity information. The encryption may be stored in (1) encrypted disk stripes in the storage such that the data is unrecoverable based solely upon remaining unencrypted portion of the data and the parity information stored in the storage, and/or (2) one or more respective disk stripes having a number that is determined based at least in part upon one or more encryption levels, if any, associated with at least one characteristic of the data.

Abstract: In a transmission apparatus, a first parity calculation controller calculates parity by the frame and inserts a calculation result into a next frame to a first frame sequence. A second parity calculation controller calculates the parity by the frame and inserts a calculation result into a next frame to a second frame sequence. The second parity calculation controller receives from the first parity calculation controller first parity data which is a parity calculation result by the first parity calculation controller and which has the same value as that of a parity calculation result to be inserted into a target frame of a parity calculation in the second frame sequence. Then, the controller calculates the parity of the target frame including the first parity data and second parity data which is a parity calculation result of a previous frame in the second frame sequence before one frame of the target frame.

Abstract: Disclosed is a wireless communication apparatus in which reception precision characteristics are improved, by specially adapting the modulating processing in respect of the code words for each encoding system. A wireless communication apparatus (100) wherein an encoding processing section (120) includes a convolutional encoder that performs convolutional encoding of fixed information blocks made up of K bits. In code word partial sequences obtained on the basis of the head and tail in a fixed information block, a modulating section (130) maps bits, from bit groups constituting single symbols, to bits associated with groups having poor quality characteristics, prioritising systematic bits over parity bits. In this way, the reception quality characteristics in first code word partial sequences having good error characteristics is equalised.

Abstract: Low-latency programmable encoders, and more particularly, low-latency programmable encoders which use low-density parity check (LDPC) codes in combination with an outer systematic code. The LDPC encoder is programmable for any irregular circulant-based LDPC code. The code profile, block length, number of block rows, and number of block columns can vary. The LDPC encoding and the outer systematic code encoding can proceed in a parallel manner (e.g., simultaneously) instead of in a serial manner.

Abstract: A radio communication apparatus of the present invention aims at improving an error rate characteristic in the end receiver. A repeater (radio relay device) RS2 receives a signal transmitted from a repeater RS1 at a point of time of signal transmission from the repeater RS1, and detects whether or not an error exists in the signal at a point of time of transmission. Also, when the repeater RS2 detects the error from a systematic bit S of the transmitted signal from the repeater RS1, such repeater RS2 generates error position information EI, replace a part of a parity bit P with the error position information EI, and transmits a resultant signal. The error detection result is notified through the control channel. The mobile station (mobile terminal) MS makes an error correction based on the error position information EI, and demodulates the signal by executing an error correction decoding process.

Abstract: A data transmission apparatus in a wireless communication system includes: a data field generation unit configured to generate a data field for transmitting data; a signal field generation unit configured to generate a signal field for transmitting information on the data field; and a transmission unit configured to transmit a data packet containing the data field and the signal field. The signal field includes a rate bit, a reservation bit, a length bit, a parity check bit, and a tail bit, and the data transmission apparatus transmits a check bit for checking whether the signal field is normal or not through two or more bits of the bits of the signal field.

Abstract: A method begins by a processing module dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. The method continues with the processing module determining a plurality of sets of slice names corresponding to the plurality of sets of encoded data slices. The method continues with the processing module determining integrity information for the plurality of sets of slice names and sending the plurality of sets of encoded data slices, the plurality of sets of slice names, and the integrity information to a dispersed storage network memory for storage therein.

Abstract: An ECC decoder outputs, to a likelihood substituting unit, information on data in data blocks that is corrected to be valid. Based on the information, the likelihood substituting unit substitutes likelihood corresponding to the data corrected to be valid by the maximum value, and outputs it to an LDPC decoder. The LDPC decoder decodes user data with likelihoods partly substituted by the maximum value using LDPC parity, and calculates likelihood of data that constitutes the user data. The LDPC decoder outputs the calculated likelihood to a channel APP decoder as external data.

Abstract: A bit adding part acquires RSSI as measured by an RSSI measuring part, and adds “1” to each bit of protected audio data of an audio vocoder, if the acquired RSSI is smaller than a predetermined threshold value. If the acquired RSSI is equal to or greater than the predetermined threshold value, the bit adding part adds the bits of additional data to the respective bits of the protected data of the audio vocoder. A frame recovery part separates upper and lower order bits of deinterleaved data, and determines, based on CRC, whether eight data parts as obtained by combining the lower order bits as separated are valid. If so, the frame recovery part combines the eight data parts as the additional data to recovery additional information. In this way, additional data can be efficiently transmitted, while error correction being performed in accordance with communication environment.

Abstract: A write channel includes a pre-encoding module that encodes write data to produce pre-encoded data. An error correcting code (ECC) module generates ECC data based on the pre-encoded data. A post-encoding module encodes the ECC data to produce post-encoded data. A combining module combines the pre-encoded data and the post-encoded data for writing to the storage medium.

Abstract: A signal reception apparatus for a communication system is disclosed in which the signal reception apparatus receives a signal and decodes the received signal using a second decoding scheme approximated from a first decoding scheme. The second decoding scheme is a scheme of applying a correction value to a third decoding scheme approximated from the first decoding scheme, and the correction value is a value for correcting a difference between a first signal obtained by decoding the received signal using the first decoding scheme and a second signal obtained by decoding the received signal using the third decoding scheme.

Abstract: According to one embodiment, a decoder device includes a decoder configured to decode a to-be-decoded sequence by performing an iterative decoding process and to perform a parity check of a decoding result using a check matrix, a detector configured to detect that the to-be-decoded sequence is a non-code word based on a parity check result for each row of the check matrix by the decoder, and a controller configured to control the decoder according to a detection result of the detector.

Abstract: A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.

Abstract: Code designs for channel coding with side information (CCSI) based on combined source-channel coding are disclosed. These code designs combine trellis-coded quantization (TCQ) with irregular repeat accumulate (IRA) codes. The EXIT chart technique is used for IRA channel code design (and especially for capacity-approaching IRA channel code design). We emphasize the role of strong source coding and endeavor to achieve as much granular gain as possible by using TCQ. These code designs synergistically combine TCQ with IRA codes. By bringing together TCQ and EXIT chart-based IRA code designs, we are able to approach the theoretical limit of dirty-paper coding.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges(interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged(interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Abstract: A method for recovering from three failed data storage devices is disclosed. A plurality of data storage devices hold data, and a row parity storage device holds row parity for them. The data storage devices and the row parity storage device form a set of storage devices. A diagonal parity storage device and an anti-diagonal parity storage device hold parity computed diagonally over the set of storage devices. In the event of a failure of three data storage devices of the set of storage devices, a first failed storage device is chosen for first restoration. A missing block of the first failed storage device is computed by using the remaining set of storage devices, and the diagonal parity storage device, and the anti-diagonal parity storage device. The remaining two failed storage devices are restored by a diagonal parity restoration technique.