Abstract: A communication system that performs encoding and decoding for communication includes a transmitting apparatus and a receiving apparatus. The transmitting apparatus includes a turbo encoding unit including a first encoding unit that encodes an input signal and generates a first parity bit by bit-based encoding and n (n=1, 2, 3, . . . ) second encoding units that encode the input signal and generate second parity bits by bit-based encoding, and a symbol mapping unit that maps an output from the turbo encoding unit to a symbol by bit-based mapping operation and modulates the output. And the receiving apparatus includes a demodulating unit that demodulates a transmission signal, and a turbo decoding unit that performs turbo decoding on the demodulated signal by bit-based decoding.

Abstract: A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast channel change while giving robustness to the mobile service data.

Abstract: Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Abstract: A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.

Abstract: An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each of the M test samples being obtained by inverting a single bit from the M bits, keeping other bits unaltered. Each test sample is expanded and passed through a selected low pass filter (e.g., 15 kHz) to obtain a filtered output and a differential value between the test sample and its filtered output. The test sample producing the least differential value is chosen to replace the erroneous signal sample. The technique is especially applicable in NICAM demodulators receiving 14 bit sample signals (at 32 kHz) companded to (N) 10 bits from which (M) 6 MSB parity encoded bits are chosen for producing test samples.

Abstract: An encoding system includes a first low density parity check (LDPC) module and a second LDPC module. The first LDPC module is configured to generate a first encoded codeword by encoding a first codeword using a first LDPC code. The second LDPC module is configured to generate a second encoded codeword by encoding a second codeword using a second LDPC code. Signals based on the first encoded codeword and signals based on the second encoded codeword are transmitted over a communications channel. The first LDPC code is defined by a first parity check matrix and the second LDPC code is defined by a second parity check matrix. The second parity check matrix includes the first parity check matrix, a zero matrix, and a supplementary matrix.

Abstract: A method and apparatus for distributing dynamically reconfigurable content to a mobile device is provided. One embodiment of a method for encoding a data stream to enable error correction by a receiver of the data stream includes storing a block of the data stream in a first memory array, processing the first memory array to produce a second memory array, inverting the second memory array, and storing the second memory array, as inverted, as a third memory array.

Abstract: The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1; determining a second demodulated symbol r2; determining a first parity symbol p1; determining a second parity symbol p2; determining a super-parity symbol q1; and detecting a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.

Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

Abstract: Different transmissions based on different content blocks which were segmented from the same digital content according to different segmentation schemes, where each of the content blocks has any substring in common with at least one of the other content blocks, are received by a receiving radio communication station, for example a mobile telephone or a mobile network base station. Certain encoded received bits derived from different ones of the transmissions are combined into combined bits. Other encoded received bits derived from one or more of the different transmissions are provided together with the combined bits to a decoder.

Abstract: A digital broadcasting system comprising of a digital broadcasting station, a set of digital broadcast receivers, and a switched network, wherein the digital broadcasting station transmits a digital signal to the set of digital broadcast receivers, and the digital broadcast receivers exchange error correction information with each other using the network to compensate errors in local receptions of the digital signal at each digital broadcast receiver location.

Abstract: A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit.

Abstract: A method and apparatus for decoding transmissions in a wireless communications network is provided. A receiver includes a receive path. The receive path includes a decoder configured to perform low density parity check decoding. The decoder includes a number of Context Reconfigurable Instruction Set Processors (CRISPs). The CRISPs are configured to process received data in parallel. The decoder includes a plurality of memory units, and each of the CRISPs includes a plurality of processors.

Abstract: Provided is a systematic encoder of cyclic codes for partially written codewords in flash memories wherein all bits of an erased but unwritten area have a default value such as one. In the case where the host writes data to one or a plurality of discontinuous fragments in an area reserved for storing the message section of a codeword in the flash memory, the encoder computes the parity of the codeword by using only the data written to the flash memory as input and by asserting that all bits in the gaps between the written fragments have the default erased value, such that after both the data and the parity are written to the flash memory, the area reserved for storing the codeword would contain a valid codeword. On read back, the host reads the entire codeword area from the flash memory without having to distinguish between the written and unwritten fragments.

Abstract: In one embodiment, a method for writing data to a storage-device array (i) including three or more storage devices and (ii) having a plurality of stripes, each stripe having two or more sector levels, each sector level containing one sector on each storage device in the array at corresponding addresses across the storage devices. The method includes: (a) calculating a parity index based on (i) an index value for a current stripe and (ii) the number of storage devices in the array, the parity index identifying a first storage device for parity data for the current stripe; and (b) at each sector level of the current stripe: (b1) writing parity data to the first storage device identified by the parity index; and (b2) writing information to the remaining storage devices.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of communicating data over wireless communication symbols with check-code. For example, a wireless communication unit may transmit a sequence of wireless communication symbols representing transmitted data bits, wherein a symbol of the symbols includes at least one data block, which includes a set of data bits and a set of repetition bits, the set of data bits including a first number of the transmitted data bits, and the set of repetition bits including a second number of bits, which are identical to at least a subset of the set of data bits, wherein the symbol includes at least one plurality of check-code bits corresponding to the at least one data block, respectively, and wherein the first and second numbers are based on a number of the transmitted data bits, a symbol bit-size of the symbol, at least one value related to at least one of a data-block bit-size of the data block and a number of the plurality of check-code bits.

Abstract: In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: An encryption key interface system (200) includes a universal asynchronous receiver transmitter (UART) peripheral (209) that communicates with a key variable loader (KVL) (201) through a communications link (205, 207). A driver application (211) associated with the UART peripheral (209) is used to both receive and transmit commands to the KVL (201). The invention operates to allow the driver application (211) to communicate key command information to the KVL (201) without the use of a timer peripheral enabling the system to interface with a much broader range of devices utilizing encryption keys without requiring the use of timer system resources.

Abstract: To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

Abstract: An apparatus and method for transmitting/receiving a signal in a communication system are provided. The method includes inputting an information word during initial transmission and transmitting a first code word created by encoding the inputted information word based on a first coding ratio, and transmitting a portion of a second code word created by encoding the first code word based on a second coding ratio at a retransmission request. Accordingly, the apparatus and method provide for transmitting/receiving signals in a communication system in such a manner that the complexity of the communication system is reduced.

Abstract: A communication system employs discontinuous transmission to create gaps in transmission during which a transmitting device (200) can receive. When the transmission of a data block coincides with a transmission gap such that a portion of the data block is not transmitted, the block is retransmitted later. Prior to the retransmission, the data in the data block is reordered. The reordering may be predetermined, or may be selected to ensure that the same portion of data does not coincide with a transmission gap in the retransmission.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: A method and an apparatus for are provided. In a method for transmitting signaling information in a digital broadcasting system, a transmitter transmits signaling information, and an information bit stream is received. The received information bit stream is encoded and a parity bit is added. The parity bit is punctured such that parity bits of different patterns are formed between adjacent frames.

Abstract: A system for use in one-way communications takes data from a source and parses it into work units. The work units may have a fixed size. The data of the work units is given to a redundant array of independent disks (RAID) library. The RAID library applies parity to the data and produces a number of output streams. Each stream includes data from the work units and redundant data from the parity application. The streams are combined and sent over a network. The inverse parity is applied on the receiving side to recreate the data. The redundant data is used in place of any data having an error condition, such as being lost or corrupted. The data is reconstructed on the receiving end without the need to resend data.

Abstract: Code designs for channel coding with side information (CCSI) based on combined source-channel coding are disclosed. These code designs combine trellis-coded quantization (TCQ) with irregular repeat accumulate (IRA) codes. The EXIT chart technique is used for IRA channel code design (and especially for capacity-approaching IRA channel code design). We emphasize the role of strong source coding and endeavor to achieve as much granular gain as possible by using TCQ. These code designs synergistically combine TCQ with IRA codes. By bringing together TCQ and EXIT chart-based IRA code designs, we are able to approach the theoretical limit of dirty-paper coding.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: In a Redundant Array of Independent Discs (RAID) type memory, dual parities P and Q are generated by a dual XOR engine that performs a plain XOR operation for parity P and a weighted XOR operation for parity Q. The plain and weighted XOR operations may be performed in a single pass.

Abstract: Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

Abstract: A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after transferring the parity to the second buffer, transferring a main data in the data read into the first buffer to the second buffer, on the basis of the parity, correcting an error in the main data transferred to the second buffer, and transferring an error-corrected main data to a third buffer.

Abstract: An apparatus and method are provided for transmitting and receiving in a communication/broadcasting system. The method includes generating a codeword including a first parity bit using a first parity-check matrix, generating an additional parity bit based on a second parity-check matrix, the second parity-check matrix being an extension of the first parity-check matrix, and transmitting the codeword and the additional parity bit.

Abstract: A group of numbers from which the smallest and second-smallest are to be selected are compared in a cascaded tree. Each comparison stage will select the smallest number from two numbers output by the previous stage, into which four numbers are input. The second-smallest number is one of the other three inputs to the previous stage and, as before, all bits of the second-smallest number will not be known until the smallest number is determined. However, because at each stage of the determination, the next stage is reached because the bit values being examined are the same, those bit values of the second-smallest number (and indeed of the smallest number) are known ahead of the final determination of the smallest number. Accordingly, one can begin to output bits of the second-smallest number (as well as of the smallest number) even before that final determination.

Abstract: A data access apparatus includes: a flash memory controller; a mirror means; and a flash memory including at least one data region and at least one mirror region. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.

Abstract: A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Abstract: Various systems and methods for detecting subsystem installation defects are provided. In one example method, a test value is generated in a detection tool to be applied to a subsystem through a plurality of interconnects. A first parity bit is then generated for the test value using the detection tool, and the test value is transmitted to the subsystem. A second parity bit is generated for the test value in the subsystem. Then, the first parity bit is compared with the second parity bit to determine if a fault exists in one of the interconnects.

Abstract: Techniques to perform iterative decoding of concatenated low-density parity-check codes (LDPC) are described. Iterative decoding of the concatenated code is achieved by performing T common iterations, wherein a common iteration comprises t1 decoding iterations on the inner LDPC code my means of a first decoder (340) followed by t2 decoding iterations on the outer LDPC code my means of a second decoder (350) , and wherein the two decoders exchange soft-output information.

Abstract: A coding system in which the coding apparatus generates information bits and parity bits and transmits the parity bits and information bits selectively to the decoding apparatus. The decoding apparatus predicts the information bits, stores the predicted information bits, also stores the parity and information bits received from the encoding apparatus, combines the received information bits with the predicted information bits, and uses an error correcting decoder to decode the combined information bits and the stored parity bits. Combining the predicted information bits with received information bits improves decoding accuracy and enables the decoding apparatus to conserve computational resources.

Abstract: A method for creating cyclic permutation matrices P (810), with an arbitrary size Z×Z set by a parameter Z5 and which are used to create one or more LDPC related matrices in OFDMA systems, comprising: defining an integer value Z; creating an initial matrix (810); creating a matrix (810) by using cyclic shifts to each row; repeating stage 3, up to Z?2 times as required, thus creating up to Z?2 matrices: P(o) . . . P(Z?I); creating an additional stairs matrix P(st). A method for using cyclic per-mutation matrixes P (840), with a fixed size Z×Z set by a parameter Z, and which are used to create one or more LDPC related matrices (820) in OFDMA systems, comprising: defining an integer value Z; storing in memory means an initial matrix (810) and its cyclic shifts permutations (840), thus keeping memory means matrices: P(o) . . . P(Z?I); storing an additional stairs matrix P(st) (840); using these matrices (810) to create LDPC related matrices (840) or LDPC operations.

Abstract: Systems and methods are provided for a quasi-cyclic low-density parity check (QC-LDPC) encoders that have reduced memory requirements. In some embodiments, the LDPC encoder may store a quasi-cyclic parity seed matrix instead of a full code generator matrix. The LDPC encoder may receive a plurality of user symbols and compute a parity seed vector based at least in part on the received user symbols. The LDPC encoder may then use the quasi-cyclic parity seed matrix and the parity seed vector to generate a plurality of parity symbols for the user symbols. In some embodiments, the LDPC encoder may generate a full code generator matrix from a quasi-cyclic parity seed matrix instead of storing the full code generator matrix.

Abstract: Arbitrarily high data transmission rates may be achieved by the use of N-dimensional, LDPC-coded modulation. N orthonormal basis functions are employed using coherent reception, resulting in a proportional increase in transmission rate with only a modest increase in bit-error ratio.

Abstract: Data is decoded by obtaining a cost function. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Processing related to error correction decoding is performed on the selected group of check nodes.

Abstract: A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.

Abstract: A wireless communication infrastructure entity including a transceiver coupled to a controller configured to generate parity bits based on an information word. The controller is also configured to encode the parity bits based on a communication configuration, e.g., symbol information, wherein the encoded parity bits are combined with the information word for transmission by the transceiver. A user terminal in receipt of the information word includes a controller configured to determine the communication configuration based on a set of configuration indicator bits used to encode the parity bits.

Abstract: A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

Abstract: A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

Abstract: A code generating device includes a code word generating section which generates a code word with a predetermined code word length by applying a second matrix Gq of a second error detection method with regard to an information word A? which has been input, and a code word conversion section which converts the code word generated by the code word generating section based on an added fixed value (Qa+Pa) which is formed from respective code words Qa and Pa which are obtained by the second matrix Gq and a first matrix Gp of a first error detection method being respectively applied to an information word A which is formed from a specific data string.