Check Character Patents (Class 714/807)
  • Patent number: 10297274
    Abstract: A method for recording parity data of data stripes within shingled media recording bands in a redundant array of independent disks can be accomplished using a plurality of shingled media recording (SMR) hard disk drives (HDD) each with a plurality of shingled data bands. A data stream received from a host computer system is sequentially stored to a plurality of block segments in successive order, one stripe at a time successively. Each of the shingled data bands possess n data blocks (or multiple data blocks that are grouped together as a data unit) that are successively ordered, each corresponding successive data block from all of the SMR HDDs defines a data stripe, accordingly n data blocks in each SMR HDD defines n stripes across the shingled data bands. A transaction group sync triggers a halt to writing the data stream. The rest of the data stripe is written with fill bits.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Spectra Logic, Corp.
    Inventor: Alan William Somers
  • Patent number: 10224953
    Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 5, 2019
    Assignee: GE VIDEO COMPRESSION, LLC
    Inventors: Detlev Marpe, Tung Nguyen, Heiko Schwarz, Thomas Wiegand
  • Patent number: 10194337
    Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Amir Aminzadeh Gohari, Shailesh Maheshwari, Sandeep Urgaonkar, Alok Mitra, Mohammed M. Rumi, Vaibhav Kumar, Uppinder Singh Babbar, Thomas Klingenbrunn, Bao Vinh Nguyen, Mathias Kohlenz, Gautam Sheoran, Daisuke Terasawa, Iain Finlay
  • Patent number: 10162702
    Abstract: In one embodiment, memory circuitry includes an error-correction code (ECC) encoder, memory, and an ECC decoder. The ECC encoder performs encoding, based on an ECC algorithm having an algorithm size, on an algorithm-size segment of input user data to generate a corresponding subset of parity data for the segment of input user data. The memory has input user data and corresponding parity data written based on a write data size and stored user data and corresponding stored parity data read based on a read data size. The ECC decoder performs decoding, based on the ECC algorithm, on an algorithm-size segment of retrieved user data and a corresponding subset of retrieved parity data, wherein the algorithm size is smaller than the write data size or the read data size. The memory circuitry enables conventional SEC-DED algorithms to be used when the write and read data sizes are different.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventor: Peng Yao
  • Patent number: 10147500
    Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yu Cai, Fan Zhang, June Lee
  • Patent number: 10142229
    Abstract: A system performs tunneling of real-time communications (“RTC”). The system establishes a tunnel between a tunneling client and a tunneling server. The system then receives a packet over the tunnel. The packet is configured according to an outer transport protocol of the tunnel and includes a datagram-based payload and a stream-based header. The system processes the packet according to a datagram-based outer transport protocol based on information in the stream-based header.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: November 27, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Rolando Herrero, Henry Katz, Michael Y. Deng
  • Patent number: 10084635
    Abstract: This disclosure describes methods, apparatus, and systems related to a high efficiency signal field coding system. A device may determine a high efficiency preamble in accordance with a high efficiency communication standard to be sent to one or more devices, the high efficiency preamble including at least in part a high efficiency signal field. The device may determine a common part included in the high efficiency signal field. The device may determine one or more device specific parts associated with the one or more devices. The device may encode the high efficiency signal field based at least in part on a predetermination combination of at least one of the common part or the one or more device specific parts. The device may cause to send the high efficiency preamble to the one or more devices, including the encoded high efficiency signal field.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 25, 2018
    Assignee: Intel IP Corporation
    Inventors: Xiaogang Chen, Qinghua Li, Yuan Zhu, Hujun Yin
  • Patent number: 10048877
    Abstract: Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 14, 2018
    Assignee: INTEL CORPORATION
    Inventors: Shaun M. Miller, Richard P. Mangold
  • Patent number: 10033563
    Abstract: A wireless network interface device selects a guard interval from a set of guard intervals including a first guard interval, a second guard interval, and a third guard interval, where in the first guard interval has a length that is 50% of a length of the second guard interval, and wherein the length of the second guard interval is 50% of a length of the third guard interval. The wireless network interface device generates a preamble of a data unit to include: a legacy signal field, a repetition of the legacy field, and a non-legacy field that includes a field that indicates the selected guard interval. The wireless network interface device generates a data portion of the data unit, including generating orthogonal frequency division multiplexing (OFDM) symbols of the data portion using the selected guard interval.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: July 24, 2018
    Assignee: Marvell World Trade Ltd.
    Inventor: Hongyuan Zhang
  • Patent number: 9983925
    Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
  • Patent number: 9866905
    Abstract: A system and method for polling a plurality of client devices of different types are provided. A reboot and polling tool pre-polls client devices, where the pre-poll is specific to a type of client device and identifies a state of the client devices. The reboot and polling tool then executes a script on the client devices that changes the state of the plurality of client devices. After the script is executed, the reboot and polling tool post-polls the client devices where the post-poll is specific to the type of client device and the post-poll provides information that identifies changes in the state of the client devices caused by the script.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 9, 2018
    Assignee: CSC Holdings, LLC
    Inventor: Christopher Quinn
  • Patent number: 9847860
    Abstract: There is provided a mechanism for conducting a communication between at least one communication network control element such as an eNB and at least one communication element such as a UE wherein a DM RS based communication mode is used. DMRS (scrambling) sequences are generated wherein each DMRS sequence includes a set of calculation parameters being specific for the respective DMRS sequence, wherein the set of calculation parameters is configurable by the eNB during communication. For initializing each of the at least one scrambling sequence before receiving the configuration information, i.e. in an initial phase of the communication, a predetermined default value based on e.g. an UE_ID and being selectable from a set of predetermined default values is used for the set of calculation parameters in each DMRS sequence.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: December 19, 2017
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Xiaoyi Wang, Peter Skov, Jingxiu Liu, DeShan Miao
  • Patent number: 9846629
    Abstract: A method and computer device for storage and retrieval of a data object on a storage medium. The method includes steps of disassembling the data object into a predetermined number of redundant sub blocks, storing the redundant sub blocks on the storage medium, retrieving at least a predetermined multiple of a minimal spreading requirement of the redundant sub blocks from the storage medium, and assembling the data object from any combination of a particular number of the redundant sub blocks, the particular number corresponding to a predetermined multiple of a minimal spreading requirement. The computer device includes modules for performing the steps.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: December 19, 2017
    Assignee: Amplidata NV
    Inventors: Frederik De Schrijver, Romain Raymond Agnes Slootmaekers, Bastiaan Stougie, Joost Yervante Damad, Wim De Wispelaere, Wouter Van Eetvelde, Bart De Vylder
  • Patent number: 9842021
    Abstract: A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: John B Halbert, Kuljit S Bains
  • Patent number: 9772393
    Abstract: One of the embodiments of the present invention relates to a method for modulation. The method comprises: providing a first bit sequence of continuous bits “1” or continuous bits “0” generating a second bit sequence by replacing, in each of a plurality of modulation intervals with a predetermined bit number, at least one bit of the first bit sequence at least one fixed position of the respective modulation interval with one information bit from an information bit sequence; and modulating the second bit sequence so as to generate a positioning packet with a modulated continuous wave signal for transmission. The embodiments further relate to a method for demodulation. Embodiments of the present invention also provide corresponding apparatuses and computer program products.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 26, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Xianjun Jiao, Xin Zhang, Canfeng Chen
  • Patent number: 9740422
    Abstract: A system and method for improving deduplication techniques in a data storage system. In one embodiment, a data storage system is configured to divide first data into a first plurality of segments, to generate a first plurality of fingerprints that are each to be associated with a segment, to identify second data that is to be updated by the first data and a second plurality of fingerprints associated with the second data, to load the second data and the second plurality of fingerprints from persistent storage of the data storage system into working memory, to determine, in the working memory, that a first segment of the first plurality of segments updates the second data by comparing a first fingerprint associated with the first segment to the second plurality of fingerprints, and to overwrite a second segment of the second data with the first segment in response to the determination.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 22, 2017
    Assignee: EMC IP Holding Company LLC
    Inventor: Kadir Ozdemir
  • Patent number: 9731733
    Abstract: A distributed interlocking device, architecture and process are disclosed, and are based on segregating the vital logic for a signal installation by type of signal equipment. A plurality of intelligent signal devices is disclosed, wherein each intelligent signal device is used to control a basic signal unit. In turn, a signal unit includes a set of signal apparatuses that are geographically and logically interrelated. An intelligent signal device receives data related to the states of other signal devices, determines and controls its own operational states, and communicates its own operational states to other devices. A generic intelligent signal device is also disclosed, and is based on a parameterization approach that incorporates a plurality of vital parameters into the vital logic of the device. The device is then customized to a site specific location by activating the appropriate parameters for that location.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: August 15, 2017
    Assignee: SIEMENS INDUSTRY, INC.
    Inventor: Nabil Ghaly
  • Patent number: 9696931
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include receiving a request to create a storage entity on a storage system, the storage entity including data and metadata, the metadata used to manage the storage entity. Upon receiving the request, multiple metadata attributes are identified for the metadata, and for each given identified metadata attribute, a respective metadata region is created on the storage system, and a subset of the metadata having the given metadata attribute is stored to the respective metadata region. Finally, a data region is created on the storage system, and the data is stored to the data region.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yifat Kuttner, Sergey Marenkov, Ury Matarazzo, Yosef Shatsky
  • Patent number: 9639417
    Abstract: A storage control apparatus controls a storage device. The storage device includes a first storage area and a second storage area different from the first storage area. An error detection information storage unit generates an ECC for each of data blocks in data to be written, as error detection information. The error detection information storage unit stores generated ECC 1 to ECC 4 in the first storage area. A data storage unit stores data blocks DB1 to DB4 in the second storage area. A detection unit performs error detection on each of the data blocks according to the error detection information read from the first storage area and the data to be written read from the second storage area.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 2, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Keiya Ishikawa, Nina Tsukamoto
  • Patent number: 9639416
    Abstract: A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and reweights the contribution of all symbols in the message, while the N reweighting modules in the N parallel feed-forward paths provide the contributions of the symbols that are “in-flight” within the feedback loop to the final CRC checksum.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 2, 2017
    Assignee: Altera Corporation
    Inventors: David Bruce Parlour, Christopher D. Ebeling, Michael Glenn Wrighton, Michael Alan Baxter
  • Patent number: 9590765
    Abstract: Resource elements from multiple code blocks are separated into different groups, and the code bits of the resource elements within each group are decoded without waiting for a completed reception of a transport block to start decoding. Coded bits from multiple code blocks are similarly separated into different groups, and code blocks containing coded bits within each group are decoded. A first CRC is attached to the transport block and a second CRC is attached to at least one code block from the transport block. An improved channel interleaver maps coded bits of different code blocks to modulation symbols, and maps modulation symbols to time, frequency, and spatial resources, to make sure each code block receives approximately the same level of protection.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhouyue Pi, Farooq Khan
  • Patent number: 9575905
    Abstract: A storage controller is provided. The storage controller includes a memory storing an indication of a current owner, a previous owner, and a preferred owner for each of one or more logical volumes. The storage controller is configured to write protect the logical volumes where the current owner and the preferred owner is the storage controller and the previous owner of the logical volumes was a different storage controller. For the logical volumes where the storage controller is the preferred but not the current owner, the storage controller is set as the current and preferred owner of the logical volumes that the different storage controller was the current but not the preferred owner for, storage controller is set as the previous owner of the logical volumes that the storage controller is the current and preferred owner of, and allowing read and write access to the one or more logical volumes.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 21, 2017
    Assignee: Seagate Technology LLC
    Inventor: Ritvik Viswanatha
  • Patent number: 9578543
    Abstract: Overhead associated with packet communication is reduced by combining or eliminating one or more fields of a packet. In some implementations, a reduction in overhead associated with packets employing security (e.g., IEEE 802.11ah packets) can be achieved by reducing overhead associated with verification-related fields. For example, a packet can include a merged frame check sequence (FCS) and an integrity check value (ICV). In some implementations, an FCS is omitted from a packet.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: James Simon Cho, Kevin Neal Hayes
  • Patent number: 9571236
    Abstract: The invention relates to the field of communications and provides a method of and apparatus for transmitting downlink control information, and the method includes: for transmission of DCI over any carrier, determining DAI information fields in uplink scheduling DCI and downlink scheduling DCI to be carried over the carrier and an HARQ process number information field in the downlink scheduling DCI dependent upon PDSCH HARQ feedback scheme currently in use; and determining a UL index information field in the uplink scheduling DCI to be carried over the carrier dependent upon a PUSCH scheduling scheme currently in use, so that an appropriate DCI design scheme is provided for an application scenario of across-system carrier aggregation to thereby satisfy a demand for the use of an evolved process in an LTE system and improve effectively the performance of the system.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 14, 2017
    Assignee: China Academy of Telecommunications Technology
    Inventors: Yanan Lin, Zukang Shen, Qianqian Si, Xueming Pan
  • Patent number: 9542261
    Abstract: Methods, systems, and computer readable media for a multi-packet CRC engine are disclosed. According to one aspect, the subject matter described herein includes a system for a multi-packet CRC engine. The system includes an input module for receiving set of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits, multiple CRC pre-calculation blocks (CPBs) that receive from the input module subsets of the set of bits, each subset containing a portion of a packet less than all of a packet, and calculate a CRC value for its respective subset of bits, and an output module for receiving the calculated CRC values from the CPBs and using the calculated CRC values to produce packet-specific CRC values, where the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: January 10, 2017
    Assignee: Ixia
    Inventors: Gerald Raymond Pepper, Brian Adam Wilson
  • Patent number: 9525513
    Abstract: Resource elements from multiple code blocks are separated into different groups, and decoding the code bits of the resource elements within each group without waiting for a completed reception of a transport block to start decoding. Coded bits from multiple code blocks are separated into different groups, and the code blocks containing coded bits within each group are decoded. A first CRC is attached to the transport block and a second CRC is attached to at least one code block from the transport block. An improved channel interleaver design includes mapping from coded bits of different code blocks to modulation symbols, and mapping from modulation symbols to time, frequency, and spatial resources, to make sure each code block to get roughly the same level of protection.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhouyue Pi, Farooq Khan
  • Patent number: 9471416
    Abstract: A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 18, 2016
    Assignee: Cavium, Inc.
    Inventor: Steven C. Barner
  • Patent number: 9454448
    Abstract: A method of fault testing in a storage device comprises testing, in accordance with a storage device testing protocol, operability of a plurality of distinct portions on the storage device. The testing includes, for each of the plurality of distinct portions on the storage device: performing one or more operations on a respective portion of the storage device; recording data corresponding to electrical current drawn during performance of the one or more operations on the respective portion of the storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and, in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions including updating a mapping of the storage device to mark the respective portion as a known-bad portion.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Robert W. Ellis
  • Patent number: 9451610
    Abstract: A communicating unit of a base station performs a plurality of periodic communication services with a wireless terminal. A communication control unit of the base station includes, in a control channel, identification information for distinguishing the periodic communication services one from the other to thereby allow the wireless terminal to control at least one of activation and release of each of the periodic communication services. A communicating unit of the wireless terminal performs the plurality of periodic communication services with the base station. A communication control unit of the wireless terminal controls at least one of the activation and the release of each of the periodic communication services using the identification information included in the control channel transmitted from the base station.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: September 20, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiaki Ohta, Yoshihiro Kawasaki, Yoshiharu Tajima, Yoshinori Tanaka
  • Patent number: 9448876
    Abstract: A method of fault detection includes, while in normal operation: recording data corresponding to measurements of electrical current drawn during performance of a respective operation on a specified portion of a storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions, the one or more remedial actions including marking the specified portion as a known-bad portion.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Robert W. Ellis
  • Patent number: 9412412
    Abstract: A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 9, 2016
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventors: Kevan Flint Rehm, Judith Ann Schmitz, Joseph Carl Nemeth, John Michael Sygulla
  • Patent number: 9389937
    Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 12, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
  • Patent number: 9384076
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for allocating machine check architecture banks. The processing device includes a plurality of machine check architecture banks to communicate a machine check error. The processing also includes an allocator to allocate during runtime of the processor a target machine check architecture bank of the plurality of machine check architecture banks. The runtime of the processor is during an occurrence of the machine check error.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: William G. Auld, Ashok Raj, Malini K. Bhandaru
  • Patent number: 9384440
    Abstract: Transponder (104), comprising a storage unit (106) having stored a number of different applications, a processing unit (108) which, on request of a reader (102), is adapted to generate a response interpretable using an encryption scheme known by both the transponder (104) and the reader (102) so that the reader (102) is capable of determining whether an application is supported by the transponder (104) by analyzing the response using the encryption scheme, and a transmission unit (110) adapted to send the response to said reader (102).
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: July 5, 2016
    Assignee: NXP B.V.
    Inventors: Susanne Stern, Paul Hubmer, Peter Thueringer, Bruce Murray, Heike Neumann, Hans De Jong
  • Patent number: 9324332
    Abstract: A method for providing information on the validity of encoded audio data is disclosed, the encoded audio data being a series of coded audio data units. Each coded audio data unit can include information on the valid audio data. The method includes: providing either information on a coded audio data level which describes the amount of data at the beginning of an audio data unit being invalid, or providing information on a coded audio data level which describes the amount of data at the end of an audio data unit being invalid, or providing information on a coded audio data level which describes both the amount of data at the beginning and the end of an audio data unit being invalid. A method for receiving encoded data including information on the validity of data and providing decoded output data is also disclosed. Furthermore, a corresponding encoder and a corresponding decoder are disclosed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: April 26, 2016
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWAN
    Inventors: Stefan Doehla, Ralph Sperschneider
  • Patent number: 9292548
    Abstract: In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Schuyler Eldridge, Gilbert M. Wolrich, Erdinc Ozturk, Wajdi K. Feghali
  • Patent number: 9252918
    Abstract: A communication system is provided wherein a user equipment (UE) receives control information from a wireless network. The UE monitors control channel candidates using common reference signals (CRS) and monitors enhanced control channel candidates using demodulation reference signals (DMRS) when the UE is configured in a first transmission mode, such as transmission mode 9, for receiving a downlink shared traffic channel based on DMRS. The UE monitors control channel candidates only using CRS when the UE is configured in a second transmission mode, such as any of transmission modes 1-6, for receiving a downlink shared traffic channel based on CRS. The UE then receives downlink control information (DCI) in a subframe in one of the monitored control channel candidates or enhanced control channel candidates in the subframe.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: February 2, 2016
    Assignee: Google Technology Holdings LLC
    Inventors: Ravikiran Nory, Sandeep H. Krishnamurthy, Robert T. Love, Vijay Nangia, Ajit Nimbalker, Krishna Kamal Sayana, Xiangyang Zhuang
  • Patent number: 9164730
    Abstract: A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 20, 2015
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 9166742
    Abstract: A frame configuration used for both SISO transmission and MISO and/or MIMO transmission. According to the frame configuration, a frame has a preamble, a control symbol, and transmission data symbols. A transmission device includes the designation of a transmission scheme of the transmission data symbols in the control symbol and includes the designation of a transmission scheme of the control symbol in the preamble. This frame configuration improves the reception performance (detection performance) of a reception device.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 20, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Mikihiro Ouchi, Yutaka Murakami, Tomohiro Kimura
  • Patent number: 9161347
    Abstract: A wireless communication base station apparatus that allows the number of times of blind decodings at a mobile station to be reduced without increasing the overhead caused by notifying information. In this apparatus, a CCE allocation part allocates allocation information allocated to a PDCCH received from modulation parts to a particular one of a plurality of search spaces that is corresponding to a CCE aggregation size of the PDCCH. A placement part then places the allocation information in one of downstream line resources, reserved for the PDCCH, that is corresponding to the CCE of the particular search space to which the allocation information has been allocated. A radio transmission part then transmits an OFDM symbol, in which the allocation information has been placed, to the mobile station from an antenna.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 13, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Akihiko Nishio, Seigo Nakao
  • Patent number: 9160485
    Abstract: A method and apparatus for encoding a transport block are provided. The method for encoding the transport block includes: determining, by a transmitter, a size of transport block; dividing, by the transmitter, the transport block into at least one code block based on the size of transport block; interleaving, by the transmitter, the at least one code block by an interleaver; and performing, by the transmitter, a turbo coding for the interleaved at least one code block, wherein the size of transport block is determined based on the number of the divided code blocks.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: October 13, 2015
    Assignee: LG Electronics Inc.
    Inventors: Bong Hoe Kim, Dong Youn Seo, Joon Kui Ahn
  • Patent number: 9154163
    Abstract: Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: October 6, 2015
    Assignee: BLACKARROW, INC.
    Inventor: Bjorn Engberg
  • Patent number: 9106388
    Abstract: Methods and devices generate cyclic redundancy check (CRC) values for a sequence of parallel words of data. The data words may have only some of the bits enabled. The input words are preconditioned, and then a common block generates a CRC remainder value. A specific preconditioning is selected based on the number of enabled bits. Additional post-processing may be performed to the CRC remainder.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 11, 2015
    Assignee: Microsemi Communications, Inc.
    Inventors: Venkat Praveen Kumar K., Nihit Chattar, Dishant Singh Rajput
  • Publication number: 20150149874
    Abstract: A reliability metric is used for determining whether to prune a decoding hypothesis. For example, a reliability metric can be generated for each possible hypothesis generated during blind decoding operations. The reliability metric can then be used in a pruning process whereby a determination to prune a given hypothesis is based on whether the corresponding reliability metric is above or below a reliability metric threshold. In some aspects, the reliability metric is based on the correlation between the symbols of a hypothesis and re-encoded symbols that are based on the hypothesis, whereby the correlation is normalized using an estimated power parameter that is independent of the hypothesis. Through the use of the reliability metric, decoding may be achieved with a low probability of false passes (in the case of noise) and a low probability of missed detection (in the case of a real signal).
    Type: Application
    Filed: May 9, 2014
    Publication date: May 28, 2015
    Applicant: QUALCOMM Incorporated
    Inventor: Roee Cohen
  • Publication number: 20150135042
    Abstract: A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 14, 2015
    Inventors: KWANGSEOK IM, JUNG-YEON YOON, HAN-JU LEE, HA-NEUL JEONG
  • Patent number: 9032277
    Abstract: In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Chuck Rumbolt
  • Patent number: 9026434
    Abstract: An audio coding terminal and method is provided. The terminal includes a coding mode setting unit to set an operation mode, from plural operation modes, for input audio coding by a codec configured to code the input audio based on the set operation mode such that when the set operation mode is a high frame erasure rate (FER) mode the codec codes a current frame of the input audio according to a select frame erasure concealment (FEC) mode of one or more FEC modes. Upon the setting of the operation mode to be the High FER mode the one FEC mode is selected, from the one or more FEC modes predetermined for the High FER mode, to control the codec by incorporating of redundancy within a coding of the input audio or as separate redundancy information separate from the coded input audio according to the selected one FEC mode.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Steven Craig Greer, Hosang Sung
  • Patent number: 9026883
    Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Chiaming Lo, Yi-Chang Liu, Lawrence Chen Lee, Wei-Yu Lai, Wei-De Wu
  • Patent number: 9026718
    Abstract: A method for recovering from an interruption during a Firmware Over-The-Air (FOTA) update is provided. The method includes identifying a missing block of a plurality of blocks to be updated in the first memory, the missing block corresponding to a block being updated when the interruption occurred, copying a backup block into a backup buffer, simulating an application of the FOTA update in a second memory, the simulation including, for each block of the plurality of blocks to be updated, performing a reversible operation on the contents of the backup buffer and an updated block, and updating the backup buffer with the operation result, replacing the missing block with the updated backup buffer, and resuming the FOTA update.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bryan Eugene Rabeler, Tao Xue
  • Publication number: 20150113363
    Abstract: A method for a first communication device transmitting data to a second communication device, according to one embodiment of the present invention, comprises the steps of: the first communication device generating a safety unique identifier by using a unique identifier of the first communication device and a unique identifier of the second communication device, in order to confirm the validity of connection between the first communication device and the second communication device; the first communication device calculating a data error detection code for detecting an error by using the safety unique identifier and the data; the first communication device generating a packet comprising the data and the data error detection code; and the first communication device transmitting the packet to the second communication device.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 23, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Sung Han Lee, Dae Hyun Kwon, Joon Seok Oh