Abstract: A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function.

Abstract: A digital electronic message comprising datawords to be transmitted in a communications system can be encoded prior to transmission using an asymmetric error detection coding scheme. The coding scheme is asymmetric because the coding scheme includes multiple codeword groups each with a different minimum coding distance. The codewords in a group having a greater minimum coding distance can correspond to datawords that have a relatively high susceptibility to transmission errors. The codewords in a group having a lesser minimum coding distance can correspond to datawords that have a relatively low susceptibility to transmission errors.

Abstract: A method processes a data packet in a first sequence of disjoint original segments of the same length. The method includes modifying a first of the original segments of the first sequence by modifying one or more symbols therein. A start of the data packet is located in the first of the original segments and is positioned after a first digital data symbol therein. The method also includes modifying a last of the original segments of the first sequence by modifying one or more digital data symbols therein. An end of the data packet is located in the last of the original segments and is located before the last digital data symbol therein. The method also includes determining a remainder sequence by effectively performing a polynomial division on a second sequence of disjoint segments that are derived from the first sequence. Each segment of the second sequence corresponds to and is derived from one of the original segments of the first sequence.

Abstract: A method of protecting digital words traversing multiple data paths is presented. The method identifies a number of bits for a header of a digital word and determines a number of protection bits for the header. A bit value for each of the protection bits is computed, and the computed bit values of the protection bits are transmitted through one or more data paths.

Abstract: A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.

Abstract: A method for detecting codewords of a length-N, qary-symbol code, the symbols of each codeword stored in respective q-level cells of solid-state memory, where q>2, includes reading from memory cells storing a group of codewords to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword. The signal components of the read signals are ordered according to signal level to produce an ordered component sequence. The ordered component sequence is partitioned to obtain segments corresponding to respective memory cell levels. Each segment contains a number of components dependent on predetermined frequency data indicative of expected frequency of occurrence of the corresponding level in use of the code. A reference signal level corresponding to each q memory cell level is determined in dependence on the signal components. The codeword corresponding to each read signal is then detected in dependence on the reference signal levels.

Abstract: In accordance with various embodiments, a memory device and method of error detection and correction are disclosed. A memory device may include an input for receiving a command packet including an error detection code to facilitate command error detection. The memory device may include an error manager configured to detect, based on the error detection code, whether an error occurred in transmission of the command packet, a command register configured to store the command packet and configured to provide the command packet to the error manager, and an output to transmit the command packet to a subsequent device of the point-to-point ring topology.

Abstract: A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.

Abstract: Methods, systems, and computer readable media for a multi-packet CRC engine are disclosed. According to one aspect, the subject matter described herein includes a system for a multi-packet CRC engine. The system includes an input module for receiving set of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits, multiple CRC pre-calculation blocks (CPBs) that receive from the input module subsets of the set of bits, each subset containing a portion of a packet less than all of a packet, and calculate a CRC value for its respective subset of bits, and an output module for receiving the calculated CRC values from the CPBs and using the calculated CRC values to produce packet-specific CRC values, where the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values.

Abstract: A data receiving apparatus includes: a header analyzing unit that analyzes a header of a frame and outputs header information; a checksum judging unit that calculates and judges a checksum of the frame; a buffer unit that stores a data portion of the frame; a reading unit that reads connection information corresponding to the header information from a second storage unit; an identifying unit that identifies a write location for the data portion based on the connection information; a data writing unit that reads data from the buffer unit and starts writing the data to the identified write location in a first storage unit before the checksum is judged; and a writing unit that, if the judgment result is “pass,” writes the connection information updated based on the header information to the second storage unit while the data writing unit is writing.

Abstract: A semiconductor device includes an error detection unit suitable for receiving data and a cyclic redundancy check (CRC) code, and for outputting a detection signal by detecting a transmission error of the data, and a signal change unit suitable for generating error information based on the detection signal while changing a signal form of the error information based on a signal transmission environment of the data.

Abstract: A technique for injecting errors into a codeword includes generating a codeword that includes data bits and one or more checkbits. One or more bit errors are injected into the codeword by modifying at least one of the one or more checkbits.

Abstract: A method for detecting errors in a transfer of data from a transmitter to at least one receiver includes coding the data together with address information identifying the receiver in a series of data packets and transferring the data and the address information using the data packets. The method also includes generating, at the transmitter, a check value for each data packet and transferring the check value with/in the data packet to the receiver. The method further includes comparing, at the receiver, the check value with an expectation value, wherein an error is detected in the event of a deviation. For each data packet to be transmitted, the method includes calculating a number sequence value from the address information using a first calculation rule, generating the check value from the sequence value using a second calculation rule and transmitting the data packet with the check value to the receiver.

Abstract: A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-DRAM addressability (PDA) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (CRC) driving unit suitable for performing a CRC operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.

Abstract: A block CRC based fast data hash provides efficient data integrity verification functions. A hash word is generated from block CRCs that are stored along with data blocks in a hard drive for each data and/or parity track of a storage system, such as a RAID array. Each storage system member writes the hash word into a global memory. Thereafter, a director verifies data integrity using all member's hash words with one or more XOR operations. Use of the hash words for data integrity verification saves system bandwidth and CPU processing resources.

Abstract: Methods and devices generate cyclic redundancy check (CRC) values for a sequence of parallel words of data. The data words may have only some of the bits enabled. The input words are preconditioned, and then a common block generates a CRC remainder value. A specific preconditioning is selected based on the number of enabled bits. Additional post-processing may be performed to the CRC remainder.

Abstract: A semiconductor system including a semiconductor circuit configured to compare a first error detection code generated by performing an operation on read data to a second error detection code and determine a data transmission error, and a controller configured to provide the second error detection code, generated by performing an operation on expect data based on the read data, to the semiconductor circuit.

Abstract: A method of merging data frames includes: receiving a first data frame having a plurality of sectors; receiving a second data frame having a plurality of sectors; generating a merged output data frame by merging, using a plurality of data paths including a plurality of multiplexers, sectors of the second data frame with sectors of the first data frame; and performing an error check on at least one check-data frame having sectors corresponding to those in the first data frame or the second data frame, where at least some of the sectors in the check-data frame are transmitted on a subset of the plurality of data paths that transmits sectors of the merged output data frame, and where the error check verifies the merged output data frame.

Abstract: A method for processing a digital signal includes: receiving a plurality of protocol data units, each having a header including a plurality of control word bits; and a plurality of audio frames, each including a cyclic redundancy check code; decoding the protocol data units using an iterative decoding technique, wherein the iterative decoding technique uses a soft output decoding algorithm for iterations after the first iteration; and using decoded cyclic redundancy check codes to flag the audio frames containing errors. A receiver that implements the method is also provided.

Abstract: A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.

Abstract: A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice.

Abstract: Data processing methods and apparatus for processing stored data with error correcting bits to detect and in some instances correct errors. The data processing including, e.g., techniques such as the detection of errors by comparing hash values of data retrieved from storage with hash values of the data generated during storage. For example, one embodiment of a method in accordance with the present invention includes reading data stored with error correcting bits from a storage device, performing a hash operation on the data read from the storage device to generate a first hash value, comparing said first hash value to a previously generated hash value corresponding to said data, and determining that a read error has occurred when said first hash value does not match said previously generated hash value. In some embodiments, the method further includes performing an error recovery operation upon detection of an error.

Abstract: In a method for forming a CRC value using a plurality of data blocks, the CRC protection can be improved even further by virtue of the fact that, in order to form the CRC value, data blocks which are not transmitted to a receiver or have not been transmitted to a receiver are placed in front of data blocks which are transmitted to the receiver or have been transmitted to the receiver.

Abstract: An asynchronous master-slave serial communication system, a data transmission method, and a control module using the same are disclosed. The asynchronous master-slave serial communication system comprises a master control module and a slave control module. The master control module generates a check code according to an address information and a data information, and generates a data package according to the address information, the data information, the check code and the master clock signal. The slave control module generates a decoding data according to the data package and a slave clock signal, and generates the address information, the data information and the check code according to the decoding data.

Abstract: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.

Abstract: In a data processing system, a memory subsystem detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory. In response to detecting at least one such potentially transient condition, the memory system identifies a first read request affected by the at least one potentially transient condition. In response to identifying the read request, the memory subsystem signals to a request source to issue a second read request for the same target address by transmitting to the request source dummy data and a data error indicator.

Abstract: Data transferring systems are provided. The data transferring system includes a transmitter and a receiver. The transmitter transmit a reference code signal including a reference value of data, a transmission data signal generated by synthesizing data being transmitted and the reference code signal, and an external data masking signal. The receiver receives the transmission data signal to extract an internal code signal and generates an internal data masking signal in response to the internal code signal and the reference code signal. Further, the receiver generates an internal data signal from the transmission data signal in response to the external data masking signal and the internal data masking signal. Related methods are also provided.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: The invention relates to a method for protecting a sensitive operation by checking the integrity of at least a subset of the data manipulated by the sensitive operation. Data to be checked are divided into blocks, an intermediate integrity check value being computed for each block, the intermediate integrity check values being computed in random order. The invention also relates to a cryptographic device wherein at least one sensitive operation of the cryptographic device is protected by a method according to the invention.

Abstract: The invention discloses a method and an apparatus for data check processing, the method comprises: acquiring data to be checked; acquiring a first polynomial matrix F according to a generator polynomial; acquiring a second generator polynomial matrix Fi according to Fi=Fi, wherein i is the digit of the data; generating a CRC code of the data from the second generator polynomial matrix Fi, initial CRC register value X(0) and the data; and sending the data and the CRC code to a receiver for being checked by the receiver.

Abstract: Errors that can be detected as a result of the mapping of transmission data from its physical form back to its logical form can be considered in addition to the errors detected by using an error detection technique (e.g., a conventional CRC technique), thereby allowing fewer error detection/recovery bits (error recovery data or bits) to be used as would be possible by using the error detection technique alone. In other words, less error recovery data would be needed to achieve a given level accuracy using conventional techniques. As a result, overhead associated with adding error detection/recovery bits can be reduced.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract: A data storage device includes a memory and a controller. The controller is configured to receive a read request that indicates a logical address. The controller is further configured to perform a first read operation to retrieve a representation of an entry of a logical mapping table from the memory, and perform a second read operation to retrieve a representation of a codeword from the memory. The controller is further configured to decode the representation of the codeword to determine whether an error exists at the entry, and, prior to completion of decoding, to initiate a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry.

Abstract: The present disclosure describes methods and apparatuses for improved transport block decoding in devices capable of wireless communication, which may include user equipment and network entities. For example, the present disclosure presents methods and apparatuses for decoding a code block from a plurality of code blocks corresponding to a transport block, obtaining a reliability indicator that identifies a reliability of the decoding of the code block, comparing the reliability indicator to a reliability threshold, and determining whether to decode a subsequent code block from the plurality of code blocks based on the comparing. Furthermore, these methods and apparatuses may include determining not to decode at least one subsequent code block of the transport block where the comparing indicates that the reliability indicator is less than the reliability threshold. As such, device power is not unnecessarily consumed by decoding likely superfluous code blocks.

Abstract: Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: A method for decoding linear network codes that includes receiving a plurality of packets from an ererror detector and generating a matrix out of the plurality of packets where elements of each column of the matrix correspond to symbols of the plurality of packets. Then decoding across each row of the matrix using only the symbols with highest associated reliability values to obtain a decoded matrix, where each column of the decoded matrix corresponds to a message packet.

Abstract: A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.

Abstract: Devices implement encapsulation to support link layer preemption. The device may include a encapsulation logic that encapsulates data, such as an Ethernet frame, to produce an encapsulated frame. The encapsulated frame may include an encapsulation element that indicates whether the encapsulated data includes non-preemptible data, such as Distinguished Minimum Latency Traffic (DMLT), or preemptible data. The encapsulated frame may also indicate whether the encapsulated data comprises the last fragment of a preemptible frame.

Abstract: A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function.

Abstract: In particular embodiments, a method includes receiving from a remote system a binary decision diagram (BDD) representing data streams from sensors, an input, and a first hash code, transforming the received BDD to a second arithmetic function by performing the arithmetic transformation on the received BDD, calculating a second hash code from the second arithmetic function and the input, and if the first hash code equals the second hash code, then indicating that the received BDD is uncorrupted data, else indicating that the received BDD is corrupted data.

Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to techniques for accurately determining a number of data symbols in a data packet. The techniques provided herein may allow a receiving terminal to correct number of symbol calculations based on such ambiguous length field values.

Abstract: Disclosed are methods and apparatus for improved backwards compatible DMX communications. In some embodiments,methods and apparatus related to extensions of the DMX protocol enable error detection by enhanced DMX slave devices while maintaining full compatibility with non-enhanced DMX slave devices. The methods and apparatus may utilize a packet checksum byte that is incorporated within a start code packet and that is a checksum of a plurality of bytes in the start code packet. A plurality of bytes within the start code packet may optionally be interleaved according to an interleaving scheme in some variations.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: A wireless apparatus and a method thereof are provided. The wireless apparatus comprises a receiving unit and a processing unit. The receiving unit is configured for receiving a packet which comprises a data portion and a cyclic redundancy check portion from the base station. The processing unit connected to the receiving unit which is configured for generating a de-masked packet by de-masking the cyclic redundancy check portion and at least one selected bit of the data portion by a plurality of predetermined bits, determining that the de-masked packet pass a cyclic redundancy check, and accepting the packet after the determination.

Abstract: A method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. In one embodiment of the invention, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction.

Abstract: A method for processing data packets of a data stream, in which the received data packets are processed in real-time by a first unit and only data packets that are received error-free are processed by a second unit, include a data sink initially receiving only the data packets processed by a first unit. Once a second unit and the first unit are processing identical data packets nearly simultaneously, data packets processed by the second unit can be routed to the data sink. Embodiments of the invention can be used advantageously in video coding, for example with a video-on-demand service or image analysis within the framework of a surveillance system.