Abstract: Embodiments of the present disclosure provide a method and device for storage management. The method comprises: receiving from a host a storage creating request which specifies a target capacity expected by the host creating for the host a first group of logical units having the target capacity; associating the first croup of logical units with physical storage for use by the host; and creating for the host a second group of logical units having a first additional capacity, the second group of logical units being unassociated with the physical storage.

Abstract: Disclosed are system and method for verification of data transferred among several data storages. An exemplary method includes: calculating first hash-sums of the data during an initial placement in a data storage; transmitting the first hash-sums to at least one blockchain network; detecting a transfer of the data to a new data storage; calculating second hash-sums of the data after a placement of the data in the new data storage; transmitting the second hash-sums to the at least one blockchain network; comparing the first and second hash-sums of the data; and determining data immutability after the transfer of the data from the data storage to the new data storage based at least on results of the comparing.

Abstract: Erasure code for data is generated by: calculating the size and bytes of an erasure code block, calculating a number of stripes for the erasure code, and generating each stripe of each block for the erasure code, such that the stripes alternate in a pattern for each block, and saving hashes. A portion of the data is repaired by: for each block of the portion of the data, calculating the stripe of the block, identifying each hash for which the hash of the block of the portion of data does not match the saved hash of the block as a bad block, and for each identified bad block, generating a repair block for the bad block based on the stripe of the block and corresponding block of the data in the erasure coding for the data.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: Systems and methods for communication between a vehicle system and a secure communication bus are disclosed. Systems can include a microcontroller and a transceiver configured to send transmit data to the communication bus, receive data from the communication bus, and send data received from the communication bus to the microcontroller. The microcontroller may be prevented from transmitting data to the transceiver by hardware separation between an output of the microcontroller and the transmit data input of the transceiver. The communication bus may be a CAN bus.

Abstract: A computer-implemented method for using invertible, shortened codewords is described. The method includes receiving a request to store user data bits in a set of memory devices; expanding the user data bits and an inversion bit to bit locations of a codeword template, wherein the expanding forms expanded inversion and user data bits that collectively include additional bits to represent the user data bits and the inversion bit; generating parity bits for the expanded inversion and user data bits to form a shortened codeword, wherein the shortened codeword comprises the expanded inversion and user data bits, and the parity bits; compressing the shortened codeword to form a compressed shortened codeword; and storing the compressed shortened codeword in the set of memory devices.

Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.

Abstract: A terminal device is provided such that in a case that closed-loop UE transmit antenna selection is configured, a bit sequence is given by scrambling CRC parity bits with an RNTI and an antenna selection mask, in a case that the number of the CRC parity bits is a first value, a first transmit antenna port is given by a first antenna selection mask, and in a case that the number of the CRC parity bits is a second value, the first transmit antenna port is given by a second antenna selection mask that is different from the first antenna selection mask.

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: A data processing method and apparatus, a server, and a controller, where the method includes receiving, by a server, a data processing request, where the data processing request includes a request sequence number, and the request sequence number marks the data processing request, generating at least one input/output (I/O) request according to the data processing request, adding the request sequence number to each of the at least one I/O request, merging the I/O requests having the request sequence number, and generating an aggregation instruction when a quantity of I/O requests having the request sequence number is greater than a preset threshold, and sending the aggregation instruction to a controller of a storage system. Hence, a time taken to perform monitoring and management using a transaction mechanism can be reduced, thereby simplifying the transaction mechanism.

Abstract: In an information processing apparatus 200, a communication portion 250 acquires a data stream of a photographed image in a wireless communication manner. A packet analyzing portion 252 detects a lost packet, and a retransmission request producing portion 254 issues a retransmission request for a packet within a predetermined allowable time. Along with expiration of the allowable time, a lacked information producing portion 258 produces lacked information in which data lacked due to the packet loss is associated with a position on an image plane. A decoding portion 260 decodes the data associated with the photographed image and stored in the buffer 256, and substitutes invalid data for the lacked portion. An image analyzing portion 262 differentiates the lacked portion from other portions, and performs analysis processing. An information processing portion 264 and an output data producing portion 266 execute information processing by utilizing the analysis result, and produce output data, respectively.

Abstract: A method, performed by a base station, of transmitting and receiving data in a wireless communication system, and an apparatus therefor are provided. The method includes determining whether a code block (CB), one of a plurality of CBs included in a transport block (TB), is scheduled for a transmission based on code block group transmission information (CBGTI), in response to the CB being scheduled for the transmission, determining a length of a sequence for the CB based on a number of CBs of the TB or a number of scheduled CBs of the TB, generating the sequence for the CB according to the determined length of the sequence, and transmitting a signal including the generated sequence.

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

Abstract: Efficient deduplication for storage systems is disclosed, including: using the current data structure to track a set of deduplication data entries associated with a collection group; determining a flush criterion has been met; and storing the set of deduplication data entries of the current data structure as one or more persistent objects associated with the collection group in a persistent storage, wherein the one or more persistent objects are usable to update a set of persistently stored metadata associated with the collection group that tracks deduplication data entries generated before a previous merge operation.

Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

Abstract: With CRC-code-computation logic used in electronic-communications hardware, many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. A component-efficient CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.

Abstract: According to some embodiments, a method for use in a wireless receiver comprises determining a transport block size, TBS, for a transport block to be communicated between the wireless transmitter and a wireless receiver via a physical channel transmission. The TBS determination uses a formula accounting for cyclic redundancy check, CRC, bits. The method further comprises transmitting the transport block according to the determined TBS. In particular embodiments the formula is based on an approximate transport block size, a number of code blocks, at least one of a number of CRC bits attached to the transport block, and a number of CRC bits added to each of the C code blocks.

Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.

Abstract: A system for locating a ground fault in an HRG power distribution system includes an HRG pulsing system having a ground fault sensor to detect a ground fault, a pulsing contactor to introduce a pulsing current into the power distribution system, and a controller to control the pulsing contactor to introduce the pulsing current into the power distribution system in response to a ground fault detection by the ground fault sensor. Current sensors in the power distribution system monitor three-phase current signals on conductors of the power distribution system, with the current sensors positioned on distribution networks in the power distribution system and at a protection device included on each respective distribution network. A processor associated with each protection device and operably connected to the current sensors thereat receives signals from the current sensors for identifying a location of a ground fault in the power distribution system.

Abstract: Apparatuses, methods, and computer-readable media for a context-based access mediator (“CAM”) are described. The CAM may be configured to mediate access to computer-accessible resources by a user using a computing device after receiving a request from the computing device for the computing device to access a computer-accessible resource. The computer-accessible resource may be local or remote to the computing device. The CAM may be configured to receive the request and to mediate access to the requested resource. Such mediation may be performed through the CAM determining whether the resource may be accessed by the computing device and/or through the CAM determining which resources are available to the be accessed by the computing device. The CAM may be configured to mediate access to computer-accessible resources based on information about a context for the computing device and/or computer-accessible resource. Other embodiments are described and claimed.

Abstract: Disclosed are systems, methods, and articles for determining compatibility of a mobile application and operating system on a mobile device. In some aspects, a method includes receiving one or more data values from a mobile device having a mobile medical software application installed thereon, the data value(s) characterizing a version of the software application, a version of an operating system installed on the mobile device, and one or more attributes of the mobile device; determining whether the mobile medical software application is compatible with the operating system by at least comparing the received data value(s) to one or more test values in a configuration file; and sending a message to the mobile device based on the determining, the message causing the software application to operate in one or more of a normal mode, a safe mode, and a non-operational mode.

Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.

Abstract: Provided are a method and device for transmitting control information in a wireless communication system. In particular, a base station transmits, to a terminal, an RNTI mapped to a downlink terminal group or an uplink terminal group including a terminal, and a terminal ID instructing the terminal in the downlink terminal group or the uplink terminal group. The RNTI and the terminal ID are used to set control information, and the control information includes an identification information field instructing whether scheduling information on the terminal exists, a scheduling information field for the terminals in each terminal group, and a first CRC field. The first CRC field is encoded for the scheduling information field for the terminals in each terminal group. The set control information is transmitted to the terminal.

Abstract: Provided are method, apparatus, and computer-readable medium for packet slicing, comprising: performing start of packet (SOP) detection on data packet to obtain first detection result; when first detection result indicates that data packet satisfies condition for inserting first burst control word, inserting first burst control word and filling data control words, each corresponding to interface bit width, in unit of interface bit width; performing intermediate detection on data packet to obtain second detection result; when second detection result indicates that data packet satisfies condition for inserting second burst control word, inserting second burst control word, and filling one or more data control words, each corresponding to interface bit width, in unit of interface bit width; performing packet tail mark detection on data packet to obtain third detection result; and inserting, when third detection result indicates that data packet has packet tail mark, fixed number of idle control words.

Abstract: Embodiments include radio transmitters, receivers and methods of operation for enhanced bandwidth utilization. The transmitter hashes received data blocks to produce indices associated with the received data blocks. The data blocks and associated indices are stored in memory and transmitted. If the received data blocks have previously been stored, the indices are transmitted instead of the data blocks. The receiver stores the received data blocks and associated indices in memory, and outputs the received data blocks. When the receiver receives indices instead of data blocks, it accesses the memory to look up and retrieve the associated data blocks, and outputs the retrieved data blocks.

Abstract: A base station device can adaptively assemble the downlink control information using a plurality of information segments and then transmit the assembled downlink control information to a mobile device. The information segments can each represent different control functions and the base station device can select relevant and appropriate information segments to include in the downlink control information based on the features represented in the downlink data transmission and the mobile device. If the downlink data transmission does not have a certain feature, the base station device can leave the information segment relevant to the feature out of the downlink control information. Additionally, when new features are introduced, new information segments can be added without defining a new downlink control information format.

Abstract: Certain aspects of the present disclosure provide for signaling to expanded capability UEs that may limit the interruption of legacy UEs. According to certain aspects, a base station (e.g., an eNB) may generate and transmit one or more signals containing information that is recognizable by at least one expanded capability UE and identified as invalid by at least one legacy UE. An expanded capability UE may receive such signaling and identifying supplemental information in the signaling, while a legacy UE may regard the signaling as invalid.

Abstract: A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method including reading data from an array of memory chips, calculating at least one hash based on the data, checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash, determining whether an error is detected, when an error is detected, correcting the data by changing each bit of the array of the memory chips one at a time until no error is detected, wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected, and outputting the corrected data when no error is detected.

Abstract: An example system for side band communication can include a processor, a system-on-chip (SOC), and a repeater communicatively coupled to the processor and the SOC. The repeater can receive packets from a first transceiver. The repeater can also detect a pattern in the packets to identify a guest protocol. The repeater can further send the packets from the first transceiver to the SOC via a second transceiver based on the identified guest protocol.

Abstract: A receiver includes a polar decoder for decoding an encoded codeword transmitted over a communication channel. The receiver includes a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel and a soft decoder operated by a processor to produce a soft output of the decoding. The codeword is encoded by at least one polar encoder with a polar code. The processor is configured to estimate possible values of the bits of the received codeword using a successive cancelation list (SCL) decoding to produce a set of candidate codewords, determine a distance between each candidate codeword and a soft input to the soft decoder, and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. The controller derives a ratio value according to the write workload of the non-volatile memory between a first time point and a second time point and then performs a patrol read on a portion of the closed blocks according to the ratio value.

Abstract: A method for recording parity data of data stripes within shingled media recording bands in a redundant array of independent disks can be accomplished using a plurality of shingled media recording (SMR) hard disk drives (HDD) each with a plurality of shingled data bands. A data stream received from a host computer system is sequentially stored to a plurality of block segments in successive order, one stripe at a time successively. Each of the shingled data bands possess n data blocks (or multiple data blocks that are grouped together as a data unit) that are successively ordered, each corresponding successive data block from all of the SMR HDDs defines a data stripe, accordingly n data blocks in each SMR HDD defines n stripes across the shingled data bands. A transaction group sync triggers a halt to writing the data stream. The rest of the data stripe is written with fill bits.

Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.

Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.

Abstract: In one embodiment, memory circuitry includes an error-correction code (ECC) encoder, memory, and an ECC decoder. The ECC encoder performs encoding, based on an ECC algorithm having an algorithm size, on an algorithm-size segment of input user data to generate a corresponding subset of parity data for the segment of input user data. The memory has input user data and corresponding parity data written based on a write data size and stored user data and corresponding stored parity data read based on a read data size. The ECC decoder performs decoding, based on the ECC algorithm, on an algorithm-size segment of retrieved user data and a corresponding subset of retrieved parity data, wherein the algorithm size is smaller than the write data size or the read data size. The memory circuitry enables conventional SEC-DED algorithms to be used when the write and read data sizes are different.

Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.

Abstract: A system performs tunneling of real-time communications (“RTC”). The system establishes a tunnel between a tunneling client and a tunneling server. The system then receives a packet over the tunnel. The packet is configured according to an outer transport protocol of the tunnel and includes a datagram-based payload and a stream-based header. The system processes the packet according to a datagram-based outer transport protocol based on information in the stream-based header.

Abstract: This disclosure describes methods, apparatus, and systems related to a high efficiency signal field coding system. A device may determine a high efficiency preamble in accordance with a high efficiency communication standard to be sent to one or more devices, the high efficiency preamble including at least in part a high efficiency signal field. The device may determine a common part included in the high efficiency signal field. The device may determine one or more device specific parts associated with the one or more devices. The device may encode the high efficiency signal field based at least in part on a predetermination combination of at least one of the common part or the one or more device specific parts. The device may cause to send the high efficiency preamble to the one or more devices, including the encoded high efficiency signal field.

Abstract: Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.

Abstract: A wireless network interface device selects a guard interval from a set of guard intervals including a first guard interval, a second guard interval, and a third guard interval, where in the first guard interval has a length that is 50% of a length of the second guard interval, and wherein the length of the second guard interval is 50% of a length of the third guard interval. The wireless network interface device generates a preamble of a data unit to include: a legacy signal field, a repetition of the legacy field, and a non-legacy field that includes a field that indicates the selected guard interval. The wireless network interface device generates a data portion of the data unit, including generating orthogonal frequency division multiplexing (OFDM) symbols of the data portion using the selected guard interval.

Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.

Abstract: A system and method for polling a plurality of client devices of different types are provided. A reboot and polling tool pre-polls client devices, where the pre-poll is specific to a type of client device and identifies a state of the client devices. The reboot and polling tool then executes a script on the client devices that changes the state of the plurality of client devices. After the script is executed, the reboot and polling tool post-polls the client devices where the post-poll is specific to the type of client device and the post-poll provides information that identifies changes in the state of the client devices caused by the script.

Abstract: There is provided a mechanism for conducting a communication between at least one communication network control element such as an eNB and at least one communication element such as a UE wherein a DM RS based communication mode is used. DMRS (scrambling) sequences are generated wherein each DMRS sequence includes a set of calculation parameters being specific for the respective DMRS sequence, wherein the set of calculation parameters is configurable by the eNB during communication. For initializing each of the at least one scrambling sequence before receiving the configuration information, i.e. in an initial phase of the communication, a predetermined default value based on e.g. an UE_ID and being selectable from a set of predetermined default values is used for the set of calculation parameters in each DMRS sequence.

Abstract: A method and computer device for storage and retrieval of a data object on a storage medium. The method includes steps of disassembling the data object into a predetermined number of redundant sub blocks, storing the redundant sub blocks on the storage medium, retrieving at least a predetermined multiple of a minimal spreading requirement of the redundant sub blocks from the storage medium, and assembling the data object from any combination of a particular number of the redundant sub blocks, the particular number corresponding to a predetermined multiple of a minimal spreading requirement. The computer device includes modules for performing the steps.

Abstract: A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

Abstract: One of the embodiments of the present invention relates to a method for modulation. The method comprises: providing a first bit sequence of continuous bits “1” or continuous bits “0” generating a second bit sequence by replacing, in each of a plurality of modulation intervals with a predetermined bit number, at least one bit of the first bit sequence at least one fixed position of the respective modulation interval with one information bit from an information bit sequence; and modulating the second bit sequence so as to generate a positioning packet with a modulated continuous wave signal for transmission. The embodiments further relate to a method for demodulation. Embodiments of the present invention also provide corresponding apparatuses and computer program products.

Abstract: A system and method for improving deduplication techniques in a data storage system. In one embodiment, a data storage system is configured to divide first data into a first plurality of segments, to generate a first plurality of fingerprints that are each to be associated with a segment, to identify second data that is to be updated by the first data and a second plurality of fingerprints associated with the second data, to load the second data and the second plurality of fingerprints from persistent storage of the data storage system into working memory, to determine, in the working memory, that a first segment of the first plurality of segments updates the second data by comparing a first fingerprint associated with the first segment to the second plurality of fingerprints, and to overwrite a second segment of the second data with the first segment in response to the determination.

Abstract: A distributed interlocking device, architecture and process are disclosed, and are based on segregating the vital logic for a signal installation by type of signal equipment. A plurality of intelligent signal devices is disclosed, wherein each intelligent signal device is used to control a basic signal unit. In turn, a signal unit includes a set of signal apparatuses that are geographically and logically interrelated. An intelligent signal device receives data related to the states of other signal devices, determines and controls its own operational states, and communicates its own operational states to other devices. A generic intelligent signal device is also disclosed, and is based on a parameterization approach that incorporates a plurality of vital parameters into the vital logic of the device. The device is then customized to a site specific location by activating the appropriate parameters for that location.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include receiving a request to create a storage entity on a storage system, the storage entity including data and metadata, the metadata used to manage the storage entity. Upon receiving the request, multiple metadata attributes are identified for the metadata, and for each given identified metadata attribute, a respective metadata region is created on the storage system, and a subset of the metadata having the given metadata attribute is stored to the respective metadata region. Finally, a data region is created on the storage system, and the data is stored to the data region.

Abstract: A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and reweights the contribution of all symbols in the message, while the N reweighting modules in the N parallel feed-forward paths provide the contributions of the symbols that are “in-flight” within the feedback loop to the final CRC checksum.