Abstract: A method and apparatus for generating a Cyclic Redundancy Check (CRC) encoded message in a communication system are provided. The method includes generating the message, generating a first CRC for the message, generating a second CRC for the message, scrambling the first CRC by a first bit sequence of the message, and scrambling the second CRC by a second bit sequence of the message. The apparatus includes a message generator, a first CRC encoder, and a second CRC encoder. The message generator generates a message. The first CRC encoder generates a first CRC for the message, and scrambles the first CRC by a first bit sequence of the message. The second CRC encoder generates a second CRC for the message, and scrambles the second CRC by a second bit sequence of the message.

Abstract: In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.

Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.

Abstract: Aspects of the present disclosure provide methods, apparatus and computer program products for turbo decoder throttling (e.g., in an effort to limit power consumption by a user equipment (UE)). According to an aspect, the UE may identify an error in a received code block (CB) of a transport block (TB). The UE may enter a throttle mode in a decoder at the UE in response to the identified error, wherein the throttle mode determines how one or more subsequent CBs are processed. Numerous other aspects are provided.

Abstract: A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data.

Abstract: A communication device includes a division circuit configured to divide a data block received from a network into a plurality of cells, a plurality of processing circuits, each configured to execute predetermined processing with respect to the plurality of cells received from the division circuit, an assembling circuit configured to assemble the data block from the plurality of cells received from the plurality of processing circuits, and a first control circuit configured to determine whether or not mismatch is present in a plurality of calculation results stored in the cell, wherein at least two of the division circuit, the plurality of processing circuits, and the assembling circuit store the calculation result of error check calculation with respect to at least one of the plurality of cells, in the cell.

Abstract: Various embodiments of the present inventions are related to initialization of decoder-based filter calibration, and in particular to initially using either a detector output or unconverged data from the decoder to train filter coefficients in a noise predictive calibration engine until data sectors converge in the decoder and can be used to train filter coefficients.

Abstract: The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.

Abstract: In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

Abstract: An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.

Abstract: An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.

Abstract: A device may include a compressor. The compressor may receive a first number of inputs, each of the inputs having a predetermined width. The compressor may also compute a one's complement sum of the first number of inputs to generate carry bits having the predetermined width and sum bits having the predetermined width, modify the carry bits by moving a most significant bit of the carry bits to a least significant bit position, and output the modified carry bits and the sum bits.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract: An embodiment of the invention provides a telecommunications method performed by a second telecommunications device. According to the embodiment, the second telecommunications device first tries to use a received part of a data block to decode the data block, wherein the received part is received from a first telecommunications device. Next, the second telecommunications device determines whether a code metric derived based on the received part indicates that the data block is decodable. If the code metric indicates that the data block is decodable, the second telecommunications device further determines whether a set of confirmation criteria is satisfied.

Abstract: Generating data checksum for a data object including multiple data units comprises, for each data unit, obtaining a corresponding address of the data unit, and rotating the data unit based on said corresponding address of the data unit to generate a rotated data unit. A checksum value for the data object is determined based on said rotated data units.

Abstract: A method and an apparatus for indicating a temporary block flow (TBF) to which a piggybacked acknowledgement/non-acknowledgement (PAN) field is addressed. A method and apparatus of performing receive processing to reduce the probability of false acceptance of erroneous PANs are also disclosed. A transmit station generates a PAN check sequence (PCS) and performs a channel coding on a PAN field and the PCS. The transmit station scrambles the encoded bits of the PAN field and the PCS with a TBF-specific scrambling code. Because of the scrambling, the PCS decoding at a receive station will pass if the data block is received by an intended receive station, while the PCS decoding will fail if received by a non-intended receive station. Alternatively, the scrambling may be performed before the channel coding. Alternatively, the transmit station may combine the PAN field and a temporary flow identity (TFI) to generate a PCS.

Abstract: The disclosure is related to systems and methods for checking the integrity of a data transfer to or from a buffer or other data storage medium. Check values can be added to a data object in a data object based file system. From the check values, a device receiving the data object may determine an integrity or validity of the received data object based on the check values. In a particular embodiment, a hash value may be determined based on the check values. The hash value may be stored in the metadata of the transferred data object. The receiving device may re-calculate the hash value from the check values and compare it to the stored hash value to determine an integrity of the received data object.

Abstract: The present disclosure includes methods, devices and systems for establishing a connection between a medical device and a remote computing device, receiving an upgrade command at the medical device, storing a current version of persistent data and a current version of executable code in a first storage area of the medical device, transmitting at least the current version of the persistent data to the remote computing device, receiving a second format of the current version of the persistent data and an upgraded version of executable code at the medical device, storing the second format of the current version of the persistent data and the upgraded version of the executable code in a second storage area of the medical device, and executing the upgraded version of the executable code with the second format of the current version of the persistent data.

Abstract: The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a predetermined number of consecutive iterations. In another example embodiment, a decoding iteration is performed on a particular sub-block of multiple sub-blocks of a transport block, which includes a single CRC over an entirety of the transport block. The CRC is checked using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained from previous decoding iterations on other sub-blocks of the multiple sub-blocks. The decoding iteration is then performed on a different sub-block if the CRC does not check. Also, the decoding iterations for the sub-blocks may be terminated if the CRC checks.

Abstract: Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.

Abstract: A display control apparatus includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check in the arbitrary region, which facilitates the cyclic redundancy check.

Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.

Abstract: A data recording apparatus includes a storage unit, a control unit, and a card interface unit. The storage unit stores master data being original data of data to be recorded on a card-type medium. The control unit reads out the master data from the storage unit and executes a recording processing control of the read-out master data with respect to the card-type medium. The card interface unit installs the card-type medium therein and executes data recording processing. Further, the control unit executes, in parallel to recording processing of the master data with respect to the card-type medium, error verification processing of the master data to which the verification value stored in the storage unit is applied, and performs a control of stopping the recording processing of the master data with respect to the card-type medium when an error is detected.

Abstract: Systems and methods for intelligently reducing the number of log-likelihood ratios (LLRs) stored in memory of a wireless communication device are described herein. In one aspect, the systems and methods described herein relate to selecting LLRs for storage based on a quality metric. In another aspect, the systems and methods described herein relate to improving communication quality in response to available memory capacity.

Abstract: A method and device for segmenting, CRC encoding and turbo encoding a CRC attached transport block.

Abstract: A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit.

Abstract: Message content associated with at least one message received by a message processing server is stored in association with the message processing server. The message content within an incoming message is compared with the stored message content. A determination is made as to whether the stored message content is duplicated by the message content associated with the incoming message. A duplicate message content management action is performed based upon the determination as to whether the stored message content is duplicated by the message content associated with the incoming message. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.

Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Abstract: An integrity unit can be calculated from a first data unit, and a first storage device can be requested to store the first data unit. A second storage device, which can be separate from and/or a different type of device from the first storage device, can be requested to store metadata, which includes the integrity unit, in nonvolatile memory. Also, a second data unit can be received from the first storage device in response to a request for the first data unit. The integrity unit can be received from the second storage device, and the second data unit and the integrity unit can be analyzed to determine whether the second data unit matches the first data unit. Alternatively, a first integrity unit can be stored in a metadata region of a nonvolatile memory block, where the block also stores the data from which the first integrity unit was calculated.

Abstract: A first check code is computed by applying an algorithm to a proper subset of a first body of data. A second check code is computed by applying the algorithm to an equivalent proper subset of a second equivalent body of data. The two check codes are compared. The extent of the proper subset of the first body of data is determined by a semantic analysis of the first body of data. Multiple versions of an application, when the semantic changes between the applications are inconsequential, may then be certified by ignoring the non-significant modifications and ensuring the integrity of the remainder of the content.

Abstract: A method begins by determining that a disk drive of a slice server has been replaced with a new disk drive. The method continues by identifying a data slice that was stored on the disk drive and identifying a data segment based on the identified data slice. The method continues by identifying other slice servers that are storing other data slices of the encoded data segment. The method continues by retrieving, from the other slice servers, a sufficient number of the other data slices to reconstruct the data segment and decoding the sufficient number of the other data slices to reconstruct the data segment. The method continues by encoding the reconstructed data segment in accordance with the information dispersal algorithm to produce a new set of data slices. The method continues by selecting a data slice of the new set of data slices as a rebuilt data slice.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: A receiver includes a decoder configured to decode at least a portion of a data stream comprising a data frame. The data frame includes a code block having a data block and a parity block. The receiver also includes a controller. The controller is configured to determine whether to disable at least a portion of the receiver during transmission of the parity block to the receiver when the data block contains at least one erasure.

Abstract: A method of channel coding for transmitting data in a wireless access system includes: calculating a number C of code blocks by an equation of C=?B/(Z?L)?, wherein B denotes a size of an input bit sequence, wherein Z denotes a maximum size of the code blocks, and wherein L denotes a size of a cyclic redundancy check (CRC) which is to be attached to each of the code blocks; calculating a size B? of a modified input bit sequence by an equation of B?=B+C*L; generating the code blocks based on the number C of the code blocks and the size B? of the modified input bit sequence; and channel-coding the code blocks.

Abstract: An apparatus includes, in at least one aspect, a plurality of buffers and circuitry configured to store encoded data in one buffer of the plurality of buffers concurrently with storing other data in another buffer of the plurality of buffers and to write the stored encoded data from the one buffer to a storage device concurrently with storing encoded other data in the other buffer, replacing the stored other data in the other buffer.

Abstract: A method for reading data from an electronic data memory. The data lie as data words in the memory, wherein each data word is available at a unique address. In addition, the data word is available as an identical copy at a second address having a fixed address offset (N) in the same data memory or the copy is available at an address of a different data memory that is linked through a unique assignment instruction to the address of the data word in the data memory. A checksum (CRC) for each data word is additionally stored in the data memory. For reading a data word, the data word and the checksum (CRC) are initially read. Then the checksum (CRC) is calculated via the data word and compared to the read checksum (CRC). If the checksums (CRC) do not correspond to one another, the read operation is repeated with the copy of the data word. If this value is also invalid, a default value is used and/or an error message is issued.

Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

Abstract: Embodiments of methods and systems are presented for generating PHY frames with multiple Reed-Solomon encoded blocks in PLC networks. In one embodiment, a MAC layer divides a data frame from a higher level into data blocks. The MAC layer may add a MAC header and/or an error-detection code to each data block. The MAC layer then passes the data blocks to a PHY layer to be individually Reed-Solomon encoded and combined into a single PHY frame for transmission on a PLC network. In other embodiments, the MAC layer passes a single data frame to the PHY layer, which divides the MAC data frame into segments to be individually Reed-Solomon encoded. The individual Reed-Solomon encoded segments are combined into a single PHY frame for transmission on a PLC network.

Abstract: A method for computing a X-bit cyclical redundancy check (CRC-X) frame value for a data frame transmitted over a N-bit databus is provided. The method includes receiving a N-bit data input with an end-of-frame for the data frame at bit position M on the N-bit databus, performing a bitwise XOR on X most significant bits of the N-bit data input with a CRC-X feedback value to form a first N-bit intermediate data. The method also includes shifting the first N-bit intermediate data by M bit positions to align the end-of-frame of the data frame with a least significant bit (LSB), and padding M number of zero bits to a most significant bit (MSB) of the first N-bit intermediate data to form a second N-bit intermediate data.

Abstract: Techniques for protecting information elements transmitted to mobile stations from intruders. The technique can involve applying a randomized mask over an information element and then providing a scrambled cyclic redundancy check (CRC) value. A seed for the randomized mask can be different from a seed for the scrambled CRC value.

Abstract: A method for decoding linear network codes that includes receiving a plurality of packets from an ererror detector and generating a matrix out of the plurality of packets where elements of each column of the matrix correspond to symbols of the plurality of packets. Then decoding across each row of the matrix using only the symbols with highest associated reliability values to obtain a decoded matrix, where each column of the decoded matrix corresponds to a message packet.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is operable to apply a first data decode algorithm to a decoder input to yield a decoded output. The second decoder circuit is operable to apply a second data decode algorithm to a subset of the decoded output to modify at least one element of the decoded output to yield a modified decoded output.

Abstract: A method for detecting codewords of a length-N, qary-symbol code, the symbols of each codeword stored in respective q-level cells of solid-state memory, where q>2, includes reading from memory cells storing a group of codewords to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword. The signal components of the read signals are ordered according to signal level to produce an ordered component sequence. The ordered component sequence is partitioned to obtain segments corresponding to respective memory cell levels. Each segment contains a number of components dependent on predetermined frequency data indicative of expected frequency of occurrence of the corresponding level in use of the code. A reference signal level corresponding to each q memory cell level is determined in dependence on the signal components. The codeword corresponding to each read signal is then detected in dependence on the reference signal levels.

Abstract: Embodiments of the invention relate to efficiently employing checksums for shared nothing clustered filesystems. Tools are provided to compute the checksum in response to a read transaction and to utilize the computed checksum to prevent serving corrupted data. Multiple levels of data replication are provided. The checksum computation functions within the multiple levels and addresses a specified data block that is the subject of the read transaction.

Abstract: Methods and apparatus for wireless communication in a wireless communication network include determining a transmit data packet size at a transmitting device and computing an early termination scheme associated with a receiving device. Aspects of the methods and apparatus include increasing a transmission length of a Cycle Redundancy Check (CRC) field associated with the transmit data packet before transmission of the transmit data packet, wherein the transmitted length of the CRC field is based on the early decoding scheme. Aspects also include transmitting the transmit data packet with the increased transmission length of the CRC field to the receiving device.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM rows, and wherein a subset of the columns in each RAM row are RAM columns and at least one column in each RAM row is a flag bit column, the memory cells corresponding to the flag bit column and RAM rows operable to store flag bit signals; a soft error detection (SED) circuit operable to read the configuration memory to derive a checksum; a logic circuit to determine if a RAM row is being read by the SED circuit that includes an asserted flag bit; and a blocking circuit that provides a known logical value to the SED circuit responsive to the logic circuit to block readback of the memory cells corresponding to the RAM rows and RAM columns.