Abstract: A disk drive receives a request to write at least one block of a first block size, wherein the disk drive is configured to store blocks of a second block size that is larger in size than the first block size. The disk drive stores a plurality of emulated blocks of the first block size in each block of the second block size. The disk drive generates a read error, in response to reading a selected block of the second block size in which the at least block of the first block size is to be written via an emulation. The disk drive performs a destructive write of selected emulated blocks of the first block size that caused the read error to be generated. The disk drive writes the at least one block of the first block size in the selected block of the second block size.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: detecting, by a resource allocation device, a failure of server hardware; identifying a first agent device that is configured to utilize the server hardware; and taking at least one action to effect a reconfiguration of the first agent device in response to the server hardware failure. Various embodiments additionally include one or more of the following: identifying a second agent device that is configured to utilize the server hardware; and taking at least one action to effect a reconfiguration of the second agent device in response to the server hardware failure. Various embodiments additionally include one or more of the following: receiving, by the resource allocation device from a second agent device, an indication of the failure of server hardware, wherein the second agent device is different from the first agent device.

Abstract: After power is restored to a node in a utility network, that node employs one or more of its neighboring nodes as proxies to route a message to a central control facility of the utility. The message contains information about the restored node, and possibly one or more of its neighbor nodes. This information may include reboot counters, the amount of time that the node was down, momentary outages or power fluctuations, and/or the time of power restoration. The node that creates and initially sends the message can be the restored node itself, or another node that recognizes when a restored node has recently come back online.

Abstract: A method begins by a dispersed storage (DS) processing module identifying a set of collections of records corresponding to a data segment that is stored in a dispersed storage network (DSN) as a set of encoded data slices, wherein a collection of records includes an event record including information regarding an event, a first record including information regarding a dispersed storage (DS) processing module processing an event request to produce a plurality of sub-event requests, and a plurality of records including information regarding a set of DS units processing the plurality of sub-event requests. The method continues with the DS processing module determining whether an error exists for one of the set of encoded data slices based on at least some of the set of collections of records and when the error exists, flagging the one of the set of encoded data slices for potential rebuilding.

Abstract: A control computer system comprising at least two modules (1, 2, 1001, 1002, 1003, 1004, 1021, 1071) which are designed to be redundant with respect to one another. The control computer system having at least one comparison unit (20, 21, 91, 92, 1011, 1012) for monitoring the synchronization state of the at least two redundant modules (1, 2, 1001, 1002, 1003, 1004, 1021, 1071) and for detecting a synchronization error at least one peripheral unit (95, 96, 1022, 1030, 1031, . . . , 1038). At least one switching matrix (21, 1013, 1063) which is set up to allow or block access to the at least two redundant modules or access to the peripheral unit (95, 96, 1022, 1030, 1031, . . .

Abstract: A method utilizes cluster-awareness to effectively support a live partition mobility (LPM) event and provide recovery from node failure within a Virtual Input/Output (I/O) Server (VIOS) cluster. An LPM utility creates a monitoring thread on a first VIOS on initiation of a corresponding LPM event. The monitoring thread tracks a status of an LPM and records status information in the mobility table of a database. The LPM utility creates other monitoring threads on other VIOSes running on the (same) source server. If the first VIOS VIOS sustains one of multiple failures, the LPM utility provides notification to other functioning nodes/VIOSes. The LPM utility enables a functioning monitoring thread to update the LPM status. In particular, a last monitoring thread may perform cleanup/update operations within the database based on an indication that there are nodes on the first server that are in failed state.

Abstract: Instructions within a processor are managed by receiving, at a recovery unit of the processor, an instruction that modifies a control register residing within the recovery unit. The recovery unit receives a first set of data associated with the instruction from a general register. A second set of data associated with the instruction is retrieved from the control register by the recovery unit. The recovery unit performs at least one binary logic operation on the first set of data and the second data.

Abstract: An information processing apparatus includes an acquiring unit that acquires diagnosis information regarding an operating condition of an image forming apparatus that forms an image, a communication connection unit that establishes a communication connection with the image forming apparatus and a management server via a communication line, a storage controller that stores the diagnosis information acquired by the acquiring unit in a predetermined memory, where the storage controller reduces a data amount of the diagnosis information stored when a communication connection is not established to less than that stored when a communication connection is established, and a transmitting unit that transmits the diagnosis information stored in the memory to the management server if a communication connection is established by the communication connection unit.

Abstract: The disclosure relates to communication technologies and discloses a method and a system for emergency switching. In accordance with the embodiments of the present invention, by configuring a mapped IP address in a previous level network device which can map addresses, the embodiments of the present invention enable corresponding devices in respective service processing subsystems to be backup devices to each other. When a problem occurs in a device of a service processing subsystem, as long as an IP address, which is mapped to the network device, in the previous level network device is mapped to a corresponding device of another service processing subsystem, and the corresponding device in another service processing subsystem acts as a backup device to process a service of the device in which the problem occurs, thus enabling simple and fast starting of a backup device when a problem occurs in the original device.

Abstract: The present invention describes an architecture for hosting and managing disparate, connected applications in a cloud environment. In addition to all of the traditional advantages of the cloud environment, e.g. the economies of renting vs. buying and scalability, this invention allows for management, security, data exchange, authentication, predictive performance and resource integrity it enables business opportunities and models that here-to-fore could not have been realized. Specifically an example being providing on a global scale an intelligent platform for managing a citizens health and health care, this patent covers the enabling technologies and the enabling business models and user interfaces.

Abstract: Embodiments are configured to improve the stability of a Web browser by identifying plug-in modules that cause failures. Data in memory at the time of a failure is analyzed, and a failure signature is generated. The failure signature is compared to a database of known failure signatures so that the source of the failure may be identified. If a plug-in module to a Web browser is identified as the source of a failure, options are presented to the user who may update the plug-in module with code that does not produce a failure or disable the plug-in module altogether.

Abstract: Systems and methods are disclosed for identifying repair points reported by individuals at one or more locations in a geographic area, and providing an effective process for dispatching repair crews. Event data related to a repair point is provided, where the event data is processed to determine the type(s) of repair needed, times and locations of reported events, as well as relationships between events and priority. This information is then used to prioritize dispatch to repair crews to address the events, and further monitor repair crews to determine status of repairs, and to further update priorities relating to ongoing repairs.

Abstract: In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Abstract: A redundant two-processor controller having a first processor (1) and a second processor (1) for the synchronous execution of a control program. The controller having at least a first multiplexer (70, 91) for optionally connecting at least a first peripheral unit (72, 95) to be actuated to one of the two processors (1, 2), and at least a first Comparison unit (70, 91) for monitoring the synchronization state of the two processors (1, 2) and for detecting a synchronization error. A restoration control unit (44) is designed to monitor the execution of at least one test program by the two processors (1, 2) after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer (70, 91).

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.

Abstract: An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.

Abstract: The present disclosure provides a method and apparatus for backing up a subversion repository. In one embodiment, a method of backing up a subversion repository wherein a version attribute of a backup repository is preset and identifies a latest version of the backup repository, the method comprises: synchronizing the backup repository based on the version attribute of the backup repository; in an event of successful synchronization, updating the version attribute of the backup repository with an identification of a synchronized version; and in an event of unsuccessful synchronization, determining that a current version to be a non-synchronizable version, backing up an original repository by duplicating a copy of the original repository, and updating the version attribute of the backup repository with an identifier of the non-synchronizable version.

Abstract: A system includes a production computer machine that includes an operating system and a driver stack. The driver stack includes a file system layer, a recovery driver, a storage layer, a driver layer, a bus driver layer, and a storage device. The system also includes a backup computer processor coupled to the production computer machine via the recovery driver. The recovery driver is configured to commence a recovery of data from the backup computer processor, receive a disk access request from the file system layer, determine if the disk access request accesses data that has not yet been recovered from the backup computer processor, and initiate an on-demand recovery request from the backup computer processor when the data has not been recovered from the backup computer processor.

Abstract: A method for event management in asynchronous work processing including timing at least one step in an asynchronous work process, wherein the at least one step is performed by an application and the at least one step has an expected time of completion; determining an error preventing step completion in response to the expected time of completion expiring; correcting the error; and re-performing the at least one step.

Abstract: Aspects of the invention provide for a fault processing system. In one embodiment, the fault processing system includes: a first processing engine wrapper having: an inbound pipe configured to obtain a first claimcheck data packet; a processing engine component configured to: process a first context message derived from the first claimcheck data packet according to a fault rule selected from: a fault detection rule, a fault location rule, a fault isolation rule, or a fault restoration rule; and generate a second context message, the second context message including data processed according to the selected fault rule; and an outbound pipe configured to provide a second claimcheck data packet derived from the second context message.

Abstract: Embodiments of the invention provide systems and methods for handling internal compiler errors encountered during compilation of a computer program without breaking the compilation. Implementations of a computer-implemented compiler system include a compiler driver, configured to compile a computer program according to a set of compiler settings, and a number of compiler components, each corresponding to a portion of the computer program. Each compiler component is configured to detect an internal compiler error during compilation of the component; identify a recovery plan having a recovery target and at least one recovery setting; and direct the driver to continue compiling the computer program according to the recovery plan, such that the compilation recompiles from the recovery target and according to a modified set of compiler settings according to the at least one recovery setting.

Abstract: According to one embodiment, an error correction channel determination module determines, a channel to be allocated to a logical page as an error correction channel so that each of a plurality of channels is allocated to a uniform number of logical pages as the error correction channel. A command list generation module generates a list of write commands each specifying that a corresponding logical page is to be written using, in parallel, channels included in the plurality of channels and excluding the error correction channel, based on the determination of the channel to be allocated to the corresponding logical page as the error correction channel. A command list issue module issues the list of the write commands.

Abstract: Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.

Abstract: Fast error reporting is provided in networks that have an architected delayed error reporting capability. Errors are detected and reported without having to wait for a timeout period to expire. Further, failures of other components caused by the delay are avoided, since the delay is bypassed.

Abstract: A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location.

Abstract: A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: A setup module organizes a single software image for a management command. A process module creates a plurality of processes independently executing the management command on each of the plurality of devices from a management console. Each process employs the software image. A termination module ends the management command after each process has completed on each of the plurality of devices.

Abstract: Systems. Methods, and Computer Program Products are provided for recovering transactions of failed nodes using a recovery procedure in a clustered file system (CFS). A data segment is determined that the data segment should be copied to a final storage location by validating that an ownership of the data segment is not associated with any other operational node, via a distributed shared memory (DSM) agent. The ownership of the data segment is set to a local DSM agent.

Abstract: When a determination is made that a signal transmitted by a voltage sensor, a second voltage sensor, a current sensor, a temperature sensor, a second temperature sensor, a first CPU, a second CPU and a communication circuit is in error, a third CPU of a motor generator ECU determines that the control system is in error. When a determination is made that the control system is in error, the third CPU determines whether each of the voltage sensors, the current sensor, the temperature sensors, the first CPU, the second CPU and the communication circuit is in error or not.

Abstract: A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

Abstract: Described herein are technologies pertaining to matrix computation. A computer-executable algorithm that is configured to execute perform a sequence of computations over a matrix tile is received and translated into a global directed acyclic graph that includes vertices that perform a sequence of matrix computations and edges that represent data dependencies amongst vertices. A vertex in the global directed acyclic graph is represented by a local directed acyclic graph that includes vertices that perform a sequence of matrix computations at the block level, thereby facilitating pipelined, data-driven matrix computation.

Abstract: A wireless communications device may be configured to perform integrity checking and interrogation with a network entity to isolate a portion of a failed component on the wireless network device for remediation. Once an integrity failure is determined on a component of the device, the device may identify a functionality associated with the component and indicate the failed functionality to the network entity. Both the wireless network device and the network entity may identify the failed functionality and/or failed component using a component-to-functionality map. After receiving an indication of an integrity failure at the device, the network entity may determine that one or more additional iterations of integrity checking may be performed at the device to narrow the scope of the integrity failure on the failed component. Once the integrity failure is isolated, the network entity may remediate a portion of the failed component on the wireless communications device.

Abstract: A maintenance free storage container includes a plurality of storage servers, wherein the maintenance free storage container allows for multiple storage servers of the plurality of storage servers to be in a failure mode without replacement. The maintenance free storage container further includes a container controller operable to establish a first mapping of a plurality of virtual storage servers to at least some of the plurality of storage servers and facilitate storage of encoded data slices in the at least some of the plurality of storage servers. The container controller is further operable to when evaluation of storage server utilization information triggers an adjustment, adjust the first mapping to produce a second mapping, facilitate storage of new encoded data based on the second mapping, and facilitate modification of storage of the encoded data slices stored in accordance with the first mapping based on the data storage adjustment criteria.

Abstract: Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.

Abstract: A method begins by a dispersed storage (DS) processing module determining storage device failure information for a plurality of storage devices within a maintenance free storage container, wherein the maintenance free storage container allows for multiple storage devices of the plurality of storage devices to be in a failure mode without replacement and wherein the storage device failure information indicates storage devices of the plurality of storage devices that are in the failure mode. The method continues with the DS processing module maintaining a dynamic container address space of the maintenance free storage container based on the storage device failure information. The method continues with the DS processing module managing mapping of container addresses of the dynamic container address space to dispersed storage network (DSN) addresses of an assigned DSN address range.

Abstract: In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.

Abstract: Disclosed is an RFID tag that is provided with a laminate forming a layered structure; an antenna disposed with respect to the laminate so as to enable external communication; and an RFID circuit electrically connected to the antenna. The laminate has a shielding member for shielding from radiation, and the RFID circuit is arranged in the laminate so as to be covered by the shielding member.

Abstract: For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data. The data is placed among data storage ranks The data storage ranks are balanced according to the adaptive data placement plan.

Abstract: A premises based multimedia communication system includes a source device that produces multimedia content, a rendering device that presents the multimedia content, and a premises communication network coupling the source device to the rendering device. The system determines a bit error rate of the premises communication network, transfers the multimedia content from the source device to the rendering device, and when the bit error rate exceeds a bit error rate threshold, the system at least partially disables link layer encryption of video frames of the multimedia content transfer. With the link layer operations at least partially disabled, the system can enable, at least partially, content layer encryption operations for the transfer of the multimedia content from the source device to the rendering device.

Abstract: A computer includes a central processing unit (CPU), a power supply, a control unit, a switch unit connected to the CPU and the control unit, a north bridge chip connected between the switch unit and the power supply. The CPU includes a temperature detection unit to detect temperature of the CPU. When the temperature of the CPU is greater than a predetermined value, the CPU outputs a first low level signal to the switch unit. When the button is pressed, the control unit outputs a second low level signal to the switch unit. When the switch unit receives at least one of the first and second low level signals, the switch unit outputs a control signal to the north bridge chip to disable the power supply, thereby turning off the computer.

Abstract: The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

Abstract: A method and system for recovery of a computing environment includes monitoring during a pre-boot phase and a runtime phase of a computing device for selection of a hot key sequence by a user and performing a recovery action in response to the selection of the hot key sequence by the user. The recovery action may be any one of a number of predetermined and/or selectable actions such as restoring system defaults, migrating memory, displaying a menu of options, setting various software flags, restarting or rebooting the computing device, and/or the like.

Abstract: A plurality error correction circuits connected with series includes a calculator circuit corrects the codeword when the determination results of a determining circuit indicate that the error correcting circuit at the present stage is to correct the codeword, and a determining circuit at a subsequent error correction apparatus determines whether the error correcting circuit at the subsequent stage is to correct the codeword when the determination results of the determining circuit indicate that the error correcting circuit at the present stage is not to correct the codeword.

Abstract: A method for initiating a refresh operation of a solid-state nonvolatile memory device coupled to a processor is disclosed. The method comprises determining an error number for a block of the solid-state nonvolatile memory. The error number corresponds to an amount of error bits in a page of the block having a greatest amount of error bits. The method further comprises comparing the error number with an error threshold and determining a reset number indicating an amount of times that the processor has been reset since a previous refresh operation was performed on the block of the solid-state nonvolatile memory. The method further includes comparing the number of resets with a reset threshold and refreshing the block of the solid-state nonvolatile memory when the number of errors exceeds the error threshold and the number of resets exceeds the reset threshold.

Abstract: While system-directed checkpointing can be implemented in various ways, for example by adding checkpointing support in the memory controller or in the operating system in otherwise standard computers, implementation at the hypervisor level enables the necessary state information to be captured efficiently while providing a number of ancillary advantages over those prior-art methods. This disclosure details procedures for realizing those advantages through relatively minor modifications to normal hypervisor operations. Specifically, by capturing state information in a guest-operating-system-specific manner, any guest operating system can be rolled back independently and resumed without losing either program or input/output (I/O) continuity and without affecting the operation of the other operating systems or their associated applications supported by the same hypervisor.

Abstract: A method and apparatus for parallel and adaptive signal reconstruction from a multitude of signal measurements. Algorithms and hardware are disclosed to denoise the measured signals, to compress the measured signals, and to reconstruct the signal from fewer measurements than standard state-of-the-art methods require. A parallel hardware design is disclosed in which the methods that are described can be efficiently executed.

Abstract: A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.

Abstract: A process is disclosed for identifying and recovering from resource leaks on compute nodes of a parallel computing system. A resource monitor stores information about system resources available on a compute node in a clean state. After the compute node runs a job, the resource monitor compares the current resource availability to the clean state. If a resource leak is found, the resource monitor contacts a global resource manger to remove the resource leak.

Abstract: A method of managing errors in a data processing system (10) may involve at least one computer system (14). Each computer system (14) may include a plurality of hardware components (18), including a processor (20) for executing a respective operating system and a memory (22) for storing instructions for the respective operating system (24), and firmware (28) including a firmware error handler (30). For each computer system (14), the firmware error handler (30) may identify an error occurring in one of the hardware components (18). Each respective firmware error handler (30) may communicate error information about the identified error to an error manager (32) external of the computer system (14). The error manager (14) may compile the error information communicated from each respective firmware error handler (30).