Error Or Fault Handling (epo) Patents (Class 714/E11.023)
  • Publication number: 20130238927
    Abstract: A device power is supplied for running a storage device. When a device error occurs, a recovery operation is performed on the storage device. When the recovery operation fails, the device power is reset in a compatibility verification operation and the recovery operation is performed again on the storage device.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: SYNOLOGY INCORPORATED
    Inventors: Hsuan-Ting Chen, Kuei-Huan Chen, Ming-Hung Tsai
  • Publication number: 20130227369
    Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to error detection or correction of stored signals in memory devices.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Publication number: 20130227368
    Abstract: A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicants: BOSTON UNIVERSITY, FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ravindraraj Ramaraju, Ajay J. Joshi, Bobak A. Nazer
  • Publication number: 20130227336
    Abstract: In one embodiment, an intermediate device transmits a data message away from a root device toward a receiver device in a computer network, the data message transmitted by utilizing, in reverse, a link that had been previously selected by the receiver device toward the root device. In response to detecting that the data message did not reach the receiver device, a discovery message is may be sent to one or more neighbor devices, wherein the discovery message carries an identification (ID) of the receiver device and a discovery scope indicating how many hops the discovery message is allowed to traverse to reach the receiver device, and wherein the receiver device, upon receiving the discovery message, triggers a local link repair of the link from the receiver device toward the root device.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: Cisco Technology, Inc.
    Inventors: Navneet Agarwal, Jean-Philippe Vasseur
  • Publication number: 20130219211
    Abstract: A method, an apparatus and an article of manufacture for cloud-driven application execution. The method includes determining a plurality of attributes of a failed application, wherein the plurality of attributes comprises at least one policy context attribute and at least one context attribute, correlating each of the plurality of attributes to at least one alternative asset, wherein the at least one alternative asset is a part of an environment on which the failed application can be executed, using the plurality of attributes correlated to the at least one alternative asset to identify an alternative asset set of alternative assets, wherein the alternative asset set is capable of enabling an alternative environment on which to execute the failed application, and provisioning the alternative assets in the alternative asset set from at least one cloud network to create the alternative environment on which the failed application is executed.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ramesh Gopinath, Andrzej Kochut, Kathiravan M. Ramaswami, Anca Sailer, Charles O. Schulz, Hidayatullah Shaikh
  • Publication number: 20130219234
    Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: LSI CORPORATION
    Inventors: Varun Shetty, Debjit Roy Choudhury, Dipankar Das, Ashank Reddy
  • Publication number: 20130212422
    Abstract: Various embodiments provide a method and apparatus of providing a rapid disaster recovery preparation in cloud networks that proactively detects disaster events and rapidly allocates cloud resources. Rapid disaster recovery preparation may shorten the recovery time objective (RTO) by proactively growing capacity on the recovery application(s)/resource(s) before the surge of recovery traffic hits the recovery application(s)/resource(s). Furthermore, rapid disaster recovery preparation may shorten RTO by growing capacity more rapidly than during “normal operation” where the capacity is increased by modest growth after the load has exceeded a utilization threshold for a period of time.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: Alcatel-Lucent USA Inc.
    Inventors: Eric J. Bauer, Randee S. Adams, Daniel W. Eustace
  • Patent number: 8510564
    Abstract: Embodiments are directed to establishing the integrity of a portion of data on at least one level of a plurality of network stack levels and automatically continuing an established federation relationship between at least two federation computer systems. In an embodiment, a first federation computer system receives a digital signature corresponding to a computer system signed by a digital signature which includes the computer system's identity and other federation relationship information configured to establish a trusted federation relationship between a first federation computer system and a second federation computer system. The first federation computer system attempts to validate the received digital signature at a first level of a network stack and determines that the validation at the first network stack layer was unsuccessful. The first federation computer system then validates the received digital signature at a second, different level of the network stack.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: August 13, 2013
    Assignee: Microsoft Corporation
    Inventors: David J. Nicholson, David Lewis Fisher, Michael D. Ritche, Chun-Hung Lin, Christopher B. Dove, Kavitha Radhakrishnan
  • Publication number: 20130198556
    Abstract: Methods and apparatus are provided for determining a lowest total cost maintenance plan. The method comprises receiving a sequence of maintenance actions in an order of a waiting time for each maintenance action, wherein one of the maintenance actions is likely to repair the failure mode. Each maintenance action has an associated cost equal to a waiting time cost, an execution time cost and a material cost, wherein the waiting time of each maintenance action is the time required to requisition and receive material required to perform the maintenance action. The method also constructs a maintenance plan comprising a primary requisition and a secondary requisition by assigning each of the sequence of maintenance actions to one of the primary and secondary requisition.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: David Michael Kolbet, Ravindra Patankar, Randy R. Magnuson
  • Publication number: 20130198558
    Abstract: Devices, methods and instructions encoded on computer readable medium for implementation of a dual-adjacency between edge devices of a network site. A first edge device comprises one or more local interfaces configured for communication, via a local network, with one or more network devices co-located in a first network site. The first edge device also comprises one or more overlay interfaces configured for communication, via a core network, with one or more network devices located in one or more other network sites connected to the core network. The first edge device comprises a processor configured to establish, via at least one of the local interfaces, a site communication channel with a second edge device co-located in the first network site. The processor is further configured to establish an overlay communication channel, via at least one of the overlay interfaces, with the second edge device.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Dhananjaya Rao, Victor M. Moreno, Hasmit Grover, Gaurav Badoni
  • Publication number: 20130185609
    Abstract: A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array.
    Type: Application
    Filed: November 5, 2012
    Publication date: July 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Publication number: 20130179607
    Abstract: Data is buffered for concurrent writing to tape. For a magnetic tape drive having a magnetic head with multiple sets of transducers; a drive mechanism configured to pass a magnetic tape past the magnetic head; interfaces from two different hosts; and at least one buffer configured to buffer data; and a control; the buffering comprises receiving data from two different hosts at the interfaces; buffering the received data in separate buffer space of the buffer(s) associated with each host, and adjustably size the separate buffer space for each host in accordance with a data transfer rate of the host associated with the separate buffer space; and concurrently writing data from the separate buffer spaces with the magnetic head to separate partitions of the magnetic tape.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: SHAWN O. BRUME, FAHNMUSA C. JANGABA
  • Publication number: 20130173980
    Abstract: The present invention provides a switching converter with pulse skipping mode. The switching converter comprises a switching circuit having at least one switch, a controller and a feedback circuit. The controller comprises an error amplifying circuit, a logic circuit, a ramp signal generator and a pulse skipping circuit. The error amplifying circuit generates a compensation signal based on comparing the feedback signal with a reference signal. The logic circuit generates a control signal to control the ON and OFF switching of the at least one switch based on the compensation signal. The ramp signal generator generates a ramp signal. The pulse skipping circuit generates a pulse skipping signal based on the compensation signal, the ramp signal and a threshold voltage. The logic circuit skips one or more switching pulses of the control signal in accordance with the pulse skipping signal.
    Type: Application
    Filed: March 7, 2012
    Publication date: July 4, 2013
    Inventor: Xiaoyu Xi
  • Publication number: 20130166980
    Abstract: A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Guillaume SCHON, Luca Scalabrino, Frederic Claude Marie Piry, David Michael Bull
  • Publication number: 20130159764
    Abstract: An apparatus and method of PCIe error handling and recovery actions taken in the event of an error. An error reporting extension defines a set of commonly used actions that are taken by a device in response to the detection of an error. This minimizes the side effects of continued device operation following the occurrence of an error. The device's error handling capabilities are advertised and the system software specifies the desired device action to take upon occurrence of a particular error. The particular error handling action is defined uniquely for each PCIe function and error type, such that different errors trigger a different type of action, thereby affecting only specific device functions or the entire device, depending on the configuration. Error handling actions and control fields are placed in the extension portion of the PCI Express Advanced Error Reporting configuration space.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Etai Adar, Ilya Granovsky
  • Publication number: 20130159769
    Abstract: Embodiments of the present invention relate to detecting and rectifying corruption in a distributed clock in a distributed system. Aspects may include receiving a sequence number used as part of the distributed clock at a node and determining if the sequence number is corrupt. In order to provide an effective mechanism for determining a sequence number is corrupt and taking corrective actions, a valid sequence number range may be determined, a propagation count associated with the sequence number may be evaluated, an estimated sequence number may be calculated, and an epoch number associated with the sequence number may be evaluated. Additionally, in exemplary aspects node with a corrupt trusted sequence values may self diagnosis and terminate associated processes to prevent further propagation of the corrupt sequence number.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: GARRET J. BUBAN, RITESH KUMAR
  • Publication number: 20130159804
    Abstract: The subject disclosure is directed towards a technology by which the accuracy of context-based information provided by at least one data source for received context data is increased. Correctness information received in association with usage of looked up context-based information is logged. The correctness information may be processed to increase the overall accuracy by correcting a data source, and/or by creating a blended data source that includes the most likely accurate portions (segments) from among multiple data sources as determined via the correctness information.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Applicant: Microsoft Corporation
    Inventors: Yutaka Suzue, Johnson T. Apacible, Mark J. Encarnación, Jamie Huynh, Simon D. Bernstein
  • Publication number: 20130151891
    Abstract: A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: ARM LIMITED
    Inventors: Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Publication number: 20130151919
    Abstract: A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes a processor, a fault protect circuit, a first terminal, a driver that drives the first terminal, a second terminal, and detection circuitry that outputs a digital detection signal indicative of whether a predetermined condition is detected on the second terminal. The processor can program the fault protect circuit so that the fault protect circuit will later disable the driver as a function of multiple signals, including the digital detection signal. The function is programmable by the processor. In one example, if the detection circuitry detects the predetermined condition on the second terminal then the fault protect circuit disables all the high-side drivers and all low-side drivers of the MTPMIC independently of and without input from the processor.
    Type: Application
    Filed: April 24, 2012
    Publication date: June 13, 2013
    Applicant: Active-Semi, Inc.
    Inventor: Steven Huynh
  • Publication number: 20130145203
    Abstract: A stream application may allocate processing elements to one or more compute nodes (or hosts) to achieve a desired optimization goal. Each optimization mode may define processing element selection criteria and/or host selection criteria. When allocating a processing element to a host, a scheduler may place each processing element individually. Accordingly, the scheduler may use the processing element selection criteria for selecting which processing element in the stream application to allocate next. The scheduler may then determine, based on one or more constraints, which host the processing element can be placed on. If the scheduler determines that multiple hosts are suitable candidates for the processing element, it may use the host selection criteria to pick one of the candidate hosts that further optimize the stream application to meet the desired goal.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Bradley W. Fawcett
  • Publication number: 20130145202
    Abstract: A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Sebastien Nussbaum, Rex McCrary, Philip J. Rogers, Mark Leather
  • Publication number: 20130136214
    Abstract: According to one embodiment, a scaling decision device includes a first decision unit and a second decision unit. The first decision unit decides, based on a plurality of input signals, a K-th smallest signal of the plurality of input signals or a range to which the K-th smallest signal belongs of a plurality of ranges which classify the plurality of input signals by intensities. The second decision unit decides, based on a decision result of the first decision unit, a scaling value which prevents the K-th smallest signal from being submerged in quantization errors by normalization.
    Type: Application
    Filed: March 19, 2012
    Publication date: May 30, 2013
    Inventor: Toshiyuki YAMAGISHI
  • Publication number: 20130132769
    Abstract: A method that includes identifying a failure indication for a first data storage device that is a member of a first RAID group within a storage array. The method further can include, via a processor external to the storage array, identifying a virtual drive that is defined to include at least one logical storage volume defined in a second RAID group. The virtual drive can be provisioned to serve as a virtual hot spare within the first RAID group to replace the first data storage device.
    Type: Application
    Filed: July 20, 2012
    Publication date: May 23, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: JANMEJAY S. KULKARNI
  • Publication number: 20130124930
    Abstract: Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kokil K. Deuri, Vishal R. Mansur, Arpana Prashanth, Dilip K. Singh
  • Publication number: 20130117601
    Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
  • Publication number: 20130117604
    Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Publication number: 20130117605
    Abstract: Techniques for taking corrective action based on probabilities are provided. Request messages may include a size of a data packet and a stated issue interval. A probability of taking corrective action based on the size of the data packet, the stated issue interval, and a target issue interval may be retrieved. Corrective action may be taken with the retrieved probability.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Inventors: Michael L. Ziegler, Paymon Ghamami
  • Publication number: 20130117620
    Abstract: A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.
    Type: Application
    Filed: April 18, 2012
    Publication date: May 9, 2013
    Inventors: Sang-Hyun JOO, Kitae PARK, Sangyong YOON, Jinman HAN
  • Publication number: 20130111287
    Abstract: A memory storage device, a memory controller thereof and a data transmission method thereof are provided. The memory storage device includes a rewritable non-volatile memory module having a first and a second memory dies, and the first and the second memory dies are coupled to the memory controller through the same data input/output bus. The method includes transmitting a read command to the first memory die and then transmitting a write command to the second memory die by the memory controller. The method further includes controlling the first and the second memory dies to respectively read out and put data onto the data input/output bus in accordance with the read command and write the data from the data input/output bus into the second memory die in accordance with the write command at the same time by the memory controller.
    Type: Application
    Filed: January 3, 2012
    Publication date: May 2, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Shen-Yi Chao
  • Publication number: 20130111278
    Abstract: A hardware phase shift correction method for a multi-channel apparatus is provided. The method includes the following steps. A multi-channel apparatus including a plurality of analog circuits is provided, wherein the multi-channel apparatus transmits an analog signal and receives an echo signal. In a receiving path test mode, a plurality of first test signals are received. The first test signals are enabled to pass through a receiving path of the multi-channel apparatus, and converted to a plurality of test data. In response to the test data corresponding to the first test signals, phase shift correction for the channels is performed.
    Type: Application
    Filed: May 17, 2012
    Publication date: May 2, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fu-Chiang Jan, Wei-Cheng Lu, Chih-Yu Chang
  • Publication number: 20130103973
    Abstract: The present solution provides increases in automation, scalability and efficiency for delivering technical support services to devices. Systems and methods of the present solution provide a hierarchy or layers of automated desktop services with remote technical support services, which may be automated. The present solution provides an on desktop automation support system that detects and automatically remediates problems on a device of the user. If the problem is not fixed or fixable via local automated remediation at the desktop, a centralized service may remotely deliver technical support services to the device in the form of automated support services delivered to the device or remote technical agents connecting remotely with the device. With the combination of local support automation, remote support automation, remote and onsite technicians, the centralized service may deliver a hierarchy or multi-layers of services to any device.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 25, 2013
    Applicant: PlumChoice. Inc.
    Inventor: PlumChoice. Inc.
  • Publication number: 20130103972
    Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Inventors: Emre Özer, Yiannakis Sazeides, Daniel Kershaw, Stuart David Biles
  • Publication number: 20130091381
    Abstract: The operator terminal receives input of the terminal status of the recovery target terminal 10 from an operator, extracts a recovery item for recovering the terminal status of the recovery target terminal 10 and a recovery set value being a value recovered corresponding to the recovery item based on the input terminal status, and generates a recovery code at least including the recovery item and the recovery set value. The recovery target terminal 10 decodes the recovery code in response to input of the recovery code to acquire the recovery item and the recovery set value and executes a recovery process for the terminal status based on the acquired recovery item and the acquired recovery set value.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 11, 2013
    Applicant: OPTIM CORPORATION
    Inventor: Shunji SUGAYA
  • Publication number: 20130086413
    Abstract: A method for fast I/O path failure detection and cluster wide failover. The method includes accessing a distributed computer system having a cluster including a plurality of nodes, and experiencing an I/O path failure for a storage device. An I/O failure message is generated in response to the I/O path failure. A cluster wide I/O failure message broadcast to the plurality of nodes that designates a faulted controller. Upon receiving I/O failure responses from the plurality nodes, an I/O queue message is broadcast to the nodes to cause the nodes to queue I/O through the faulted controller and switch to an alternate controller. Upon receiving I/O queue responses from the plurality nodes, an I/O failover commit message is broadcast to the nodes to cause the nodes to commit to a failure and un-queue their I/O.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: SYMANTEC CORPORATION
    Inventors: Kirubakaran Kaliannan, Venkata Sreenivasa Rao Nagineni
  • Publication number: 20130086433
    Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma
  • Publication number: 20130086411
    Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: identifying a hardware failure of a failed component of a plurality of hardware components; determining a set of agent devices currently configured to utilize the failed component; reconfiguring an agent device to utilize a working component of the plurality of hardware components. Various exemplary embodiments additionally or alternatively relate to a method and related network node including one or more of the following: projecting a failure date for the hardware module; determining whether the projected failure date is acceptable based on a target replacement date for the hardware module; if the projected failure date is not acceptable: selecting a parameter adjustment for a hardware component, wherein the parameter adjustment is selected to move the projected failure date closer to the target replacement date, and applying the parameter adjustment to the hardware component.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Alcatel-Lucent USA, Inc.
    Inventors: Eric J. Bauer, Randee S. Adams, William D. Reents, Mark M. Clougherty
  • Publication number: 20130080831
    Abstract: A storage apparatus includes a storage drive which writes and reads out a block of data with respect to a storage medium loaded on the storage apparatus, a processor which executes access control on a plurality of volumes assigned to the storage medium and a memory which stores a piece of management information that includes a piece of information indicating a usage frequency of each of the volumes. The processor executes a procedure including: determining a reallocation target volume from among a plurality of volumes assigned to the storage medium based on the management information, and moving the data of the reallocation target volume to a reallocation destination storage medium which is different from the storage medium.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 28, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Hiroaki NISHIJO, Yasuhiko Hanaoka
  • Publication number: 20130073892
    Abstract: Disclosed herein are methods, systems, and articles associated with remediation execution. In embodiments, a set of policy test failures may be selected for remediation. The set of policy test failures may be associated with a computer network with a number of nodes. For each failure within the set of policy test failures, a remediation script may be obtained to remediate a corresponding policy test failure. The remediation scripts may be selectively provided to nodes that are affected by policy test failures, for execution by the nodes. A remediation script result for each remediation script executed may be received. Based upon the remediation script results, it may be determined whether or not execution of the remediation scripts was successful.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: TRIPWIRE, INC.
    Inventors: David Whitlock, Guy Gascoigne-Piggford, Geoff Granum, Mark Petrie
  • Publication number: 20130073893
    Abstract: Disclosed herein are methods, systems, and articles associated with remediation workflow. A method may include determining one or more test failures related to a policy test within a computer network, and reviewing the one or more test failures. The method may further include, based upon a result of the reviewing, creating a remediation work order that includes at least one of the one or more test failures. Each test failure within the remediation work order may be approved or denied. For each test failure that is approved for remediation, a remediation process may be executed.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: TRIPWIRE, INC.
    Inventors: David Whitlock, Guy Gascoigne-Piggford, Geoff Granum, Mark Petrie
  • Publication number: 20130073903
    Abstract: A system and method for distributing prepaid cash alternatives and resolving exceptions related to the sale of prepaid cash alternatives such as traveler's cheques or prepaid cards. Reports of sales may be reviewed to identify exceptions, and information explaining the exceptions may be made available electronically. Sellers may be notified of exceptions by e-mail, which may include a link or address to information explaining the exceptions. The information may be provided in real time through a secure site on a network, such as the Internet. A company may contract with business partners to sell the prepaid cash alternatives to customers, and the business partners may report the sales to the company via reports. After being notified of exceptions, business partners may provide corrected information or new information to resolve the exceptions.
    Type: Application
    Filed: November 14, 2012
    Publication date: March 21, 2013
    Applicant: American Express Travel Related Services Company, Inc.
    Inventor: American Express Travel Related Services Compa
  • Publication number: 20130061085
    Abstract: A system and method for managing an IT infrastructure using a mobile device, the method comprises identifying, using one or more processors of a network management system, an issue in one or more components in the infrastructure; retrieving a message instruction for the identified issue from an action database, wherein the message instruction includes information identifying a support personnel and a mobile device of the support personnel to contact regarding the identified issue; sending an alert message to the mobile device of the identified support personnel, wherein the alert message contains information of the identified issue; receiving, at the network management system, a reply message from the mobile device, wherein the reply message contains an instruction to resolve the identified issue; generating an executable command corresponding to the instruction in the reply message; and executing the executable command on the affected components in the infrastructure to resolve the identified issue.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Applicant: INFOSYS LIMITED
    Inventor: Arun Gautham Raja Rao
  • Publication number: 20130061089
    Abstract: Embodiments are directed to efficiently backing up portions of data and to performing a scoped data recovery. In an embodiment, a computer system preloads data images with data corresponding to various different software applications or operating systems. The computer system chunks the data images, so that each data image is divided into multiple data chunks, and where each data chunk is represented by a hash value. The computer system then receives, from a user, portions of delta data representing data differences between the received user data and the data in the preloaded data images. The computer system also generates a logical backup representation that includes the data chunk hash values for the preloaded data images as well as the delta data received from the user. This logical representation allows restoration of the user's data using only the hash values and the delta data.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Manoj K. Valiyaparambil, Amit Singla, Vijay Sen, Abid Ali
  • Publication number: 20130061099
    Abstract: The present invention describes how to handle errors occurring during communication in a frame-based communication system that uses a communication protocol having a first error handling mechanism responsive to receipt of an incorrect protocol symbol. The invention provides a method and apparatus that allow several errors to occur without the communication system responding by initiating the first error handling mechanisms. Under circumstances where errors occur, the method and apparatus may improve throughput.
    Type: Application
    Filed: May 27, 2011
    Publication date: March 7, 2013
    Applicant: ST-ERICSSON SA
    Inventor: Andrei Radulescu
  • Publication number: 20130055042
    Abstract: A data quality analysis and management system includes a data quality testing module to perform data quality tests on received data and determine data quality statistics from the execution of the data quality tests. The system also includes a data quality analysis and management engine to determine data quality cost metrics including cost of setup, cost of execution, internal data cost, and external data cost, and calculate a cost of data quality from the data quality cost metrics, and a reporting module to generate a data quality scorecard including statistics determined from execution of the data quality tests by the data quality testing module and the cost of data quality determined by the data quality analysis and management engine.
    Type: Application
    Filed: August 31, 2012
    Publication date: February 28, 2013
    Applicant: Accenture Global Services Limited
    Inventors: Ashraf Al Za'noun, Lisa Wilson
  • Publication number: 20130055046
    Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventor: Greg A. Blodgett
  • Publication number: 20130055019
    Abstract: A pilot process method for system boot and an associated are provided. An environment variable is read from a NAND flash memory. When an irrevocable error exists in an environment variable, the environment variable is read successively for a predetermined threshold number of times. A backup variable of the environment variable is read when the irrevocable error is still present in the environment variable that is read for a predetermined threshold number of times, and the environment variable is restored according to the backup variable. Therefore, when it is confirmed that the environment variable is damaged, a backup variable is utilized and the damaged environment variable is restored according to the backup variable, so as to ensure a normal boot-up process of the system to significantly enhance system reliability as well as user experience.
    Type: Application
    Filed: January 12, 2012
    Publication date: February 28, 2013
    Applicant: MStar Semiconductor, Inc.
    Inventor: Tao Zhou
  • Publication number: 20130055008
    Abstract: Example embodiments relate to downloading a disk image from a server while reducing the corruption window. In example embodiments, a computing device writes a recovery image to a portion of a primary storage device. The computing device may then write the disk image to the primary storage device until a portion of the disk image corresponding to the recovery image remains. Next, the computing device may write the remaining portion of the disk image to a secondary storage location. Finally, the computing device may overwrite the recovery image using the remaining portion of the disk image from the secondary storage location.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Emmanuel Dimitri Christian Ledoux, Fletcher Liverance, Timothy J. Freese
  • Publication number: 20130047050
    Abstract: A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.
    Type: Application
    Filed: June 28, 2012
    Publication date: February 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Shinya KUWAMURA, Atsushi Ike
  • Publication number: 20130047031
    Abstract: A system and method is disclosed for recovering a boot image from a secure location. Hardware instructions initiate a sequence of boot cycles to launch a computer operating system on a computer-enabled device. During the boot cycles, multiple levels of boot code are verified and a determination is made whether each level is usable by the device. If a level of boot code is determined to be unusable, a secure copy of the boot code is loaded from a secure read-only location to repair the unusable code to launch the computer operating system.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Applicant: GOOGLE INC.
    Inventors: Ryan TABONE, Randall R. Spangler
  • Publication number: 20130047044
    Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.
    Type: Application
    Filed: July 19, 2012
    Publication date: February 21, 2013
    Applicant: STEC, Inc.
    Inventors: Anthony D. Weathers, Richard D. Barndt, Xinde Hu