Abstract: A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.

Abstract: A script specifies a script action and an expected reaction in response to the script action. When one of the script actions is executed, a failure is detected indicating that the expected reaction did not occur. In response to the failure, a fallback action is executed.

Abstract: In an embodiment, a method of determining whether to trigger an event based on data blocks having status data includes electronically receiving the data blocks over a channel, performing a data integrity check on the data blocks to determine whether a particular data block has a transmission fault, calculating a received error metric based on performing the data integrity check, and disabling an event trigger if the received error metric crosses a first error threshold.

Abstract: A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.

Abstract: An electronic apparatus includes a sensor unit including a sensing device and configured to transmit detection data acquired with the sensing device; a computing device configured to receive the detection data and compute the corrected value of the detection data; and a memory containing, together with identification information, correction information for computing the corrected value A characteristic of the corrected value is switched by the computing device switching, in accordance with the identification information contained in the memory, a correcting operation method for computing the corrected value using the correction information contained in the memory.

Abstract: According to one embodiment, a cache control apparatus includes an error detecting and correcting module and a controller. The error detecting and correcting module is configured to detect errors in the data read from a cache memory and to correct the errors. The controller is configured to control the supply of power to the cache memory if the error detecting and correcting module is unable to correct errors and if the errors are hard errors.

Abstract: An embodiment of the invention provides a backup method for a portable device to back up a first data to a backup server. The backup method includes steps of determining whether the backup server can be accessed; when the backup server can be accessed, establishing a first data transmission path that the first data would be backed up to the backup server via a third party, a second data transmission path that the first data would be backed up to the backup server via a router, and a third data transmission path that the first data would directly backed up to the backup server; selecting one data transmission path among the first, second and third data transmission paths; and backing up the first data via the selected data transmission path.

Abstract: A device for improving the fault tolerance of a processor installed on a motherboard, the motherboard comprising memory units and a data input/output interface, the processor being able to execute at least one application, includes: a software layer, called a hypervisor, centralizing exchanges between the said processor and the said application and implementing fault tolerance management mechanisms, and a programmable electronic component forming an interface between the processor on the one hand.

Abstract: A server includes a monitor unit configured to monitor a failure of one or more user networks and a recovery support unit configured to support a recovery of the failure of one or more user networks. When detecting an alarm showing occurrence of the failure, the server identifies a user network in which the failure occurs based on both line information for each user network and the alarm, and notifies the alarm to the plurality of management terminals of the identified user network.

Abstract: Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error.

Abstract: A CPU saves a portion of device data stored in a device memory into a save memory every time a scanning process is performed so that the device data can be reliably saved even if a voltage holding time is shortened due to degradation of an electrolytic capacitor, and when a power-failure detecting circuit detects power failure of a main power supply, the CPU saves a remaining portion of the device data stored in the device memory using a power supply held by the electrolytic capacitor. When a capacity of the electrolytic capacitor detected by a capacitor-capacity detecting circuit is reduced, the CPU changes a size of the device data to be saved by a saving process performed every time the scanning process is performed according to the capacity of the electrolytic capacitor detected by the capacitor-capacity detecting circuit such that the size of the device data to be saved every time the scanning process is performed is increased.

Abstract: A monitoring device including: a receiving unit configured to receive a malfunction notice of a data processing device, the data processing device being connected to the monitoring device which monitors running condition through a network; a malfunction device identification unit configured to identify a data processing device that is malfunctioning based on the received malfunction notice; a data obtaining unit configured to obtain running data and device data of the data processing device that is malfunctioning and an another data processing device; and a malfunction cause identification unit configured to identify a cause of the malfunction, based on the obtained running data and the obtained device data.

Abstract: Various embodiments provide a guard mechanism that is configured to prevent transmission of synchronous function calls to hung application components. In at least some embodiments, a hang resistance application layer intercepts a synchronous function call that is intended for an application component. Before permitting the synchronous function call to be transmitted to the application component, the hang resistance application layer determines whether the application component is hung by transmitting a message other than the synchronous function call to the application component that requests that a response be received before transmission of the synchronous function call to the application component is permitted. Responsive to determining that the component is hung, a hung component recovery process is initiated.

Abstract: A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry.

Abstract: An application can specify reliability values via a communication path between the application and the registers. Application reliability could increase if the application itself could specify the timeout and retry values. For instance, some errors might be prevented if the timeout value is lengthened by a short amount. A longer timeout value would result in slower performance because the memory component could not be accessed during the timeout period. However, resolving errors in memory devices would prevent unrecoverable error indicators from being returned to the application, which would in turn limit application and system crashes.

Abstract: According to one embodiment, a data storage device includes a read module, an ECC module, and a controller. The read module is configured to read data to be accessed and designation data designating the data, from nonvolatile memories. The ECC module is configured to perform an error check and correction process on the data and designation data read by the read module. The controller is configured to correct the designation data if the ECC module cannot correct the designation data and to perform an error detection process based on the designation data corrected.

Abstract: System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Abstract: An anomaly detection mechanism is provided that detects an anomaly in a control network, and includes an identifying unit to receive event information on an event that occurs, and to identify a group including a resource related to the event information by referring to a configuration management database for retaining dependence relationships between processes and resources including a control system; a policy storing unit to store one or more policies each of which associates one or more actions with a condition defining a situation suspected to have an anomaly; an adding unit to acquire group-related information needed for application to the one or more policies, and to add the acquired information to the event information; and a determining unit to apply the event information to the one or more policies and to determine the one or more actions associated with the matched condition as one or more actions to be taken.

Abstract: A distortion compensation device includes a distortion compensator that predistorts an input signal based on delay signals and distortion compensation coefficients corresponding to the respective delay signals obtained by applying different amounts of delay to the input signal, a calculator that calculates an error signal based on the predistorted input signal and an output signal from an amplifier that amplifies the predistorted input signal, a calculator that calculates prospective distortion compensation coefficients for updating the distortion compensation coefficients, based on the error signal, a saturation processor that performs saturation processing for bringing, when the prospective distortion compensation coefficients do not fall into a preset range, the prospective distortion compensation coefficients into the preset range, and a controller that controls the updating of the distortion compensation coefficients based on pieces of coefficient saturation information indicating whether the saturation

Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h0=h1+h2; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Abstract: An operation management device includes a collecting unit to receive management data of elements provided in a plurality of management target devices, an analyzing unit to obtain a dependency relation of problematic data defined as data of devices with occurrence of the problem in the received management data according to definition information which defines a dependency relation between the elements and to obtain a dependency relation of non-problematic data defined as data of the devices with non-occurrence of the problem in the received management data according to the definition information, and a comparing unit to obtain management data of a common element by comparing the problematic data with the non-problematic data and to extract a difference between the problematic data and the non-problematic data with respect to management data of elements dependent on the common element.

Abstract: Embodiments of the invention provide systems and methods for the reporting of status changes, such as but not limited to power outages and/or power restorations, throughout a smart grid system. Through the use of location-based reporting period selection and/or status change report aggregation, embodiments may provide efficient reporting processes that timely and accurately report status change information from the point(s) of the change to a back-end system via an access point.

Abstract: Disclosed are an air conditioner, a method for controlling outdoor units thereof, and a central control system having the same. A mode conversion unit such as a boot loader is provided to perform a mode conversion between a driving control mode and an upgrade mode in a software manner, without requiring a user's visit to the site. This may allow an outdoor unit control program to be remotely upgraded. In the present disclosure, the air conditioner may return to a previous mode or previous program in the occurrence of an error on an upgrade signal or upgrade program.

Abstract: An application can specify reliability values via a communication path between the application and the registers. Application reliability could increase if the application itself could specify the timeout and retry values. For instance, some errors might be prevented if the timeout value is lengthened by a short amount. A longer timeout value would result in slower performance because the memory component could not be accessed during the timeout period. However, resolving errors in memory devices would prevent unrecoverable error indicators from being returned to the application, which would in turn limit application and system crashes.

Abstract: A communication apparatus performs communication with another communication apparatus through a communication path. The communication apparatus includes an encoder which is configured to generate B number of check packets from A number of information packets, a packet transmitter which is configured to transmit x number of the information packets and y number of the check packets, and a determination unit which is configured to determine the number of the information packets and the check packets to be transmitted by the packet transmitter to satisfy a condition of A?x+y?A+B in accordance with a state of the communication path.

Abstract: A pattern-dependent error correction method and system for a code group alignment finite state machine (FSM) are disclosed. A state corrector generates a start-of-stream delimiter (SSD) detected signal to the FSM when the FSM is in an idle state and at least one condition due to a lost SSD signal is met; and the state corrector generates an idle detected signal to the FSM when at least one condition due to a lost idle signal is met. A pattern corrector generates a corrected code pattern {J,K} to FSM when the FSM is in an idle state and at least one condition due to a false idle state is met; and the pattern corrector generates a corrected code pattern {T,R} to the FSM when the FSM is in a data state, a start of stream state or a data error state, and at least one condition due to a false packet end is met.

Abstract: Enabling application instructions to access mathematical functions from an accelerated function library to perform instructions. In the performance of the instructions, applying a predefined test instruction on a value, the value being at least one of an input argument, an intermediate result or a final result to determine if the value is a general-case or a predetermined special-case. Responsive to a determination that the value is a special-case, performing a predetermined set of special-case instructions for the performance of the mathematical function.

Abstract: Apparatus and method for recovering errors from erroneous files in a storage system. In order to recover the errors from the erroneous files, each of at least three erroneous files stored in the storage system may be divided in half to form three sets of divided files. Three corresponding, portions from each of the three sets of divided files may be compared. A determination may be made as to whether at least two portions among the three corresponding portions are substantially identical. Based on the determination, substantially identical portions are determined to be non-erroneous portions. Then, a non-matched portion that is not substantially identical to the two substantially identical portions may be replaced with one of the non-erroneous portions.

Abstract: The invention provides an enhanced two phase commit process to perform a transaction started by an application program and involving access to one or more resources managed by respective resource managers. The method comprises the steps of: enlisting the resource managers participating in the transaction, said enlisting step including associating a priority rank with each identified resource manager based on predefined priority rules; sending a prepare signal to said enlisted resource managers to begin the process of committing the transaction; and if a ready signal is received from all resource managers in response to the prepare signal, committing the resource managers in the order defined from the priority ranks associated with the resource managers.

Abstract: A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received.

Abstract: In a circuit, memory controller, memory system, and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: A messaging system may operate on multiple processor partitions in several configurations to provide queuing and topic subscription services on a large scale. A queue service may receive messages from a multiple transmitting services and distribute the messages to a single service. A topic subscription service may receive messages from multiple transmitting services, but distribute the messages to multiple recipients, often with a filter applied to each recipient where the filter defines which messages may be transmitted by the recipient. Large queues or topic subscriptions may be divided across multiple processor partitions with separate sets of recipients for each partition in some cases, or with duplicate sets of recipients in other cases.

Abstract: A method controls the routing of service requests to a plurality of servers using a first routing distribution algorithm. The method includes waiting a first period of time for a designated server to respond to a service request, transmitting the service request to the designated server a second time, and waiting a second period to time for the designated server to respond to the service request assigned to the designated server, the second period of time being longer than the first period of time. The method also includes determining that the designated server has failed, rerouting the service request to a different server, and routing the service requests to the plurality of servers using a second routing distribution algorithm.

Abstract: A method for modifying a user interface (UI), comprising the steps of: listening for a UI event; determining whether the UI event is erroneous; in response to determining that the UI event is erroneous, initiating a recording comprising a user fix of the error and a state associated with the UI; storing the user fix as an alternative UI event; and in response to subsequently detecting the UI event and a matching state associated with the UI, providing the alternative UI event such that the UI is modified.

Abstract: A receiving apparatus includes a receiving unit that receives a plurality of packets of content data from a transmitting apparatus and also receives, from the transmitting apparatus, recovery data for each group including a plurality of packets that belong to the plurality of packets of content data and that are a predetermined number of packets apart from each other in position in transmission order so that when a packet in the group is not correctly received (not-correctly-received packet), the recovery data is used to recover the not-correctly-received packet; and a determination unit that determines, before the recovery data is received, whether packets have been correctly received that are necessary to recover the not-correctly-received packet by using correctly received packets of content data and the recovery data in a case where the recovery data is correctly received.

Abstract: Some embodiments of the invention provide techniques whereby a user may perform a system reset (e.g., to address system performance and/or reliability degradation, such as which may be caused by unused applications that unnecessarily consume system resources, an attempted un-install of an application that left remnants of the application behind, and/or other causes). In some embodiments, performing a system reset replaces a first instance of an operating system on the system with a new instance of the operating system, and removes any applications installed on the system, without disturbing the user's data.

Abstract: A mobile device includes a NOR flash memory for storing settings of the mobile device, a NOR flash memory controller having a memory storing data and/or program code for controlling operations of the NOR flash memory; and a processor coupled to the memory and the NOR flash memory for executing the program code. The program code when executed by the processor causes the memory controller to sequentially write to a sequentially first block of each sector of the NOR flash memory, then write to a sequentially second block of each sector of the NOR flash memory, and when all blocks of all sectors of the NOR flash memory have been written, the memory controller erases a sequentially first sector and then writes to the sequentially first block of the sequentially first sector.

Abstract: Embodiments that generate checkpoint images of an application for use as warm standby are contemplated. The embodiments may monitor accesses of external references by threads. An external reference may comprise a connection or use of services of an entity that is external to the set of processes that constitute the application, to which a process of the application attempts to connect by means of a socket or inter-process communication (IPC). Various embodiments comprise two or more computing devices, such as two or more servers. One of the computing devices may generate a checkpoint image of an application at a suitable point in time during initialization, when the state of the application is not yet dependent on interactions with external references. The second computing device may preload checkpoint image for the application and activate the checkpoint images when needed, following the specific resource management rules of the distributed subsystem.

Abstract: An approach to detection and repair of application level semantic errors in deployed software includes inferring aspects of correct operation of a program. For instance, a suite of examples of operations that are known or assumed to be correct are used to infer correct operation. Further operation of the program can be compared to results found during correct operation and the logic of the program can be augmented to ensure that aspects of further examples of operation of the program are sufficiently similar to the examples in the correct suite. In some examples, the similarity is based on identifying invariants that are satisfied at certain points in the program execution, and augmenting (e.g., “patching”) the logic includes adding tests to confirm that the invariants are satisfied in the new examples. In some examples, the logic invokes an automatic or semi-automatic error handling procedure if the test is not satisfied.

Abstract: Reducing application downtime during failover including identifying a critical line in the startup of an application, the critical line comprising the point in the startup of the application in which the application begins to use dependent resources; checkpointing the application at the critical line of startup; identifying a failure in the application; and restarting the application from the checkpointed application at the critical line.

Abstract: A method, computer readable medium and apparatus for performing session establishment management. For example, the method detects an evolved packet system establishment success rate that is measured over a predefined period of time falling below a predefined threshold, and performs, via a rule management server, an analysis on a bearer portion. The method then associates, via the rule management server, a root cause that contributed to the evolved packet system establishment success rate falling below the predefined threshold.

Abstract: A data receiving device includes a receiving unit, an inverse conversion unit and an error correction unit. The receiving unit receives converted data, which is obtained by converting data including transfer data of a plurality of bits, and an error detection code for error detection of the transfer data, according to a predetermined first procedure. The inverse conversion unit inversely converts the received converted data according to a predetermined second procedure. If it is impossible for the inverse conversion unit to inversely convert the converted data, if it is possible for the inverse conversion unit to inversely convert inverted data obtained by inverting a portion of the bits of the converted data, and if an error is not detected in data obtained by inversely converting the inverted data based on the error detection code, the error correction unit performs error correction by inversely converting the inverted data.

Abstract: A method of achieving fault tolerance in a distributed stream processing system organized as a directed acyclic graph includes the initial step of managing a stream process within the distributed stream processing system including one or more operators. The one or more operators of the stream process are communicatively associated with one or more downstream operators. The method includes the steps of maintaining one or more data copies of a processing state of the one or more operators until the one or more data copies can be safely discarded, notifying the one or more operators when it is safe to discard at least one of the at least one of the one or more data copies of the processing state; and using an identifier to denote the data copy of the processing state to be safely discarded.

Abstract: A decoder and method of decoding a sub-band coded digital audio signal. The decoder comprises: an input, for receiving sub-band coefficients for a plurality of sub-bands of the audio signal; an error detection unit (20), adapted to analyze the content of a sequence of coefficients in one of the sub-bands, to derive for each coefficient an indication of whether the coefficient has been corrupted by an error of a predefined type; an error masking unit (30), adapted to generate from the sequence a modified sequence of coefficients for the sub-band, wherein errors of the predefined type are attenuated; a coefficient combination unit (40), adapted to combine the received coefficients and the modified coefficients, in dependence upon the indication of error; and a signal reconstruction unit (50), adapted to reconstruct the audio signal using the combined coefficients.

Abstract: A computer platform provides a method and system for establishing scenarios for interactions between users (both individually and as a group) and a web site or other software application over a network. The interactions are described in terms of events, actions, and conditions, where a single mechanism may be used to describe events, actions, and conditions for both individuals and a group. One portion of a scenario may apply to the group, while another portion applies to individuals. Time elements and branches also can be employed to describe the scenario. The scenario may describe a non-deterministic process, but be modeled as a deterministic state machine for execution.

Abstract: A network device for building up a network connection via a high-definition multimedia interface, includes a scrambler, a descrambler, a comparator and a control unit. The scrambler is utilized for generating a transmission signal according to a first seed. The descrambler is for decoding a receiving signal to generate a second seed. The comparator is for generating a comparing result according to the first seed and the second seed. The control unit is for controlling the network connection according to the comparing result.

Abstract: A method, including receiving, by a user space driver framework (UDF) library executing from a user space of a memory over a monolithic operating system kernel, a kernel application programming interface (API) call from a device driver executing from the user space. The UDF library then performs an operation corresponding to the kernel API call.

Abstract: A signal processing circuit includes a plurality of processing-circuit modules and a logic control circuit. The plurality of processing-circuit modules is configured to process an electrical signal. The plurality of processing-circuit modules has at least one processing parameter that is adaptively adjusted based on the electrical signal. The logic control circuit is configured to receive signals from the plurality of processing-circuit modules, validate the processing based on the received signals, and control a storage circuit to sample and store a value of the processing parameter when the processing is validated. Further, the logic control circuit is configured to control the storage circuit to maintain the value of processing parameter when the processing fails validation, and to control the storage circuit to recover the processing parameter in the plurality of processing-circuit modules to the stored value when the plurality of processing-circuit modules is disturbed by a defect.