Abstract: Memory units are accessed using address bits. The address bits used to access memory units can have various formats. The address bits to access successive locations that are to be sequentially accessed can have a reduced Hamming distance binary code format to reduce a quantity of toggling to switch from one set of address bits to another set of address bits.

Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

Abstract: A method begins by a processing module generating a transaction number and generating at least a threshold number of dispersed storage network (DSN) concurrency requests, wherein each of the at least the threshold number of DSN concurrency requests includes a header section and a payload section; each of the payload sections includes the transaction number, a last known slice revision number, and a slice name section, wherein a first slice name section of a first one of the payload sections includes one or more first slice names that includes a first slice name corresponding to a first encoded data slice of a set of encoded data slices; and a second slice name section of a second one of the payload sections includes one or more second slice names that includes a second slice name corresponding to a second encoded data slice of the set of encoded data slices.

Abstract: A method begins by a processing module dispersed storage error encoding secret data in accordance with first dispersed storage error encoding parameters to produce at least one set of encoded secret slices and dispersed storage error encoding data in accordance with second dispersed storage error encoding parameters to produce a plurality of sets of encoded data slices. The method continues with the processing module determining an inter-dispersing function for outputting the sets of encoded secret slices and the plurality of sets of encoded data slices, and for a set of the plurality of encoded data slices: identifying at least one encoded data slice of the set of encoded data slices based on the inter-dispersing function, replacing the at least one encoded data slice with at least one encoded secret slice to produce a mixed set of encoded slices, and outputting the mixed set of encoded slices.

Abstract: An example apparatus has an interface to a first memory and to a second memory. The example apparatus also has a control logic that functions to control the interface. The control logic can control the interface to write a data word to the first memory and to write an error checking and correcting (ECC) word associated with the data word to the second memory.

Abstract: A function of a software program is stored in a memory during execution in a device of the software program. A processor relocates the function in a region of the memory comprising dummy code, transforms the dummy code in a predictable manner, generates a predicted checksum for the region based on a previous checksum, generates a calculated checksum over the region, and verifies the integrity of the function by comparing the predicted checksum and the calculated checksum. Also provided are a device and a computer program product.

Abstract: Integrated circuit memory systems include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells. This modification occurs in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle.

Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

Abstract: A memory system includes a writable data memory and means for recognizing an error in a data word read out from the data memory, correcting the error, and storing the corrected data word at a new address in a free area of the data memory.