To Protect Individual Data Words Written Into, Or Read Out Of, The Addressable Memory Subsystem Of Data Processing Equipment (epo) Patents (Class 714/E11.041)
  • Publication number: 20140115427
    Abstract: A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: WESTERN DIGITAL TECHNOLOGIES, INC.
  • Publication number: 20140108869
    Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: Infineon Technologies AG
    Inventors: Simon Brewerton, Simon Cottam, Frank Hellwig
  • Publication number: 20130117603
    Abstract: The present invention is directed to a method for completing a stripe write operation in a timely fashion to a RAID drive pool which includes an abnormally slow drive. For example, the stripe write operation either completes within a required time interval, or an error is provided to the host/initiator which provides an indication to an application that the stripe write operation did not complete.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: LSI Corporation
    Inventors: Martin Jess, Kevin Kidney
  • Patent number: 8135935
    Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: March 13, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael John Haertel, R. Stephen Polzin, Andrej Kocev, Maurice Bennet Steinman
  • Publication number: 20110239091
    Abstract: A memory system according to the embodiment comprises a p-adic number converter unit operative to convert ?-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.
    Type: Application
    Filed: January 21, 2011
    Publication date: September 29, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Publication number: 20090204824
    Abstract: Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key.
    Type: Application
    Filed: December 30, 2008
    Publication date: August 13, 2009
    Inventors: Jason T. Lin, Steven S. Cheng, Shai Traister
  • Publication number: 20090193316
    Abstract: An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second data bus routing data groupings in an upper 72 bits to a second memory expander. A first memory module receives all of the data groupings in the lower 72 bits of each memory expander. A second memory module receives all of the data groupings in the upper 72 bits of each memory expander. A failure in any one or more bytes in an ECC word indicate failures in the computer memory system.
    Type: Application
    Filed: April 4, 2009
    Publication date: July 30, 2009
    Inventor: Michael Kennard Tayler