Abstract: In a communication system comprising a first network operatively coupled to a second network, wherein the first network comprises a first security edge protection proxy element operatively coupled to a second security edge protection proxy element of the second network, and wherein one of the first and second security edge protection proxy elements is a sending security edge protection proxy element and the other of the first and second security edge protection proxy elements is a receiving security edge protection proxy element, the receiving security edge protection proxy element receives a message from the sending security edge protection proxy element. The receiving security edge protection proxy element detects one or more error conditions associated with the received message. The receiving security edge protection proxy element determines one or more error handling actions to be taken in response to the one or more detected error conditions.

Abstract: According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.

Abstract: A novel and useful hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.

Abstract: Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).

Abstract: Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.

Abstract: The present invention provides a method and apparatus for blocking the operation of selected USB devices at the hardware level, while allowing the operation of selected USB devices and external USB hubs to continue to operate normally. In particular, the method provides for the restricted operation of one or a plurality of USB devices by altering one or a plurality of data fields contained within a USB transaction. An apparatus for operation of the method is also provided. Control of the use of USB storage devices is provided.

Abstract: An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.

Abstract: According to an embodiment of a controller, a bit string manipulating unit manipulates a bit string of manipulation target data based on a predetermined rule. A special data setting unit generates a magic number based on a special data setting request from a host interface, obtains an error detecting code for the magic number, and sends the magic number and the error detecting code as manipulation target data to the bit string manipulating unit to obtain a manipulated manipulation target data. The special data setting unit also extracts logical block address information from the special data setting request, and instructs an access unit to write the magic number in the manipulated manipulation target data to a user data storage area and to write the error detecting code in the manipulated manipulation target data to a redundant area in a storage area located by the logical block address information.

Abstract: Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected.

Abstract: A circuit for emulating bit-level erasable non-volatile memory includes an emulator that activates a first virtual sector of a bit-level programmable, block-level erasable non-volatile memory. The first virtual sector receives and stores write requests having an address and a record to be written to the received address. A linked list of records is used to store each subsequent record received in subsequent write requests having the received address. A separate thread in the linked list is maintained for each different received address. The last record subsequently received for each of the received addresses is copied to a linked list of a second virtual sector when a first operating parameter has been exceeded. The active virtual sector is deactivated and erased when the last record subsequently received for each of the received addresses in the linked list of the active virtual sector have been copied to the second virtual sector.

Abstract: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.

Abstract: An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.

Abstract: A layer-aware Forward Error Correction (FEC) encoding and decoding method for encoding and decoding an information content, an encoding apparatus, a decoding apparatus, and a system thereof are provided, wherein the information content has a plurality of layer source symbol sets. In the encoding method, source symbols of each layer are encoded into encoding symbols corresponding to the layer by using an FEC encoder. In addition, final encoding symbols of an upper layer are generated by aggregating encoding symbols of both the upper layer and a lower layer. Thereby, the layer-aware FEC encoding method can maintain the encoding/decoding dependency between different layers of data without increasing the complexity of the encoding/decoding operations.

Abstract: A method of setting a number of iteration counts of iterative decoding, and an apparatus and method of iterative decoding. The iterative decoder including a signal-to-noise ratio (SNR) estimation unit that estimates an SNR of a received signal, an iterative decoding count setting unit that sets a minimum number of iteration counts for the received signal based on the estimated SNR, and a decoding unit that iteratively decodes the received signal using tentative decoding and error check, and selectively performs the error check based on the minimum number of iteration counts.

Abstract: Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines; and a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines.

Abstract: The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits.

Abstract: An information bit and a redundant bit at addresses of memory determined by a random number are both read without receiving error detection or error correction, the bit at a bit position determined by a random number is inverted, and the bit-inverted data is written to the same address of the same memory. The number of bits (one bit, two or more bits, etc.) to be inverted is set appropriately on the basis of what types of errors are to be caused in a simulated manner.

Abstract: A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping.

Abstract: To feedback MIMO channel conditions, a codeword from a codebook is selected. To reduce signalling, the codewords are organized into codeword subsets. The receiver signals an index of a codeword into a current 5 codeword subset previously made known to the transmitter. The current codeword subset is adaptively selected based on a threshold criterion. For example, if the best codeword from the current codeword subset is not sufficiently similar to the best codeword in the full codebook, a switch in the codeword subset is made.

Abstract: In an embodiment, regarding an addition of a kb-bit number A and a b-bit random number r, element data of a pre-calculated table C? is set based on a sum AH+rH of a value AH of upper b/2 bits of a number A2, which is lower b bits of the number A, and a value rH of upper b/2 bits of the random number r and the sum AL+rL of a value AL of lower b/2 bits of the number A2 and a value rL of lower b/2 bits of the random number r in such a way that presence/absence of carrying-over of A2+r is indicated. Accordingly, the size of the pre-calculated table needed to be reduced for obtaining an addition result of upper (k?1)b bits by mutually adding the kb-bit number A and the b-bit number r.

Abstract: A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.

Abstract: A method, a memory controller and a processor architecture for protecting an application in a memory are disclosed. The application is cached as memory lines according to a size of a cache line. For example, the method comprises: in response to a load access request from a processor, reading from the memory a flagged memory line and an ECC checksum corresponding to the memory line, wherein the flagged memory line is obtained by performing a logic operation on a predetermined bit of the memory line and a flag bit for identifying the memory line; performing an ECC check on the flagged memory line by using the ECC checksum to obtain a value of the flag bit of the memory line; restoring the flagged memory line to the memory line according to the value of the flag bit; and determining whether or not to load the memory line according to the value of the flag bit and the type of the load access request from the processor.

Abstract: A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit.

Abstract: Methods and apparatus are provided for recording input data in q-level cells of solid-state memory (2), where q>2. Input data words are encoded as respective codewords, each having a plurality of symbols. The coding scheme is such that each symbol can take one of q values corresponding to respective predetermined levels of the q-level cells, and each of the possible input data words is encoded as a codeword with a unique sequence of relative symbol values. The symbols of each codeword are then recorded in respective cells of the solid-state memory by setting each cell to the level corresponding to the recorded symbol value. Input data is thus effectively encoded in the relative positions of cell levels, providing resistance to certain effects of drift noise.

Abstract: A solid-state mass storage device and method for its operation that includes performing preemptive scrubbing of data during offline periods or disconnects from a host system to which the mass storage device is attached. The device includes a system interface adapted to connect the drive to a host system, at least one nonvolatile memory device, controller means through which data pass when being written to and read from the memory device, a volatile memory cache, a system logic device, and an integrated power source for powering the drive. The system logic device is configured to operate when the drive is not functionally connected to a host system, execute copy commands without accessing a host system, and prioritize preemptive scrubbing of addresses in the memory device on the basis of risk of data loss based on one or more parameters logged by the internal system logic device.

Abstract: A method is described for packing variable-length entropy coded data into a fixed rate data stream along with resolution enhancement data, the method providing tightly constrained propagation of transmission channel errors and graceful degradation of signal resolution as entropy-coded data rate increases. An application to a multiband ADPCM audio codec is also described.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined.

Abstract: Methods and apparatus for early stop algorithm of turbo decoding are disclosed. An example method comprises of combination of comparing of hard decisions of soft outputs of the current iteration and the previous iteration and comparing the minimum log likelihood results against a threshold. The decoding iteration is stopped once the hard decisions are matched and the minimum soft decoding result exceeds a threshold.

Abstract: Apparatuses and methods are provided for generating a plurality of redundancy versions using various rate matching algorithms. In some embodiments, a rate matcher is provided that allocates systematic and parity bits to the redundancy versions in a manner that allows all, of these bits to be transmitted in at least one redundancy version. In some embodiments, the rate matcher uses a first puncturing algorithm to generate both a first redundancy version and a third redundancy version, but allocates a different proportion of the systematic bits to these redundancy versions. In these embodiments, the second redundancy version may include only bits that were not transmitted in the first redundancy version.

Abstract: Apparatuses and methods are provided for generating a plurality of redundancy versions using various rate matching algorithms. In some embodiments, a rate matcher is provided that allocates systematic and parity bits to the redundancy versions in a manner that allows all of these bits to be transmitted in at least one redundancy version. In some embodiments, the rate matcher uses a first puncturing algorithm to generate both a first redundancy version and a third redundancy version, but allocates a different proportion of the systematic bits to these redundancy versions. In these embodiments, the second redundancy version may include only bits that were not transmitted in the first redundancy version.

Abstract: A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.

Abstract: Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (?) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(?)) values and check edge message/intrinsic information (?) values for their respective updating in successive decoding iterations.

Abstract: A computer program product, apparatus, and method for handling exception condition feedback at a channel subsystem of an I/O processing system using data from a control unit are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes sending a command message to the control unit, and receiving a response message in response to the command message. The response message includes exception condition feedback identifying a termination reason code in response to unsuccessful execution of at least one command in the command message. The method also includes interrupting a CPU in the I/O processing system, and reporting status associated with the exception condition feedback to the CPU in an interrupt response block.

Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

Abstract: A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).

Abstract: A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g.

Abstract: A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.