Abstract: Operations to recognize clock ports within a simulation circuit component and/or recognize a clock signal within simulation waveforms are described. One or more of the operations include generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component. The operations also include calculating a correlation vector based on bit sequences in the input values and bit sequences in the output values. The first input port is determined to be a clock port by applying a machine learning model to the correlation vector.

Abstract: Methods and systems for managing data collection throughout a distributed environment are disclosed. To manage data collection, a system may include a data aggregator and a data collector. The data collector may utilize a consensus sequence to generate reduced-size data transmissions. The consensus sequence may be made up of patterns of data that occur frequently in data collected by the data collector. Therefore, data collected by the data collector may be condensed by replacing segments of the data with pointer pairs, pointer pairs being indicators of a portion of the consensus sequence that matches a segments of data. The data collector may transmit these pointer pairs, along with any additional segments of data, to the data aggregator instead of transmitting full data sets. The data aggregator may reconstruct data from the data collectors using the reduced-size data and the consensus sequence.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

Abstract: A memory system includes a writable data memory and means for recognizing an error in a data word read out from the data memory, correcting the error, and storing the corrected data word at a new address in a free area of the data memory.