Simple Parity (epo) Patents (Class 714/E11.047)
  • Patent number: 11557365
    Abstract: Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 8352363
    Abstract: A mainframe-based far-distance bicentric transaction information processing system, providing a processing operation solution. The method includes: receiving upload transaction information containing transaction type data; searching transaction information requiring an amount of shared resource less than a preset threshold when being processed, according to the transaction type data; and transmitting the transaction information requiring the amount of shared resource less than the preset threshold when being processed, to a backup processing center to be processed, when CPU utilization rates exceeds a preset safety threshold. The system includes a main processing center and a backup processing center.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Bank of Communications
    Inventor: Weidong Hou
  • Publication number: 20090307566
    Abstract: An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 10, 2009
    Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Seoul National University
    Inventors: Jong Seon No, Beom Kyu Shin, Seok Il Youn, Jae Dong Yang, Jun Jin Kong, Jae Hong Kim, Yong June Kim, Kyoung Lae Cho