Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Abstract: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.

Abstract: A pattern forming method including modifying design data subjected to a first design rule check in design data of a pattern to be formed in a semiconductor substrate, performing the first design rule check to the modified design data again, outputting the modified design data which does not violate the first design rule as pattern forming design data used in actual pattern formation, and performing a second design rule check having an allowable range wider than that of the first design rule to the modified design data which violates the first design rule, and outputting the modified design data which does not violate the second design rule as the pattern forming design data, and redesigning the pattern to satisfy the second design rule or adjusting the modification guideline such that the modified design data which violates the second design rule satisfies the second design rule.

Abstract: An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design.

Abstract: The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout.

Abstract: A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.

Abstract: Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators.

Abstract: Some embodiments of the present invention provide systems and techniques for checking a livelock in a circuit design. During operation, the system can identify a finite state machine (FSM) in the circuit design, wherein the FSM comprises a first set of state variables. The system can then construct an abstract machine of the circuit design, wherein the abstract machine includes the FSM and a second set of state variables. Next, the system can search for one or more livelocks in the abstract machine. If a livelock is found in the abstract machine, the system can verify that the livelock is a livelock in a concrete machine of the circuit design, wherein the concrete machine includes the FSM and a third set of state variables, wherein the second set of state variables is a subset of the third set of state variables.

Abstract: Techniques and technology for formally verifying a first electronic design with a second electronic design that has been synthesized from the first electronic design, wherein the synthesis process included structural transformation operations, is provide herein. In various implementations, a first design and a second design are received. The second design having been synthesized from the first design, where no structural transformation operations were performed during synthesis of the second design. Additionally, a third design and a structural transformation guidance file are received. The third design having also been synthesized from the first design, but, where structural transformation operations were performed during synthesis of the third design. The structural transformation guidance file specifies what transformations where made during synthesis.

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.

Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.

Abstract: Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.

Abstract: During a method, a hybrid graphical user interface (GUI), which is associated with electronic-design-automation (EDA) software, is displayed. This hybrid GUI allows users to efficiently specify useful analysis equations using textual and/or graphical information. In particular, the hybrid GUI has a first window that includes graphical objects associated with a circuit design. A user can select one or more of the graphical objects and associated electrical parameters using a user-interface device, such as a mouse. The hybrid GUI has a second window that has icons and other graphical controls that allow the construction of an analysis equation using the user-interface device.

Abstract: The LSI design apparatus adds diagnostic circuitry for micro diagnosis to a behavior level description. Based on behavior level design data for a normal system of a LSI, high level synthesis generates RTL design data and register information. Based on the register information, a unique address used by a micro diagnosis program is allocated to each register. Circuit components within the normal system are grouped together. Based on the result of the address allocation and the result of the grouping, a behavior description for diagnostic circuits constituting a diagnosis system for the LSI is generated and added to the behavior level design data for the normal system, resulting in behavior level design data in which the normal and diagnosis systems are integrated together.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: A system and method for navigating drawings on a computing system is provided. The method includes loading drawings and associated object data. The drawings and the associated object data are arranged into at least two types of navigation networks, each type of navigation network having a plurality of parameters to interact with the drawings. Keys in a keyboard are mapped based on the plurality of parameters of the at least two types of navigation networks. A navigation network for the drawings is selected from the at least two types of navigation networks and the drawings are displayed. The drawings are manipulated using the mapped keys based on the selected navigation network, wherein the at least two types of networks include at least two of a row and column network, a flow chart network, a wiring diagram network, and a component location drawing navigation network.

Abstract: Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.

Abstract: A hierarchizing means 101 for blocking, of a first description which represents a functional circuit in an RTL, a second description and for converting the first description into a hierarchized third description; a first logic synthesis means 102 for logic synthesis of the third description; a first placement and routing means 103 for first placement and routing; a first substitution means 104 for substituting a fourth description indicating the unit circuit which is asynchronous for the second description; a second logic synthesis means 105 for logic synthesis of the fourth description; a second placement and routing means 106 for second placement and routing; a calculation means 107 for calculating a circuit on which the second placement and routing is performed; and a second substitution means 108 for substituting the circuit on which placement and routing is performed by the second placement and routing means 106 for a selected circuit on which placement and routing is performed by the first placement and

Abstract: A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.

Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: In a computer aided design (CAD) apparatus, an association-data acquiring unit acquires association data that defines an association between pins of a first connector and those of a second connector to be connected to the first connector, and an assignment of signals to the pins. A part-information acquiring unit acquires information including a symbol of the first connector. A layout-condition acquiring unit acquires a layout condition to lay out the symbol of the first connector on a circuit diagram. A circuit diagram creating/updating unit lays out the symbol of the first connector on the circuit diagram based on the layout condition, and adds a net name indicating a signal assigned to each of the pins to the symbol.

Abstract: A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided.

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract: Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be overlaid on top of a floorplan layout of the IC to highlight the parts of the design that may be further optimized. The visual indicator can be updated in real time to highlight the optimizations that have been achieved by the changes made to the design. The real time update of the visual indicator may allow multiple changes to be made to the design before the design is recompiled with a design program.

Abstract: The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.

Abstract: Design apparatuses according to the present embodiments each include a CDFG generator, a scheduler, a binder, a retention register selector, a control circuit generator, and an RTL description generator. The binder generates a data path circuit in which a hardware element is allocated to a CDFG after scheduling by the scheduler. The retention register selector detects, as a retention control step, one of the control steps which has a minimum number of latch bits from the CDFG after scheduling and selects, as a retention register, a register allocated to the detected retention control step. The control circuit generator generates a control circuit which performs an execution control of the data path circuit and causes a state to transition to the retention control step when a signal for power-off is enabled.

Abstract: A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.

Abstract: Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a particular circuit. The various embodiments may then implement the designed N-variants as hardware in the IC. Additional variants and embodiments may also be disclosed.

Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Abstract: A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.

Abstract: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.

Abstract: Semiconductor devices, logic devices, libraries to represent logic devices, and methods for designing and fabricating the same are disclosed. The semiconductor devices include a substrate comprising sapphire or diamond, an active layer disposed on the substrate, the active layer having a thickness tSi and comprising a channel region having a length L, where L/tSi is above 7 and an oxide layer disposed on the active layer.

Abstract: A serial communications protocol is provided that has optional link initialization features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional serial communications link features are implemented are able to perform the lane polarity reversal and lane order reversal functions. Integrated circuits in which the optional serial communications link features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.

Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty.

Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.

Abstract: A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and cannot compare differences between models created with third party design environments. The present invention increases interoperability and capabilities of existing circuit design environments, and achieves an advance in the art, by converting high level block diagram models to a user readable text-based format and performing a text-based differential analysis on the converted models to determine differences.

Abstract: A method and apparatus for improving the interconnection and multiplexing cost of circuit design from high level synthesis using ant colony optimization is described. In one example, a plurality of hardware components for performing an operation is represented with a data flow graph having edges and nodes. A plurality of solutions are simulated for performing the operation as hardware component and schedule combinations represented as paths on the data flow graph. For each solution, cost including a number of edges and nodes traversed on the data flow graph and an interconnection cost related to the number of different hardware components in the path is determined. A pheromone trail is associated with each path, the pheromone trail including a cost of the respective scheduling solution, and a solution is selected with the highest value pheromone trail as a hardware component and schedule combination for a circuit.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.

Abstract: Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.

Abstract: A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module, and receiving a user input selecting a plurality of ports of the module for inclusion in an interface through which the module communicates with the circuit design. Responsive to a user input specifying an interface type, the interface type can be associated with the plurality of ports. The interface type can be associated with a port list including standardized ports. Individual ones of the plurality of ports can be automatically matched with standardized ports from the port list. A programmatic interface description specifying the interface for the module can be output.

Abstract: Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.

Abstract: An electronic device and method for inspecting electrical rules of circuit boards includes selecting at least two design files that record electrical rules of the circuit boards and searching the electrical rules in the selected design files using preset parameter keywords. Same electrical rules of the selected design files are acquired by comparing the electrical rules in the selected design files. The same electrical rules and corresponding parameter values are input to a comparison table, and the comparison table is output.