Design Entry Patents (Class 716/102)
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Patent number: 7984400Abstract: Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.Type: GrantFiled: May 8, 2008Date of Patent: July 19, 2011Assignee: Synopsys, Inc.Inventors: Richard C. Maixner, Mario Larouche, Chun Kit Ng, Kenneth S. McElvain
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Publication number: 20110173580Abstract: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.Type: ApplicationFiled: March 21, 2011Publication date: July 14, 2011Applicant: Synopsys, Inc.Inventor: Harold J. Levy
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Patent number: 7979816Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.Type: GrantFiled: April 9, 2008Date of Patent: July 12, 2011Assignee: Xilinx, Inc.Inventors: Arne S. Barras, Rajeev Jayaraman
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Publication number: 20110161896Abstract: In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert Robison, Yun Shi, William R. Tonti
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Publication number: 20110161897Abstract: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: SYNOPSYS, INC.Inventors: Guillermo Maturana, Arturo Salz, Joseph T. Buck
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Publication number: 20110145770Abstract: An electronic design automation process, such as a layout-verses-schematic analysis process, may recognize a representation of a device from physical layout design data. Information, such as geometric information separately obtained from the physical layout design data, is then associated with the recognized device representation. The associated information can subsequently be used in a later electronic design automation operation involving the recognized device representation.Type: ApplicationFiled: May 14, 2010Publication date: June 16, 2011Inventors: Phillip A. Brooks, Fedor G. Pikus
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Patent number: 7962872Abstract: An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two different models of the same circuit block and performing timing analysis based on the optimized model. In an embodiment, the two models correspond to black box and interface timing models. In the optimized model, ports for which only timing arc information is deemed necessary are modeled using corresponding information from the black box model, while ports for which more accurate or detailed information is deemed necessary are modeled using corresponding information from the interface timing model. The optimized model enables the integration to be performed with a balance of resource requirements and accuracy.Type: GrantFiled: November 21, 2008Date of Patent: June 14, 2011Assignee: Texas Instruments IncorporatedInventors: Arun Koithyar, Venkatraman Ramakrishnan
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Patent number: 7957150Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.Type: GrantFiled: January 29, 2009Date of Patent: June 7, 2011Assignee: Hitachi, Ltd.Inventors: Hideki Osaka, Yutaka Uematsu
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Patent number: 7949986Abstract: A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.Type: GrantFiled: June 23, 2008Date of Patent: May 24, 2011Assignee: LSI CorporationInventor: Judy Gehman
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Publication number: 20110119646Abstract: This invention concerns an automated method of generating a design for an I/O fabric of a target integrated circuit having a core and pins. A process tool executes algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language. It imports integrated circuit design data, and from it captures I/O specification data for a circuit core, library of cells, pin, I/O control, BSR and I/O cell chaining, and die. The tool validates the specification data, and generates the I/O fabric design by configuring and inter-connecting a pin multiplexing and control matrix structures according to constraints for signal control, and timing. The structures includes on both the input and output paths of each pin a functional multiplexer matrix structure, a test multiplexer matrix structure, an override matrix structure, a multiplex select and control matrix structure, and an I/O Cell control logic.Type: ApplicationFiled: November 18, 2010Publication date: May 19, 2011Inventors: David Murray, Sean Boylan
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Publication number: 20110119645Abstract: A disclosed device includes a verification unit which performs a data verification of chip design data, an obtaining unit which obtains encryption IP and a verification result output unit which outputs a result of the data verification. The chip design data is designed by using the box IP, the box IP being data which can be disclosed to a chip designer in hardware IP. The encryption IP is the IP including part or all of data of the hardware IP being encrypted. The verification unit decrypts the encryption IP to the hardware IP and replaces the box IP of the chip design data with the decrypted hardware IP so as to perform the data verification, in the storage area such as RAM where storage data is hidden from outside.Type: ApplicationFiled: October 28, 2010Publication date: May 19, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Ryoji KOIZUMI
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Patent number: 7945890Abstract: A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element.Type: GrantFiled: October 31, 2007Date of Patent: May 17, 2011Assignee: Cadence Design Systems, Inc.Inventors: Regis Colwell, Gilles S. C. Lamant, Alisa Yurovsky, Timothy Rosek
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Publication number: 20110113392Abstract: One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory.Type: ApplicationFiled: November 9, 2010Publication date: May 12, 2011Inventors: RAJAT SUBHRA CHAKRABORTY, Seetharam Narasimhan, Swarup Bhunia
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Patent number: 7941768Abstract: A method, system, and related computer program products for computer simulation of a photolithographic process is described. In one embodiment, a method for designing an integrated circuit is provided. The geometrical design intent and process condition values are received for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit. The photolithographic process is simulated at the process condition values using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results.Type: GrantFiled: February 20, 2007Date of Patent: May 10, 2011Assignee: oLambda, Inc.Inventor: Haiqing Wei
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Patent number: 7941771Abstract: A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.Type: GrantFiled: June 4, 2008Date of Patent: May 10, 2011Assignee: Bull S.A.Inventors: Anne Kaszynski, Jacques Abily
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Patent number: 7941295Abstract: Provided is a manufacturing apparatus for appropriately managing information about parts of the manufacturing apparatus.Type: GrantFiled: February 5, 2009Date of Patent: May 10, 2011Assignee: Tokyo Electron LimitedInventors: Hiroshi Shimatani, Noriaki Shioyama
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Patent number: 7930666Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.Type: GrantFiled: December 12, 2006Date of Patent: April 19, 2011Assignee: Tabula, Inc.Inventors: Herman Schmit, Daniel J. Pugh, Steven Teig
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Patent number: 7921389Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.Type: GrantFiled: June 25, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Wolfgang Roesner, Derek Edward Williams
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Publication number: 20110078640Abstract: The invention relates to a method and a tool for generating a parameterized configuration for a Field Programmable Gate Array from a Boolean function, the Boolean function comprising at least one parameter argument, comprising the steps generating at least one tunable logic block from the Boolean function and from at least one parameter argument, and mapping the at least one tunable logic block to the Field Programmable Gate Array. This is advantageous since a parameterized configuration can be generated faster than with conventional tools.Type: ApplicationFiled: May 15, 2009Publication date: March 31, 2011Inventor: Karel Bruneel
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Patent number: 7913213Abstract: A design tool for automatically identifying minimum timing violation corrections in an integrated circuit (IC) design includes program instructions executable by a processor to identify locations to add a delay along each circuit path having a minimum timing violation. The tool may also sequentially try each of a plurality of circuit changes that add the delay and to evaluate a result of each circuit change until an acceptable percentage of the minimum timing violation has been corrected. In response to each circuit change, the design tool may update an internal node report, which includes a listing of circuit nodes and a maximum timing slack available at each node, by reducing a maximum slack value of each affected node by an amount of the added delay. The design tool may generate an output report that includes a listing of the circuit changes which correct the minimum timing violations.Type: GrantFiled: April 10, 2008Date of Patent: March 22, 2011Assignee: Oracle America, Inc.Inventor: Richard W. Smith
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Patent number: 7913217Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.Type: GrantFiled: September 18, 2008Date of Patent: March 22, 2011Assignee: Xilinx, Inc.Inventors: Alexander Carreira, Alexander R. Vogenthaler
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Patent number: 7908577Abstract: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.Type: GrantFiled: July 9, 2008Date of Patent: March 15, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takehiko Tsuchiya
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Patent number: 7895550Abstract: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured.Type: GrantFiled: April 16, 2008Date of Patent: February 22, 2011Assignee: LSI CorporationInventors: John Q. Walker, Jeffrey P. Burleson, Scott A. Service, Steven L. Howard
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Publication number: 20110025435Abstract: Pins on an RFIC package carry RF signals between the package and a PCB. A first capacitor is coupled between a selected pin of the RFIC package near the pins carrying the RF signals and a radio-frequency ground on the PCB. A coupling between the RFIC package and the PCB is modeled, and includes modeling of the pins of interest and at least one parasitic element of the coupling. A capacitance of the first capacitor is selected based on the modeling to obtain desired performance at selected operational frequencies. A second capacitor may be coupled between the selected pin a radio frequency ground of the RFIC package. An inductor may be coupled in parallel across the first capacitor.Type: ApplicationFiled: December 30, 2009Publication date: February 3, 2011Applicant: STMICROELECTRONICS LTD.Inventor: Oleksandr Gorbachov
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Publication number: 20110029942Abstract: A method for implementing soft constraints in scheduling comprises receiving a description of circuit behavior. The description is un-timed. A scheduling solution is generated for use in scheduling the description. The scheduling solution includes scheduling variables and an objective function. The scheduling variables schedule the time of at least one operation. The objective function includes a penalty term and constraints comprising at least one hard constraint and at least one soft constraint. The constraints are created on the scheduling variables. The penalty term comprises a slack variable representing violations of the constraints. The penalty term measures the design cost of violating the soft constraint. Following generation of the scheduling solution, the description is scheduled by applying the scheduling solution to the description. Timing information of the description is provided as an output of the scheduling.Type: ApplicationFiled: July 28, 2010Publication date: February 3, 2011Inventors: Bin LIU, Zhiru ZHANG, Jason CONG
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Publication number: 20100333050Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: ApplicationFiled: August 31, 2010Publication date: December 30, 2010Applicant: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Publication number: 20100313174Abstract: Systems and methods for improving a PN ratio of a logic gate by adding a non-switching transistor. In one embodiment, the logic gate includes a plurality of PMOS switching transistors and a plurality of NMOS switching transistors that are switched on and off by received input signals. The PMOS and NMOS switching transistors are interconnected to perform a logic operation on the input signals and produce a corresponding output signal. The non-switching transistor is inserted in the circuit to improve the ratio of PMOS and NMOS transistors between the power nodes of the logic gate. The non-switching transistor is either a PMOS transistor or an NMOS transistor as needed to make the PN ratio closer to 1. The non-switching transistor is biased to keep it switched on and does not affect the logic functions of the gate.Type: ApplicationFiled: August 18, 2010Publication date: December 9, 2010Inventor: Fumihiro Kono