Abstract: In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.

Abstract: A simulation method and device, a power wire topology network, and a test circuit involve: a power wire topology network is generated according to a power wire layout, the power wire topology network including a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, the parasitic element being located between the two power child nodes; a minimum voltage of the power input node of each circuit nodule in a circuit corresponding to the power wire topology network is determined, the power input node being one of the power child nodes in each circuit module; and a time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of an integrated circuit.

Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

Abstract: Disclosed is a method of evaluating placement of semiconductor devices performed by a computing device according to an exemplary embodiment of the present disclosure. The method includes receiving connection information representing a connection relationship between semiconductor devices; clustering the semiconductor devices based on the connection information; and determining a reward to train a neural network model based on clustering.

Abstract: Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

Abstract: Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method includes identifying candidate nets within a netlist. A bounding box that includes one or more nets of the candidate nets is determined. Once the bounding box is determined, the orientation of the box is determined and used to determine a pattern of bumps within the bounding box. Finally, a subchannel is generated based on the pattern of bumps.

Abstract: The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based upon the line segments and assigning random layer information to each of the line segments. Embodiments may further include performing crossover and mutation operations to the line segments using hyperparameters and evaluating a fitness of the line segments. Embodiments may also include instantiating vias based upon a layer to which the line segment was assigned.

Abstract: Filters 10 and 20 having respective pass bands different from each other, a common terminal to which a terminal 11 of the filter 10 and a terminal of the filter 20 are connected, and an inductor of which one end is connected to the terminal 11 and another end is connected to the common terminal. The filter 10 includes a longitudinally coupled resonator formed of a resonator 132 and resonators 131 and 133 disposed on both sides of the resonator 132, in which the resonator 132 is connected to the terminal 11, and a parallel resonator of which one end is connected to the resonator 132 and another end is connected to a ground electrode, and the resonator 132 and the parallel resonator of the resonators included in the filter 10 are connected to a signal path between the resonator 132 and the terminal 11.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Abstract: A computerized method of assigning a building automation system point type to a plurality of unclassified data points is provided. The method includes receiving unclassified data points and attributes for each data point. The method includes receiving classifications for a first subset of the unclassified data points. Each classification associates a data point with a building automation system point type. The method includes generating a term set containing substrings that appear in the attributes. The method includes generating a first matrix describing a frequency that the substrings appear in the attributes. The method includes calculating an indicator of a probability that the presence of the selected substring results in the data point belonging to the selected point type. The method includes assigning a point type to a second subset by finding the substring and potential point type pair having the greatest indication of probability.

Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.

Abstract: A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.

Abstract: A static safety analysis for control-flow linearization receives a control flow graph (CFG) and an intermediate representation of a computer program, and identifies, for a given loop, all memory load instructions belonging to one side of a diamond-shape structure in the CFG. For each representation of an address of each memory load instruction identified, determining whether it is used on all other sides of the diamond-shape structure. Responsive to determining each representation of an address of each memory load instruction on the one side of the diamond-shape structure is used on all other sides of the diamond-shape structure, determining whether an immediate predecessor of a top of the diamond-shape structure for the given loop post-dominates a header of the given loop. Responsive to determining the immediate predecessor of the top of the diamond-shape structure for the given loop post-dominates the header of the given loop, affirming safety of linearization.

Abstract: Auditing information is captured from a processing stack of an invoked application. An annotation customized for that invocation context is processed to filter and/or add additional audition information available from the processing stack. The customized auditing information is then sent to a destination based on a processing context of the invoked application when the invoked application completes processing. In an embodiment, the customized auditing information is housed in a data store and an interface is provided for customized query processing, report processing, event processing, a notification processing.

Abstract: Various methods, apparatuses/systems, and media for application of an N-dimensional hypercube datatype for automatically generating a data structure are provided. A database stores a plurality of data each associated with a corresponding application and each including metadata describing information about the data. A processor creates taxonomies describing data concepts associated with the metadata and store the taxonomies onto the database; receive the metadata and the taxonomies from the database via a communication network; automatically generate a cube set including a set of N-dimensional hypercubes from the received metadata to represent the metadata describing the information about the data; automatically generate a map from the cube set to express data quality checks and rules that apply to nodes in the map; and apply the data quality checks and rules to the received metadata to automatically generate a data structure.

Abstract: A method, apparatus, and system for controlling an aircraft. A target state for the aircraft is identified. A current mission state is determined for the aircraft. A sequence of actions is selected from a pool of potential actions to reach the target state from the current mission state for the aircraft. The sequence of actions is selected based on the current mission state. The actions in the sequence of actions for which preconditions for the actions that have been met are performed. The actions are performed in an order defined by the sequence of actions.

Abstract: An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.

Abstract: The present disclosure relates to a system and method for assertion-based formal verification in an electronic design environment. Embodiments may include executing, using a processor, an assertion-based formal verification proof process on a model of an electronic design and analyzing a first property associated with the model. Embodiments may further include generating at least one trace of the first property and determining a mapping function associated with the first property. Embodiments may also include storing the at least one trace and the mapping function. Embodiments may further include determining that a second property associated with the model shares a cone of influence with the first property and generating a new trace based upon, at least in part, the mapping function.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include identifying a plurality of higher level instances along an electronic design path from a source to a destination. Embodiments may further include analyzing inter-instance path information associated with the plurality of higher level instances included in the electronic design path from source to destination. Analyzing may include ignoring information included within the plurality of higher level instances. Embodiments may further include determining, based upon, at least in part, inter-instance path information whether data is unable to propagate from the source to the destination.

Abstract: Techniques for determining simulations to confirm programmatic logic are discussed herein. Such simulations may be used to identify errors in programmatic logic. As an example, a system may simulate an autonomous vehicle operating in an environment by setting various initialization parameters. Temporal logic, such as Linear Temporal Logic (LTL) and/or Signal Temporal Logic (STL) may be used to determine a numeric cost associated with how closely one or more policies are violated for each simulation of a group of simulations. Based on the costs computed, additional sets of simulations may be created using an evolutionary algorithm. Flaws in programmatic logic controlling the system may be identified based on the evolutionary algorithms and cost defined.

Abstract: A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least in part on a quantity of loop breakers n characterizing the acyclic emulation, wherein the loop detector emulation comprises at least one of an oscillation detector or a state-holding detector; and executes the loop detector emulation for a plurality of input values for the emulated circuit to generate an output indicating at least one of an oscillation status or a state-holding status of the emulated circuit.

Abstract: Described is a method for drafting and displaying electrical circuits based on libraries containing items or speech codes corresponding to the various types of electrical components, the items are made up of alphanumeric codes through which it is possible to unequivocally identify each single electrical component and the method comprises the steps of viewing on a PC screen a control unit of the electrical circuit in the middle of a work area, viewing on the PC screen further electrical components, connected directly or indirectly to the control unit, around the above-mentioned control unit, grouping the views according to a level structure, where each level represents a component or device and contains a structure of sub-levels, setting and grouping a plurality of components or devices which have to be highlighted with respect to others, through graphic animations on the PC screen.

Abstract: Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.

Abstract: A method of generating images from Register Transfer Level (RTL) code for clone detection or code verification is provided. The method includes obtaining a first RTL code, extracting first RTL constructs from the first RTL code, generating a first array from the extracted first RTL constructs, generating a first RTL image representation (RIR) image from the generated first array, wherein color in the first RIR image corresponds to values included in the first array, comparing the generated first RIR image to other RIR images to find a portion of an RIR image that matches at least a portion of the generated first RIR image, and determining that the portion of the first RTL code is validated as a result of finding the portion of the RIR image that matches the portion of the generated first RIR images.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN) as well as different versions of a feature dictionary. In the system, encoded inputs for the ANN can be decoded by the feature dictionary, which allows for encoded input to be sent to a master version of the ANN over a network instead of an original version of the input which usually includes more data than the encoded input. Thus, by using the feature dictionary for training of a master ANN there can be reduction of data transmission.

Abstract: An asynchronous switching system and method for processing SDI data streams, the system and method utilizing one or more buffers for cleaning up an output of a dirty IP switch.

Abstract: Methods, systems, and apparatus for propagating reduced-precision on computation graphs are described. In one aspect, a method includes receiving data specifying a directed graph that includes operators for a program. The operators include first operators that each represent a numerical operation performed on numerical values having a first level of precision and second operators that each represent a numerical operation performed on numerical values having a second level of precision. One or more downstream operators are identified for a first operator. A determination is made whether each downstream operator represents a numerical operation that is performed on input values having the second level of precision. Whenever each downstream operator represents a numerical operation that is performed on input values having the second level of precision, a precision of numerical values output by the operation represented by the first operator is adjusted to the second level of precision.

Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

Abstract: The disclosed technology includes, among other innovations, a framework for resource efficient compilation of higher-level programs into lower-level reversible circuits. In particular embodiments, the disclosed technology reduces the memory footprint of a reversible network implemented in a quantum computer and generated from a higher-level program. Such a reduced-memory footprint is desirable in that it addresses the limited availability of qubits available in many target quantum computer architectures.

Abstract: Refining multi-bit flip flops mapping without explicit de-banking and re-banking is provided by identifying a set of equivalent flops in a layout, that include a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; and remapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the first location.

Abstract: A method for automatic detection of a functional primitive in a model of a hardware system, the model being a netlist having cells and net links therebetween, comprising the steps: a) mapping the cells to target nodes, each of which having a target node type, and the net links to edges of a target graph, and mapping the functional primitive to a search pattern having search nodes and connections therebetween; b) selecting candidates from those target nodes the target node types of which match a search node type, and selecting a candidate structure from those selected candidates the target nodes and edges of which match the search nodes and connections of the search pattern; c) reverse-mapping the target nodes and edges of the selected candidate structure to the cells and net links of the netlist; and d) outputting said cells and net links as detected functional primitive.

Abstract: Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.

Abstract: A method is disclosed herein. The method includes: adjusting first parameters associated with parameterized cells in a netlist of an integrated circuit (IC) to generate second parameters associated with the parameterized cells in the netlist of the IC; updating the netlist of the IC according to the second parameters; and performing a simulation according to the netlist.

Abstract: Embodiments of the invention disclosed herein provide techniques for generating an alternative design recommendation. The techniques include determining, via a processor, a first function associated with one or more first components included in a first design. The techniques further include analyzing, via the processor, a plurality of components included in a database to select one or more second components associated with a second function that corresponds to the first function. The techniques further include causing an alternative design recommendation that includes the one or more second components to be output for display.

Abstract: Methods and apparatus for increasing the random logic utilization on a programmable device are provided. Although not completely homogeneous, the programmable device has many components that are repeated many times in an array. To help improve repeatability and packing, computer-aided design tools for compiling a circuit design for the programmable device may first lock down a synthesis cell netlist with stable naming, create location solution files (files with desired clustering granularity for stabilizing performance and reducing compile times) for selected regions of interest on the programmable device, and compose a final design with only the best solutions some of which can be imported from one location to another. Compiling a design in this way can help improve random logic utilization beyond 85% while improving circuit performance by 20% or more.

Abstract: A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.

Abstract: A method, system and computer program product, the method comprising: obtaining circuit information, comprising description of groups of pins of electronic chips; obtaining a description of a test comprising a plurality of rules specifying: an identifier, a first group of pins, a second group of pins, a first action to take upon successful interconnection of the first and second groups, and a second action to take upon failure, wherein the first action and second actions are one of: finish with success, finish with failure, and a rule ID of a subsequent rule to check; checking the plurality of rules, comprising checking a sequence of rules starting with a first rule, and wherein each subsequent rule is selected as the first or second action of a preceding rule, in accordance with whether the preceding rule succeeded or failed, respectively; and outputting a result of the plurality of rules.

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Abstract: A computer executable tool fixes gate-level logic simulation when unknowns (Xs) exist in nested clock gater chains to improve simulation accuracy. Due to X-pessimism in logic simulation, false Xs are generated when simulating nested clock gaters, producing incorrect simulation results. The tool analyzes the fan-in cones along a nested clock gater chain to find such false Xs. Furthermore, it generates auxiliary code to be used with logic simulation to eliminate such false Xs. Gate-level simulation can then be repaired to produce correct results for nested clock gaters.

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

Abstract: Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is determined based at least in part on the delay distribution and the residual distribution. When it is determined that that the yield loss associated with the at least one cell exceeds a yield loss threshold, the at least one cell may be identified as a candidate for replacement with a replacement cell.

Abstract: A method for analyzing a processor design includes receiving a design for a processor and receiving an application to be executed by the processor. The method includes simulating the execution of the application on the processor based on the design to identify unexercisable gates of the processor.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed or distributed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives first samples corresponding to inputs that characterize configuration of the DSN and receives second samples corresponding to outputs that characterize system behavior of the DSN. The computing device then processes the first and samples to generate a DSN model to generate predictive performance of the outputs based on various values of the inputs. In some instances, the DSN model is based on a neural network model that employs the inputs that characterize the configuration of the DSN and generates the outputs that characterize system behavior of the DSN.

Abstract: Various embodiments described herein provide for a memory sub-system read operation or a memory sub-system write operation that can be requested by a host system and involves performing a multi-level (e.g., two-level) pointer dereferencing internally within the memory sub-system. Such embodiments can at least reduce the number of read operations that a host system sends to a memory sub-system to perform a multi-level dereferencing operation.

Abstract: A non-volatile computer data storage programming system includes a scan chain modification configured to receive a default model defining a scan chain of an industry standardized device. A controller is in signal communication with the scan chain modification system, and is configured to program an industry standardized device. A non-volatile computer data storage device is configured to receive data from the industry standardized device. The scan chain modification system modifies the default model to generate a new model including a reduced scan chain, and the controller programs the industry standardized device based on the new model such that the industry standardized device is programmed with the reduced scan chain.

Abstract: A method for designing a system on a target device includes generating an intermediate representation of the system from a functional specification of a high-level description of a system. From the high-level description of the system, one or more directives are identified that (1) transform a portion of the system with a specific technique, (2) build a spatial layout for the system by dividing the system according to functionalities, and (3) specialize the system in response to the spatial layout. The intermediate representation of the system is modified in response to the one or more directives.

Abstract: Concepts, systems and methods are described for generating a quantum circuit from a Unitary Coupled Cluster (UCC) ansatz which represents the excitation of a reference state by a parameterised operator including excitation operators. The UCC ansatz includes multi-qubit Pauli operators, referred to as Pauli strings, determined from each excitation operator. The method comprises partitioning the Pauli strings into mutually commuting sets and sequencing the Pauli strings by set. Pauli gadgets are then generated from the Pauli strings by Trotterization, the Pauli gadgets having the same sequencing by set as the Pauli strings. Each set of Pauli gadgets is diagonalised to convert the Pauli gadgets into phase gadgets which are then transformed into one- and two-qubit native gates to generate the quantum circuit.

Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip, the circuit design of the IC chip including a list of properties for the IC chip. The list of properties includes a list of covers for the IC chip. The formal verification engine can also execute a formal verification of the IC chip. Results of the formal verification identifies a subset of covers of the list of covers that are unreachable. The formal verification engine can further execute a root cause search for a selected cover in the subset of covers that are unreachable. The root cause search selectively adds and removes cutpoints to signals in the circuit design to identify a root cause for the selected cover being unreachable. The root cause comprises a signal in the circuit design that is upstream from the selected cover.