Abstract: A method includes converting a first threshold voltage related (VT-related) cell of a first standard cell library to a first modified VT-related cell. The first standard cell library includes the first VT-related cell and a first base cell. The first VT-related cell and the first base cell each include different portions of a layout design of a first standard cell corresponding to a first performance setting. The method includes generating a second standard cell library based on the first base cell and the first modified VT-related cell. The first modified VT-related cell and the first base cell each include different portions of a layout design of a second standard cell corresponding to a second performance setting. The method further includes generating a layout design for an integrated circuit based on the second standard cell library; and forming a set of masks based on the layout design.

Abstract: A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.

Abstract: Systems and techniques are described for designing an integrated circuit (IC). Some embodiments identify and preserve slices by using new objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such slice objects. These new objects can enable rapid access and preservation of slices, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Abstract: A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic operators; transforming the original circuit obtained from the interpreting, into a dual logic circuit enabled for a checking of contradiction in place of tautology and vice versa, by providing a set of switching rules configured to switch each respective one of the original logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into a respective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN; and complementing outputs of the original circuit by adding an INV at each output wire. The method further provides testing in parallel the satisfiability of the original logic circuit, and the satisfiability of the dual logic circuit with inverted outputs. Responsive to one of the parallel tests finishing, the other parallel test is caused to also stop.

Abstract: A communication module for controlling a motor vehicle, which is configured for receiving vehicle-independent commands and converting these received commands into a target trajectory of the motor vehicle, and transmitting this target trajectory to an implementation module which is configured for associating a sequence of control commands for components of the motor vehicle with this transmitted target trajectory.

Abstract: One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency investigator evaluates the captured execution data and identifies the critical path of tasks that establishes the overall run-time of the software application. Advantageously, since the execution data includes both task-level performance data and dependencies between tasks, the dependency investigator enables the developer to effectively optimize software and hardware in computer systems that are capable of concurrently executing tasks.

Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

Abstract: Disclosed are mechanisms for implementing three-dimensional operations for electronic circuit designs. These mechanisms identify a cross-layer layout portion by identifying a first electronic design as an editable layout portion and a second electronic design as a selectable and non-editable layout portion in a single window, determine a ruler by identifying or generating the ruler for a three-dimensional operation across the first electronic design and the second electronic design on different layers, identify one or more starting targets and one or more end targets within an aperture at least by determining the one or more starting targets and one or more end targets based in part or in whole upon a location of the aperture and the one or more rulers, and perform the three-dimensional operation at least by manipulating a plurality of shapes in the cross-layer layout portion based in part or in whole upon the one or more rulers.

Abstract: A method for generating a layout pattern includes following steps. A basic layout pattern including a plurality of first stripe patterns in a first cluster region is provided. Each first stripe pattern extends in a first direction, and the first stripe patterns have equal pitches in a second direction. A plurality of anchor bar patterns are generated. Each anchor bar pattern extends in the first direction, and the anchor bar patterns have equal pitches in the second direction. Edges of at least one of the anchor bar patterns in the second direction are aligned with edges of two adjacent first stripe patterns respectively. At least one of the anchor bar patterns overlaps a first space between two adjacent first stripe patterns. At least one first mandrel pattern is generated at the first space overlapped by the anchor bar pattern, and the first mandrel pattern is outputted to a photomask.

Abstract: Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a series of one or more PFTs for hardware of the SDN device, each of the PFTs having one or more capabilities; generating, using dynamic programming based on the properties of the VFTs and the capabilities of the PFTs, a mapping of the series of VFTs onto the series of PFTs; and outputting the generated mapping for implementation on the hardware of the SDN device.

Abstract: Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.

Abstract: A method of detecting one or more faults in a semiconductor device that includes generating one or more secondary node lists from a primary node list. The primary node list includes one or more nodes. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists. The method also includes generating a test pattern set from the secondary node list and a fault list. The fault list identifies one or more faults.

Abstract: Electronic design automation systems and methods are presented for top-down timing budget flow in master-clone scenarios. In some embodiments, different instances of a master-clone block within an integrated circuit design are associated with different constraint files. The different constraint files are based on the different connections of each instance with elements of the integrated circuit design as well as the shared structure of the master-clone block. A top-down timing budget flow may then be generated based on the differing constraint files, and the integrated circuit design may be modified based on this analysis prior to generation of physical devices based on the design.

Abstract: Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.

Abstract: Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: An example method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design is described. The method includes traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis. The method further includes adding an execution unit to the control and data flow graph for each module having concurrent paths. Each execution unit includes nodes in the control and data flow graph. The nodes include a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths.

Abstract: Methods and apparatuses related to the generation of test stimuli are described. In some embodiments, a finite state machine is generated based on a mission profile, and test stimuli are generated based on the mission profile.

Abstract: A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.

Abstract: An approach for simulating a block of a circuit design includes using a row-matching table and a port state vector. The row-matching table includes a plurality of rows, and each row includes encoded input match patterns corresponding to a plurality of input ports of the block and an associated output value. The port state vector includes input state codes associated with the input ports. In response to an update of an input signal value at one of the input ports during simulation, the input state code associated with the one input port is updated according to the updated input signal value. A bit-to-bit pattern match is performed for each bit in the port state vector to a corresponding bit in the encoded input match patterns in one or more rows of the row-matching table. The associated output value of a matching row is selected as a new output value.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A wiring topology display method, includes: obtaining layout information indicating positions of components and wiring coupling the components; dividing first wiring into first pieces of partial wiring, and generating partial wiring information indicating the first pieces of partial wiring; identifying a first length of the partial wiring and a first angle of the partial wiring for a vector; identifying combinations of second pieces of partial wiring based on the first length and the first angle, the second pieces of partial wiring having second lengths which are a certain length or more, second angles which are different by a certain angle, and a distance which is a certain distance or less; identifying a group having the combinations including pieces of identical partial wiring; and symbolizing third pieces of partial wiring at both ends of the group and fourth pieces of partial wiring between the third pieces of partial wiring.

Abstract: An circuit-component-migration-apparatus is a computer that performs migration of design data between different pieces of circuit design software. The circuit component migration apparatus may be a design apparatus in which circuit design software of a migration destination of design data operates. The circuit component migration apparatus includes a storage unit, an obtaining unit, and a control unit.

Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Abstract: When compiling high-level, graphical code (e.g. LabVIEW™ code) to a different representation (e.g. different software code or hardware FPGA), information relating to characteristics of the design may be collected/captured from the compilation process, and automatically provided to all the earlier stages of the compilation process to obtain more optimal results. Without automated feedback of this information, users have to manually identify, produce, and provide the feedback information, or forego the process altogether, having to assume that the tool has produced the best possible results when that may not be the case. To correct timing, failed constraints paths may be parsed and compared to delays obtained during a previous compile, and previous adjustments that didn't yield desired results may be undone. The longest delay that didn't result from an undone path may then be identified, and adjusted, and the process may be repeated until all paths are predicted to pass.

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.

Abstract: A method of partitioning a verification test bench, the method comprising: receiving a source code of the verification test bench, the source code comprising reactive components for sending test traffic to a design under test (DUT) and for receiving test traffic from the DUT, the source code further comprising analytic components for verifying the test traffic between the reactive components and the DUT; identifying the analytic components in the source code; compiling the reactive components and the DUT into a first executable test bench that can be run in a regression to generate test traffic between the reactive components and the DUT; and compiling the analytic components into a second executable test bench that can be run separately from the first executable test bench in order to verify the test traffic.

Abstract: An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

Abstract: Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

Abstract: A computer implemented method for correcting early mode slack fails in an electronic circuit can include generating a logical description of an electronic circuit having a path from first circuit to a second circuit. The method then include compiling the logical description into a technology specific representation of the circuit. The method may further include determining that the path has an early mode slack fail. The method may be continued by identifying, in response to determining that a second path has a first early mode slack fail, a complex logic gate located in the second path and having an output coupled to the input of the second circuit that can be decomposed into two or more logic gates. The method may then conclude by decomposing, by processor, the complex logic gate into a two or more logic gates to address the early mode slack fail.

Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

Abstract: The techniques and/or systems described herein implement a network management service configured to read and write a state of a network for various applications (e.g., network management applications) so that the applications can operate independently. The network management service is configured to read an observed network state and provide the observed network state to the applications. Subsequently, the network management service receives proposed network states from the applications and uses a state dependency graph to determine whether state conflicts exist between the proposed network states. The network management service also determined whether defined policies are violated by the proposed network states. Finally, the network management service is configured to generate a target network state by merging non-conflicting proposed network states that comply with defined policies and to update (e.g., write) the network state based on the generated target network state.

Abstract: Methods and systems for symbolic execution of software under test include the use of parametric states to losslessly represent a group of concrete execution states. Mathematical abstractions may represent differences between execution states and may define a parametric constraint for a parametric state. The parametric states may be usable for symbolic execution to reduce an amount of memory resources consumed and/or reduce a computational load during symbolic execution. Using parametric states, a larger state space and more program behaviors may be testable using symbolic execution.

Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.

Abstract: A method and apparatus for performing compiler optimizations is described. The method determines one or more impossible values for a variable in a program code based on a plurality of values of the variable. The method propagates the one or more impossible values for the variable throughout the program code. The method identifies a set of unreachable targets in the program code based on the propagated impossible values for the variable. The method removes objects associated with the set of unreachable targets.

Abstract: An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.

Abstract: Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

Abstract: A system and method for configuring a microprocessor core may allow a microprocessor core to be configurable. Configuration may be dynamic or automatic using an application program. Microprocessor memory, decoding units, arithmetic logic units, register banks, storage, register bypass units, and a user interface may be configured. The configuration may also be used to optimize an instruction set to run on the microprocessor core.

Abstract: Methods and apparatuses for modifying a Gerber-compliant data structure that is representative of an existing printed circuit board (PCB) layout are described. This may include obtaining a Gerber-compliant data structure which includes layout information describing the physical layout of a PCB, obtaining modification information representing a modification to the physical layout of the PCB, and automatically modifying the Gerber-compliant data structure to seamlessly incorporate the modification information to create a new electrical connectivity structure for the Gerber-compliant data structure.

Abstract: A system and method introduces one or more errors into computer programming code generated from a model or other source program. The one or more errors are not present in the model, but are introduced into the code generated from the model. The one or more errors may simulate one or more bugs in the code generation process. The generated code, including the one or more introduced errors, may be analyzed by one or more verification tools. The one or more verification tools examine the generated code in an effort to detect the one or more errors that were introduced. The one or more verification tools may compare the generated code to the model or source program. If the one or more verification tools is able to detect the one or more introduced errors, then the one or more verification tools may be considered to be validated.

Abstract: Hierarchical layout synthesis of complex cells. In some embodiments, a method may include partitioning a cell into a plurality of subcells, where the cell represents a set of electronic components in an integrated circuit; identifying, among the plurality of subcells, a most complex subcell; synthesizing a layout of the most complex subcell for each of one or more side-port configurations; selecting a side-port configuration based upon the layout of the most complex subcell; and synthesizing a layout of one or more of the plurality of subcells neighboring the most complex subcell by propagating one or more constraints associated with the selected side-port configuration.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: An apparatus for processing a sequence of tokens to detect predetermined data, wherein each said token has a token type, and the predetermined data has a structure that comprises a predetermined sequence of token types, including at least one optional token type. The apparatus comprises a processor arranged to: provide a tree for detecting the predetermined data, the tree comprising a plurality of states, each said state being linked with at least one other state by a respective condition, the arrangement of linked states forming a plurality of paths; and compare the token types of the sequence of tokens to respective conditions in the tree to match the sequence of tokens to one or more paths in the tree, wherein the predetermined data can be detected without using an epsilon reduction to take account of said at least one optional token type.

Abstract: Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.

Abstract: A circuit information processing device includes an evaluating unit that evaluates complexity of placement and routing of each of multiple circuit configurations, the multiple circuit configurations each having a common portion common to the multiple circuit configurations and a non-common portion not common to the multiple circuit configurations, a selecting unit that selects, from among the multiple circuit configurations, a reference circuit configuration evaluated by the evaluating unit as satisfying a predetermined criterion, and a generating unit that causes first placement and routing information to be shared by circuit configurations other than the reference circuit configuration, and generates second placement and routing information for each of the circuit configurations other than the reference circuit configuration, the first placement and routing information being information for placing and routing the common portion of the reference circuit configuration, the second placement and routing inform