Abstract: Disclosed approaches for fixing a hold time violation in a circuit design include determining a first hold budget that is an amount to fix a first hold time violation on a first path of the circuit design. For each connection of a first plurality of connections on the first path, a respective projected setup slack of the connection in allocating the first hold budget to fixing the first hold time violation on the connection is determined. For each connection of the first plurality of connections, a respective connection hold budget based on the first hold budget and the respective projected setup slack is determined. Each connection of the first plurality of connections is adjusted according to the respective connection hold budget.

Abstract: A method for designing a system on a target device includes generating a scheduled netlist and a hardware description language (HDL) of the system from a computer language description of the system. An area report is generated prior to HDL compilation, based on estimates from the scheduled netlist, that identifies resources from the target device required to implement portions of the computer language description of the system.

Abstract: The present disclosure relates to system(s) and method(s) for capturing transaction specific stage-wise log data corresponding to at least one of a Design Under Verification or System Under Verification (DUV/SUV). The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench is configured to generate a set of input packets to be processed by the DUV/SUV. Further, the testbench is also configured to generate corresponding expected output packets. If an expected output packet does not match the corresponding actual output packet generated by the DUV/SUV after processing the set of input packets, or if the actual output packet is not generated by the DUV/SUV (when it is expected to), the testbench is configured to capture transaction specific stage-wise log data for the corresponding expected output packet in a separate TSSW log file.

Abstract: The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet.

Abstract: A dynamic path estimation method reconstructs a program timeline in real time from an incoming stream of audio or visual content in which watermark payloads are redundantly encoded. A receiving device buffers a portion of the incoming signal, executes watermark detection on the contents of the buffer, presents detection results, and then advances the incoming signal in the buffer. Each detection result corresponds to different possible detection paths, as the detector does not reveal the precise position of the watermark payload. The dynamic path estimation method operates on the detection results to determine a global cost function for each possible detection path. As the incoming audio advances through a detection buffer, the method updates cost values for the possible paths, determines a global cost for the paths, and outputs a timeline based on the path of the lowest global cost.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.

Abstract: Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware NoC design and physically aware NoC Specification based on one or more of given SoC architectural details, physical information of SoC, traffic specification, power profile and one or more constraints. The method includes steps of receiving input information, determining the location/position of different NoC agents, interconnecting channels, pins, I/O interfaces, physical/virtual boundaries, number of layers, size/depth/width of different channels at different time, and locating/configuring the different NoC agents, interconnecting channels, pins, I/O interfaces, and physical/virtual boundaries.

Abstract: A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

Abstract: Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage, and as a result assists subsequent debugging and back-annotation of RTL.

Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design having a plurality of loops and removing a section of each of the plurality of loops. The method may further include obtaining an input/output net for each of the plurality of loops and generating a copy of at least a portion of the electronic design. The method may include connecting all inputs except a loop cut input net associated with the removed section and analyzing a loop output net using formal verification.

Abstract: A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for analyzing and/or transforming code (typically, source code) to reduce or avoid redundant or unnecessary power usage (e.g., power cycling, resource leak bugs, and/or unnecessarily repeated activity) in the device that will ultimately execute the application defined by the source code. The disclosed methods can be implemented by a software tool (e.g., a static program analysis tool or EDA analysis tool) that analyzes and/or transforms source code for a software application to help improve the performance of the software application on the target device. The disclosed methods, apparatus, and systems should not be construed as limiting in any way.

Abstract: A method is provided for synthesizing a computer program by a hardware processor and a program synthesizer. The method includes representing program components and registers by position set variables and constraints on the position set variables using Monadic Second-Order Logic. The method further includes determining potential combinations of the program components by solving the constraints. The method also includes forming the computer program from at least one of the potential combinations.

Abstract: A specific information processing function, which assumes circuit implementation, is described in a programming language, and from this description, an RTL description that can be logic synthesized is automatically generated. A logic circuit generation device includes: a control flow graph generation unit that generates a control flow graph; a control flow degenerate conversion unit that generates a control flow degenerate program by removing all condition branch instructions from the control flow graph; a data flow graph generation unit that generates a data flow graph from the control flow degenerate program; and a logic circuit description output unit that generates logic circuit description indicating a sequential circuit in which a rooted branch of the data flow graph corresponds to the wiring of the logic circuit and a node of the data flow graph corresponds to a computing element of the logic circuit.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed or distributed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives first samples corresponding to inputs that characterize configuration of the DSN and receives second samples corresponding to outputs that characterize system behavior of the DSN. The computing device then processes the first and samples to generate a DSN model to generate predictive performance of the outputs based on various values of the inputs. In some instances, the DSN model is based on a neural network model that employs the inputs that characterize the configuration of the DSN and generates the outputs that characterize system behavior of the DSN.

Abstract: A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.

Abstract: Systems and methods automatically generate optimized hardware description language code for a model created in a modeling environment. A training tool selects and provides scripts to a hardware synthesis tool chain that direct the tool chain to synthesize hardware components for core components of the modeling environment. A report generated by the tool chain is evaluated to extract performance data for the core components, and the performance data is stored in a library. An optimization tool estimates the performance of the model using the performance data in the library. Based on the performance estimate and an analysis of the model, the optimization tool selects an optimization technique which it applies to the model generating a revised. Estimating performance, and selecting and applying optimizations may be repeated until a performance constraint is satisfied or a termination criterion is met.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: Solutions for object tracking problems are presented by gathering images using one or more cameras, processing the gathered images to generate a directed acyclic graph, using the directed acyclic graph to determine a path cover that achieves maximum weight and satisfies one or more positive or negative constraints, and using the path cover to solve the object tracking problem. A first set of solutions utilizes trellis graphs, a second set of solutions employs a greedy approach, and a third set of solutions uses search algorithms.

Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a plurality of clusters of related RTL modules of the IC design are generated based on statistical analysis of the collected coverage data and hierarchal information of the RTL modules. When changes are made to the RTL modules during the IC design process, a plurality of affected RTL modules are identified based on the clusters of the RTL modules and a plurality of regression tests are generated dynamically for these affected RTL modules based on their corresponding coverage data. The dynamically generated regression tests are then run to verify the changes made in the IC design.

Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.

Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Abstract: A method for designing a system on a target device includes describing the system in a high-level synthesis language where the system includes a configurable clock to drive the system at a specified clock frequency. A hardware description language (HDL) of the system is generated from the high-level synthesis language. An initial compilation of the HDL of the system is performed in response to the specified clock frequency. Timing analysis is performed on the system after the initial compilation of the HDL to determine a maximum frequency which the system can be driven. The configurable clock is programmed to drive the system at the maximum frequency.

Abstract: A method for designing a system on a target device includes identifying a soft processor to implement on the target device. The soft processor is optimized in response to code to be executed on the soft processor. Other embodiments are also disclosed.

Abstract: A method of tuning a controller area network (CAN) communication model includes: measuring a CAN signal waveform, dividing the CAN signal waveform into a steady period and a dynamic period, determining a parameter for the steady period, determining a parameter for the dynamic period, modeling a CAN line using the parameter for the steady period and the parameter for the dynamic period, and performing error analysis on the CAN line.

Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

Abstract: A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.

Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method for behavioral modeling of jitters due to power supply noise for input/output (I/O) buffers. The method may include accessing physical model data describing a physical structure of an integrated circuit device, and accessing a behavioral model schema for evaluating electrical characteristics of the integrated circuit device including jitter effects introduced by power noise in the integrated circuit device. The method may further include generating behavioral model data based on the physical model data, the behavioral model data including the electrical characteristics of integrated circuit device. The method may further include providing a data file including the behavioral model data.

Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.

Abstract: An integrated circuit may have processing and storage circuits that perform read-modify-write operations on a wide data path. A CAD tool may partition the wide data path into data path subsets based on the width of the wide data path, the characteristics of the processing and storage circuits, and various constraints such as resource constraints and timing constraints. The CAD tool may also instantiate corresponding pipelined circuitry. The pipelined circuitry may be arranged in slices with cascaded processing and storage circuits. Each processing and storage circuit in a slice may perform a read-modify-write operation based on the corresponding data path subset and any prior result produced by other processing and storage circuits.

Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.

Abstract: In one embodiment, a method comprises creating, in a computing network, a loop-free routing topology comprising a plurality of routing arcs for reaching a destination device, each routing arc comprising a first network device as a first end of the routing arc, a second network device as a second end of the routing arc, and at least a third network device configured for routing any network traffic along the routing arc toward the destination device via any one of the first or second ends of the routing arc; and causing the network traffic to be forwarded along at least one of the routing arcs to the destination device.

Abstract: Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

Abstract: Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.

Abstract: Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

Abstract: The present invention classifies all critical paths into two basic types: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: a static logic part, called critical path component (CPC), and a dynamic logic part, formalized into four wave-pipelining components (WPC) shared by all wave-pipelined circuits. Each wave-pipelining ready code in HDL comprises two components: a WPC instantiation and a CPC instantiation wire-connected and linked by a new link statement. Each WPC has new wave constants which play the same role as generic constants do, but whose initial values are determined and assigned by a synthesizer after code analysis, so designers can use after-synthesization information in their code before synthesization for wave-pipelining technology.

Abstract: An integrated circuit includes a first circuit, a second circuit, and a bus that couples the circuits together. The first circuit is simulated on a first simulator at the same time that the second circuit is simulated on a second simulator. A simulator plug-in is incorporated into the simulation model of the first circuit. A simulator plug-in is incorporated into the simulation model of the second circuit. If valid data is to pass from the first to second circuit across the bus during simulation, then the plug-in of the first model causes a network stack to generate a packet. The packet carries the data. After communication to the second simulator, the data is recovered from the packet, and is injected by the plug-in of the second model into the simulation of the second circuit. By exchanging data back and forth this way, multiple circuits are simulated simultaneously on different simulators.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: According to an aspect of some embodiments of the present invention there is provided a computerized method of analyzing code of a software program for dominance relationships between a plurality of functions of the software program, the method comprising: receiving source code of a software program, the source code having a plurality of functions; identifying a plurality of intraprocedural dominator graphs each for another of the plurality of functions; combining the plurality of intraprocedural dominator graphs to create an interprocedural dominance graph with edges that logically connect between nodes of the plurality of functions; identifying a plurality of interprocedural dominance relations between nodes in different functions of the plurality of functions using the interprocedural dominance graph; and analyzing the software program according to the plurality of interprocedural dominance relations.

Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays.

Abstract: Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block implementing the first function with a second circuit block implementing the second function. Control circuitry is included within the circuit design. The control circuitry may be configured to implement concurrent operation of the first circuit block and the second circuit block by controlling accesses of the first circuit block and the second circuit block to a plurality of buffers in the FIFO memory.