Abstract: A computing device includes an interface configured to interface and communicate with a dispersed or distributed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives first samples corresponding to inputs that characterize configuration of the DSN and receives second samples corresponding to outputs that characterize system behavior of the DSN. The computing device then processes the first and samples to generate a DSN model to generate predictive performance of the outputs based on various values of the inputs. In some instances, the DSN model is based on a neural network model that employs the inputs that characterize the configuration of the DSN and generates the outputs that characterize system behavior of the DSN.

Abstract: A method of high level synthesis may include detecting in an application, using computer hardware, a first function including a first call site for a second function and a second call site for the second function, determining, using the computer hardware, that the first call site and the second call site each pass different data to the second function and each receive different return data from the second function, and generating, using the computer hardware, a circuit design from the application including a circuit block implementing the second function and multiplexer circuitry. The multiplexer circuitry may be configured to coordinate passing of data to the circuit block from a first source circuit corresponding to the first call site and a second source circuit corresponding to the second call site, with handshake signals exchanged between the circuit block, the first source circuit, and the second source circuit.

Abstract: A method, system and computer program product, the method comprising: obtaining circuit information of at least a portion of a circuit design, the circuit information specifying a plurality of components and a plurality of connecting elements connecting components from the plurality of components; receiving a plurality of rule definitions, each rule definition verifying an interaction between one or more first objects and one or more second objects, via one or more connecting elements; obtaining a plurality of specific rules generated upon the plurality of the rule definitions; verifying the specific rules against the circuit information, thereby checking that the first objects have the interaction with the second objects via the one or more connecting elements; and outputting results of verifying the specific rules.

Abstract: A computer executable tool analyzes Boolean logic in a gate-level netlist responsible for generating false Xs due to X-pessimism in logic simulation to produce a compact fix that corrects the X-pessimism problem. The fix restores logic simulation value from X to hardware-accurate non-X value and solves X-pessimism issues in logic simulation.

Abstract: A product line engineering (PLE) feature modeling structure called a multistage configuration tree that supports the engineering, deployment and maintenance of complex product family trees is provided. Feature selections and downselections are incrementally staged throughout the nodes in a product family tree. Feature decisions made at any node are inherited by all descendants of that node, thereby defining a product family subtree.

Abstract: Electronic design automation systems, methods, and media are presented for view pruning to increase the efficiency of computing operations for analyzing and updating a circuit design for an integrated circuit. One embodiment involves accessing a circuit design stored in memory that is associated with a plurality of views, selecting a first view of the plurality of view for view pruning analysis, and identifying a plurality of input values for the first view of the plurality of views. Random nets are generated based on the views, view inputs, and pruning thresholds. Certain views are then selected as dominant based on a comparison of the output slews different nets and views. Subsequent analysis is then performed and used to update the design without using the pruned views (e.g., using the selected dominant views).

Abstract: Various techniques implement an electronic design with hybrid analysis techniques. An activity map is identified or generated for an electronic design. The electronic design is reduced into a reduced electronic design at least by applying a plurality of reduction processes to different portions of the electronic design based in part or in whole upon the activity map. Transient behaviors of the electronic design may be determined or predicted at least by performing one or more transient analyses on a representation of the electronic design with a simulation start point based in part or in whole upon the activity map. The electronic design may then be implemented for manufacturing at least by modifying or correcting the electronic design based at least in part upon the transient behaviors.

Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

Abstract: A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

Abstract: A method for managing a programmable logic circuit by invoking a dynamic library function. The method includes invoking an application programming interface (API) function by an application from a shared object; dynamically loading the library in memory and linked on demand; associating the library to a logic circuit configuration file describing logic connections within a programmable logic device (PLD); transmitting and loading the configuration file into the PLD to map the logic circuit configurations; writing, through the dynamic library, input data values as a circuit entry and clock signal for driving the logical execution of the function mapped in hardware; collecting through the dynamic library the output data values resulting of logic circuits execution by reading output of the logic circuit; converting through the dynamic library, the logic circuit output to the expected data type specified by the API function; and returning the data result to a calling application.

Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.

Abstract: A structure determination unit (112) obtains an operational description (511) and determines a candidate of a circuit structure applicable to a plurality of execution units as a structure candidate, the operational description (511) describing an operation of a circuit and including the plurality of execution units. A decision unit (113) calculates, as a circuit characteristic (522), a characteristic of the circuit when the circuit structure of the plurality of execution units is the structure candidate and outputs the structure candidate as a determined circuit structure (310) when the circuit characteristic (522) meets a threshold (521). A high level synthesis unit (140) performs high level synthesis on the operational description (511) so that the circuit structure of the plurality of execution units becomes the determined circuit structure (310).

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. Responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, the tool determines whether a latch of the one or more latches is corrupted by an unknown source. The tool gathers each of the one or more latches determined to be an unknown source after a capture clock phase. The tool performs a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source. The tool verifies that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

Abstract: Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

Abstract: Incremental synthesis for changes to a circuit design can include synthesizing, using computer hardware, a first circuit design resulting in a partitioning of the first circuit design and a plurality of synthesized partitions of the first circuit design and, for a second circuit design that is a modified version of the first circuit design and based upon the partitioning of the first circuit design, determining, using the computer hardware, a partition of the second circuit design that differs from the first circuit design. The partition of the second circuit design can be technology mapped using the computer hardware resulting in a synthesized partition of the second circuit design.

Abstract: A method is provided for synthesizing a computer program by a hardware processor and a program synthesizer. The method includes representing program components and registers by position set variables and constraints on the position set variables using Monadic Second-Order Logic. The method further includes determining potential combinations of the program components by solving the constraints. The method also includes forming the computer program from at least one of the potential combinations.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Abstract: Systems and methods are disclosed herein for performing automated testing of software. Information characterizing a set of application programming interface (API) calls is associated with the software. Dependencies between the API calls are determined using the information and a representation is generated using the dependencies. The dependencies of the representation are verified by providing API requests to the API calls. The verified representation is provided for automated testing of an API and the associated API calls.

Abstract: Various implementations described herein refer to a method. The method may include selecting a target memory instance to characterize for timing file generation, determining a number of segments for the target memory instance based on user defined accuracy, and partitioning the target memory instance into the number of segments based on a physical architecture of the target memory instance. The method may also include generating test-bench data based on the number of segments and simulating the test-bench data, obtaining simulation data for the target memory instance associated with each segment in the number of segments, and generating a timing file by reporting timing data for each segment in the number of segments.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: Some embodiments described herein provide a system for creating platform-independent software application programs. During operation, the system receives a configuration program and an application program, the application program including conditional and unconditional components. The system creates a configuration executable binary and loads this binary into a configuration execution space. The system creates a parse tree of the application program. Subsequently, the system evaluates each component of the application program in the configuration execution space and generates a modified parse tree of the application program. Semantic analysis is performed on this modified parse tree to generate an executable binary and a composition map for the application program.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: An object-oriented method for multi-threading in a constraint satisfaction solver is provided. A master thread establishes a first solution state of a constraint problem. The master thread establishes a plurality of solver threads, each solver thread having an initial solution state that is identical to a first solution state of the master thread, and a plurality of cloned planning entity objects that are clones of a plurality of planning entity objects. The master thread communicates a first plurality of temporary incremental state changes to the plurality of solver threads that alters the initial solution state of each solver thread to a different solution state. The master thread receives, from each respective solver thread of the plurality of solver threads, a first score associated with the different solution state of the respective solver thread.

Abstract: A circuit editor generates a graphic rendering of an electronic circuit design for partial display in a visual canvas on a display unit. The circuit editor detects aberrant arrangements of circuit elements which violate predetermined circuit layout criteria, such as minimum spacing between the edges or corners of circuit elements, and forms a correction scheme to rearrange the circuit elements such that consistency with the circuit layout criteria is restored. When the aberrant arrangements are not themselves displayed in the visual canvas, the circuit editor generates visual indications of the layout violation and of the correction scheme, the latter being used to guide user correction of the violation.

Abstract: A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

Abstract: A system and method for allowing configuration of a baseboard for different types of servers is disclosed. Desired parameters and corresponding server identifications are stored in either a hardware or software straps structure in a firmware image. A board identification including a server product type is read from a memory on a baseboard. The server product type is compared the server identifications in the straps structure. The corresponding desired parameter is loaded to a baseboard component on the baseboard to perform a server function.

Abstract: A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification re

Abstract: A computer performing a transient vectorless power analysis of a multi-clock domain integrated circuit (IC) design may execute a scheduling cycle based on the dominant clock frequency and schedule events based on comparing instance clock frequencies with the dominant clock frequency. If the instance clock frequency matches the dominant clock frequency, the computer may schedule a single event per scheduling cycle for the sequential circuit devices driven by the respective instance clocks. If the instance clock frequency is faster than the dominant clock frequency, the computer may schedule number of events per scheduling cycle based on the ratio of the instance clock frequency to the dominant clock frequency. If the instance clock frequency is less than the dominant clock frequency, the computer may schedule a single event per scheduling cycle if the computer determines that there is a triggering edge of the instance clock within the scheduling cycle.

Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.

Abstract: Disclosed approaches include inputting a block diagram representation of a circuit design to a processor. Respective high-level programming language (HLL) code fragments associated with each block of the block diagram representation are determined. A dependency graph is generated from the block diagram representation. One or more clusters of vertices are generated from the dependency graph. Each of the HLL code fragments represented by the vertices of each cluster includes a for-loop, and each cluster includes a subset of the plurality of vertices and edges. For each of the clusters, a plurality of for-loops of the HLL code fragments associated with blocks represented by the vertices of the cluster are combined into a single for-loop. An HLL function is generated from each single for-loop and the HLL code fragments associated with each block that is not represented by any of the one or more clusters.

Abstract: A method for processing signals in a system includes deriving a signal activity for a signal from a timing requirement assignment for the signal.

Abstract: Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.

Abstract: A memory-specific implementation of a test and characterization vehicle utilizes a design layout that is a modified version of the product mask. Specific routing is used to modify the product mask in order to facilitate memory cell characterization. This approach can be applied to any memory architecture with word-line and bit-line perpendicular or substantially perpendicular to each other, including but not limited to, volatile memories such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), non-volatile memory such as NAND Flash (including three-dimensional NAND Flash), NOR Flash, Phase-change RAM (PRAM), Ferroelectric RAM (FeRAM), Correlated electron RAM (CeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), XPoint memory and the like.

Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.

Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.

Abstract: A computer-implemented method of promoting timing constraints in an electronic design automation process of a chip is provided. A method of promoting a lower level block's timing constraint to an upper level block by providing an option to preserve the timing intent of the lower level block at the same time, or to modify the timing constraint such that the block level timing is in context to the top level block timing is provided. The method implements automatic promotion of timing constraint in different modes as an integration mode; an isolation mode and combination thereof, wherein the integration mode is independent of SDCs; and the isolation mode is based on the input SDCs. A method of automatically promoting constant values that are defined through a set_case_analysis command in the SDC file is further provided.

Abstract: An asynchronous switching system and method for processing SDI data streams, the system and method utilizing one or more buffers for cleaning up an output of a dirty IP switch.

Abstract: Aspects include a computer-implemented method for scan diagnostic logic circuit insertion in a circuit design topology. A method includes evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain. The method also includes identifying one of the plurality of physical structures as a physical structure of interest, and responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.

Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.

Abstract: One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

Abstract: Embodiments relate to schematic overlays describing modification to a base design for exploring modification or verification of the base design. Test circuitry may be modified or inserted without effecting the change in a base design schematics. The modifications to the base design schematics are also highlighted in views at a level of hierarchy where the modifications were made as well as at a higher levels of circuit abstraction. By using schematic overlays, modification to the base design can be avoided while creating a testbench.

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Abstract: Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.

Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.

Abstract: An apparatus may include a processor caused to: receive indications of first and second experiment designs to be compared; for each factor of the model of the first experiment design, identify a matching factor of the model of the second experiment design based on factor type, wherein the factor type is selected from the group consisting of a categorical factor and a continuous factor; for each categorical factor of the model of the first experiment design, identify a matching factor of the model of the second experiment design additionally based on quantity of levels of each factor; for each term of the model of the first experiment design, identify a matching term of the model of the second experiment design based on an order of each term; and present, on a display, the identified matches between the terms and between the responses of the first and second experiment designs.