Logic Circuit Synthesis (mapping Logic) Patents (Class 716/104)
  • Patent number: 11295286
    Abstract: Example implementations relate to a retail point of sale (RPOS) device and cloud service. An example system can include an RPOS agent controller and a cloud service controller communicatively coupled to one another. The cloud service controller can provide a notification of a state of the RPOS device.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 5, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Binh T Truong, Quoc P Pham, Amit Kumar Singh, David Gosman, Suzanne Broussard
  • Patent number: 11281827
    Abstract: A tool is disclosed that includes a discriminant module. The discriminant module finds one configuration, which is selected from many different possible and legal configurations, that is optimal. The optimal configuration is translated into a set of optimized parameters (identified from the library of parameters that the user can select from) and provided to the designer. The designer reviews (and can manually revise or change) the optimized parameters. The optimized parameters are translated into engineering parameters. The engineering parameters are passed, as an input, to the RTL generation module. The RTL generation module produces the RTL description of the hardware function that is optimal and meets the designer's defined requirements.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: March 22, 2022
    Assignee: ARTERIS, INC.
    Inventors: Khaled Labib, Federico Angiolini
  • Patent number: 11269762
    Abstract: Disclosed herein are techniques for analyzing hardware change impacts based on at least one functional line-of-code behavior and relation model. Techniques include identifying a new hardware component associated with a system; accessing a first line-of-code behavior and relation model representing execution of functions using the new hardware component; accessing a second line-of-code behavior and relation model representing execution of functions on a previous hardware component of the system; performing a functional differential comparison of the first line-of-code behavior and relation model to the second line-of-code behavior and relation model; determining, based on the functional differential comparison, a status of functional equivalence between the new hardware component and the previous hardware component; and generating, based on the determined difference, a report identifying the status of functional equivalence.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 8, 2022
    Assignee: Aurora Labs Ltd.
    Inventors: Zohar Fox, Carmit Sahar
  • Patent number: 11263379
    Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 1, 2022
    Inventors: Hongda Lu, Sridhar Subramaniam, Kok-Hoong Chiu
  • Patent number: 11232245
    Abstract: A circuit generation device that implements a standard function and a degeneration function has a first operation synthesis function of generating a circuit description based on a system operation description, there are provided a degenerate parameter extraction function of extracting a degenerate parameter from the operation description, a degeneration parameter change function of changing a value of the degeneration parameter, a second operation synthesis function of generating a degeneration circuit description based on the operation description and the degeneration parameter value, and a determination function of determining whether the performance of the degeneration circuit description satisfies a constraint condition based on the circuit description.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 25, 2022
    Assignee: HITACHI, LTD.
    Inventors: Teruaki Sakata, Teppei Hirotsu
  • Patent number: 11227084
    Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jerry Chang Jui Kao, Hui-Zhong Zhuang, Yung-Chen Chien, Ting-Wei Chiang, Chih-Wei Chang, Xiangdong Chen
  • Patent number: 11205032
    Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shen Lin, Chung-Hsing Wang, Kuo-Nan Yang, Hiranmay Biswas
  • Patent number: 11151301
    Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: October 19, 2021
    Assignee: SiFive, Inc.
    Inventors: Megan Wachs, Henry Cook, Wesley Waylon Terpstra
  • Patent number: 11132491
    Abstract: A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty IC layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the IC layout design.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: September 28, 2021
    Assignee: Synopsys, Inc.
    Inventor: John R. Studders
  • Patent number: 11126768
    Abstract: In a method of designing a semiconductor device, a first sub-block included in the semiconductor device is designed by a first EDA tool. A second sub-block included in the semiconductor device is designed by a second EDA tool different from the first EDA tool. A first sub-block model corresponding to the first sub-block and a second sub-block model corresponding to the second sub-block are generated by transforming logical information and physical information associated with one of a result of designing the first sub-block or a result of designing the second sub-block. The first and the second sub-block model have a same format. An integrated physical design for the semiconductor device is obtained by combining the first and the second sub-block based on the first and the second sub-block model. The first and the second EDA tool are configured to design different physical structures for a same logical block.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 21, 2021
    Inventors: Jungsu An, Daehyung Myung
  • Patent number: 11126770
    Abstract: A design method of a semiconductor integrated circuit according to embodiments includes: creating pseudo-cell information for cells included in cell library information, the pseudo-cell information reflecting the degree of difficulty of pin access that connects wires to pins set in the cells; and using cells with a low difficulty of pin access with reference to the pseudo-cell information in timing optimization.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 21, 2021
    Assignee: Kioxia Corporation
    Inventor: Shintaro Fujiwara
  • Patent number: 11119798
    Abstract: A method of generating compiled intermediate code files adjusted to apply execution control flow verification comprising receiving intermediate code file(s) generated by a compiler which comprise a plurality of routines and adjusting the intermediate code file(s) prior to generating a respective executable file for execution by one or more processors. The adjustment comprising analyzing the intermediate code file(s) to identify valid execution path(s) describing order of execution of preceding routines executed prior to execution of each critical routine, adding registration code segment(s) configured to register execution of each routine in a runtime execution sequence, adding flow validation code segment(s) configured to verify the runtime execution sequence against the valid execution path(s) before invoking the critical routine(s) and outputting the adjusted intermediate code file(s).
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 14, 2021
    Assignee: Sternum Ltd.
    Inventors: Natali Tshouva, Lian Granot, Arik Farber, Tal Granot
  • Patent number: 11120183
    Abstract: A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 14, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong Chiang
  • Patent number: 11087066
    Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
  • Patent number: 11074382
    Abstract: Techniques and a system for quantum computing device modeling and design are provided. In one example, a system includes a modeling component and a simulation component. The modeling component models a quantum device element of a quantum computing device as an electromagnetic circuit element to generate electromagnetic circuit data for the quantum computing device. The simulation component simulates the quantum computing device using the electromagnetic circuit data to generate response function data indicative of a response function for the quantum computing device. Additionally or alternatively, a Hamiltonian is constructed based on the response function.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanhee Paik, Firat Solgun, Salvatore Bernardo Olivadese, Martin O. Sandberg, Jay M. Gambetta
  • Patent number: 11016742
    Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 25, 2021
    Assignee: Altera Corporation
    Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
  • Patent number: 11012075
    Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyungdal Kwon, Seungwook Lee, Youngnam Hwang
  • Patent number: 11010519
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 18, 2021
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Patent number: 10997348
    Abstract: A method of generating an IC layout diagram includes positioning one or more cells in an IC layout diagram and overlapping the one or more cells with a first metal layer cut region based on a first metal layer cut region alignment pattern. The first metal layer cut region alignment pattern includes a pattern pitch equal to a height of the one or more cells.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Chan Yang, Fong-Yuan Chang, Li-Chun Tien, Ting Yu Chen
  • Patent number: 10902176
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 26, 2021
    Assignee: Synopsys, Inc.
    Inventors: Erdem Cilingir, Srinivasa R Arikati, Weiping Fang, Marco Hug
  • Patent number: 10896278
    Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Michitaka Hashimoto, Ryo Mizutani
  • Patent number: 10896476
    Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 19, 2021
    Assignee: NetSpeed Systems, Inc.
    Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
  • Patent number: 10891413
    Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Paul D. Kundarewich, Grigor S. Gasparyan, Mehrdad Eslami Dehkordi, Guenter Stenz
  • Patent number: 10860489
    Abstract: Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 8, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shomit N. Das, Matthew Tomei, David A. Wood
  • Patent number: 10831955
    Abstract: A method for predicting post-placement timing-analysis results includes obtaining, for a logic design, logic-synthesis data and logic-planning data. The method also includes inputting, into a neural network, the logic-synthesis data and logic-planning data. The neural network is trained to correlate logic-synthesis data and logic-planning data with post-placement timing-analysis results. The method also includes receiving, from the neural network, predicted post-placement timing-analysis results.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew A. Cooke, Zhichao Li, Kai Liu, Su Liu, Manjunath Ravi
  • Patent number: 10810563
    Abstract: Technologies are described herein for a payments portal. A payments portal can be configured to support payments by generating and embedding widgets in webpages hosted by merchant sites associated with a marketplace. The widgets can provide specific payment functionality for users, thereby providing consistent payment experiences across merchant sites without updating the merchant sites. The widgets can be dynamic or static. Interactions with the widgets can cause a browser displaying the widgets to access data hosted by the payments portal and/or other systems, devices or services in communication with the payments portal.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 20, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Alan G. Davison, Amitpal Singh Bhutani, Justin Michael Bonnar, Robert Benjamin Brydon, Bryan Christopher Castillo, Dennis Scott Doctor, Thomas L. Kovarik, Aatish S. Mandelecha, John Matthew Nienart
  • Patent number: 10810790
    Abstract: A device may determine temporal ages of a first signal and a second signal provided in a graphical model generated in a technical computing environment, where the first signal is different than the second signal. The device may determine whether the temporal age of the first signal is equivalent to the temporal age of the second signal at a particular block of the graphical model. The device may either display an indication that the first signal is synchronized with the second signal when the temporal age of the first signal is equivalent to the temporal age of the second signal, or may display another indication that the first signal is not synchronized with the second signal when the temporal age of the first signal is not equivalent to the temporal age of the second signal.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 20, 2020
    Assignee: TheMathWorks, Inc.
    Inventors: Pieter J. Mosterman, Justyna Zander
  • Patent number: 10803225
    Abstract: A system having design tools and methods using the same design tools in designing an integrated circuit (IC) are described.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: EFINIX, INC.
    Inventor: James Schleicher
  • Patent number: 10789403
    Abstract: Embodiments of the invention are directed to a computer-implemented method of logic verification. The method includes obtaining a netlist of a circuit comprising a plurality of observable gates. A first observable gate is grouped together with a second observable gate based on a portion of a fan-in logic of the first observable gate being equal to a portion of a fan-in logic of the second observable gate. The group is expanded by including a third observable gate, based on a first strongly connected component (SCC) in the group having a similarity greater than a first threshold to a second SCC in the fan-in logic of the third observable gate. The group is further expanded by including a fourth observable gate, based on the distance of a portion of the fan-in logic of the fourth observable gate from a fan-in logic of at least one observable gate in the group of observable gates.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rohit Dureja, Jason Raymond Baumgartner, Alexander Ivrii, Robert Kanzelman
  • Patent number: 10769330
    Abstract: A method for determining signal electromigration in a circuit includes selecting partitions from a netlist of the circuit is provided, each of the partitions including independent signal paths. The method includes determining a size of a partition, applying input vectors to a signal path in a large partition to obtain a signal toggle in an output, determining a current in the signal path, and identifying an electromigration result from the current flow. The method includes generating an output database for the partition, comprising an electromigration result for the first component, and combining the output database for the partition with a second output database from a second partition, the second output database including a second electromigration result for a second component in the second partition to generate an electromigration report for the netlist of the integrated circuit.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jalal Wehbeh, Harsh Vardhan, Federico Politi, Ajish Thomas, Aswin Ramakrishnan
  • Patent number: 10757128
    Abstract: Security policies may be utilized to grant or deny permissions related to the access of computing resources. Two or more security policies may be compared to determine whether the policies are equivalent, whether one security is more permissive than another, and more. In some cases, it may be possible to identify whether there exists a security permission that is sufficient to determine two security policies lack equivalency. Propositional logics may be utilized in the evaluation of security policies.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: John Cook, Neha Rungta, Catherine Dodge, Jeff Puchalski, Carsten Varming
  • Patent number: 10755013
    Abstract: Creating a high-level language (HLL) callable library for a hardware core can include automatically querying, using computer hardware, a metadata description of a core to determine a plurality of available ports of the core, automatically determining, using the computer hardware, an argument of a first function specified in a header file corresponding to the core, mapping, using the computer hardware, the argument to a first port of the plurality of available ports, and automatically generating and storing, using the computer hardware, an HLL library specifying a mapping of the argument to the first port of the core. The HLL library is configured for inclusion with a user application during compilation.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 25, 2020
    Assignee: Xilinx, Inc.
    Inventors: Zhenman Fang, James L. Hwang, Samuel A. Skalicky, Tom Shui, Michael Gill, Welson Sun, Alfred Huang, Jorge E. Carrillo, Chen Pan
  • Patent number: 10747930
    Abstract: An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 18, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10740518
    Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10740517
    Abstract: Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a generalized refactoring engine which supports multiple representation forms and (v) a Boolean resynthesis flow, which combines these techniques.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 11, 2020
    Assignee: Synopsys, Inc.
    Inventors: Luca Gaetano Amaru, Patrick Vuillod, Jiong Luo
  • Patent number: 10740519
    Abstract: The disclosure is directed to the design and manufacture of synchronous digital systems, such as integrated circuits (IC), to employ dynamic frequency boosting. The proposed technique overcomes limitations of conventional synchronous clock design by boosting operating clock frequency despite critical path time constraints and without violating the correct functionality. In accordance with an exemplary embodiment, ICs are configured to set the clock frequency during each state event by selecting a more optimum clock frequency, on a clock cycle basis, thus improving system performance in terms of throughput while maintaining the benefits and design approach of synchronous digital systems.
    Type: Grant
    Filed: July 8, 2017
    Date of Patent: August 11, 2020
    Assignee: TRIMSIGNAL IP LLC
    Inventor: Nikolaos Zompakis
  • Patent number: 10732971
    Abstract: A method for generating dynamical systems that can be instantiated on reconfigurable computing platforms for solving instances of the Boolean satisfiability problem (SAT) is disclosed. When the SAT instance can be satisfied by an appropriate assignment of the variables, the dynamical system has a fixed point attractor that corresponds to a satisfying assignment of variables. When the SAT instance cannot be satisfied by any assignment of variables, there is no such fixed point attractor. Exemplary embodiments represent a physically-realizable computing device that solves SAT problems outside the Turing machine paradigm. Exemplary embodiments detect when the system reaches a fixed point attractor.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 4, 2020
    Inventor: Andrew Pomerance
  • Patent number: 10715038
    Abstract: A circuit includes a first TSCP (tri-stage charge pump), a second TSCP, a third TSCP, a fourth TSCP, a fifth TSCP, and a load. The first TSCP receives a first phase and a third phase of a five-phase clock and outputs a first current to an output node. The second TSCP receives a second phase and a fourth phase of the five-phase clock and outputs a second current to the output node. The third TSCP receives a third phase and a fifth phase of the five-phase clock and outputs a third current to the output node. The fourth TSCP receives a fourth phase and the first phase of the five-phase clock and outputs a fourth current to the output node. The fifth TSCP receives a fifth phase and the second phase of the five-phase clock and outputs a fifth current to the output node. The load terminates the output node.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: July 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10699795
    Abstract: A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 30, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Norman Card, Steven Lee Gregor
  • Patent number: 10698661
    Abstract: According to at least one aspect, a system for collecting computer usage information is provided. The system includes a hardware processor, a display coupled to the hardware processor to display a user interface, and a computer-readable storage medium storing processor-executable instructions that cause the hardware processor to receive an indication of an action being performed by a user on the system, gather contextual information associated with the action responsive to the action performed by the user, store information indicative of the action and the contextual information in a volatile memory as an event, determine whether at least one event stored in the volatile memory includes personal information of the user, and write the at least one event stored in the volatile memory to an event log in a non-volatile memory responsive to a determination that the at least one event does not include personal information of the user.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: June 30, 2020
    Assignee: Soroco Private Limited
    Inventors: Yoongu Kim, Abdul Qadir, Arjun Narayanaswamy, Rohan Narayan Murty, Shane Barratt, George Peter Nychis
  • Patent number: 10665553
    Abstract: A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: May 26, 2020
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Liwei Li, Yuejun Zhang, Bo Chen, Gang Li
  • Patent number: 10664564
    Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 26, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier A Delacruz, Eric Nequist, Jung Ko, Kenneth Duong
  • Patent number: 10664035
    Abstract: In certain aspects, an integrated circuit comprises a first circuit macro having a first power delivery network, a second circuit macro having a second power delivery network. The integrated circuit further comprises a coupling circuit couples to the first power delivery network and to the second power delivery network.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 26, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Mikhail Popovich, Juan Sebastian Ochoa Munoz
  • Patent number: 10635843
    Abstract: A method for enabling user-customization of a controller design for simulation comprises accessing at least one library of individual simulation component models for controller components. The method further comprises receiving information describing an architecture of a customized controller design corresponding to a controller that controls communications between other parts of a first target system. The method additionally comprises generating a controller simulation model for the customized controller design based on the first architectural information, the controller simulation model including instances of a plurality of the simulation component models.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: April 28, 2020
    Assignee: Synopsys, Inc.
    Inventors: Amit Garg, Ashutosh Pandey, Nitin Gupta
  • Patent number: 10628544
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Patent number: 10614187
    Abstract: An exemplary system, method and computer-accessible medium can be provided which can include, for example, generating a super control dataflow graph(s) (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit, determining an upper bound(s) number and a lower bound(s) number based on a number of CDFGs in the super CDFG(s)—with each number being one metric of a capability of the integrated circuit to resist reverse engineering attack—, and inserting a component(s) into a register transfer level netlist to effectuate a modification of the upper bound(s) and the lower bound(s).
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 7, 2020
    Assignee: New York University
    Inventors: Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
  • Patent number: 10614260
    Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 7, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsiu Tsai, Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Patent number: 10606558
    Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 31, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Patent number: 10586007
    Abstract: A multi-dimensional placement methodology, system and computer readable medium is presented. A plurality of data sets is ordered by need. A plurality of storage areas are defined based on a storage device type, an associated compression algorithm, and a plurality of parameters associated with different properties of the particular storage device and the compression algorithm being used. A data set is placed in a selected storage area based on a determination of which storage area provides a desired combination of the storage device type and compression.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 10, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Ron Bigman
  • Patent number: 10572624
    Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Erez Barak, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach