Logic Circuit Synthesis (mapping Logic) Patents (Class 716/104)
  • Patent number: 11016742
    Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 25, 2021
    Assignee: Altera Corporation
    Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
  • Patent number: 11010519
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 18, 2021
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Patent number: 11012075
    Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyungdal Kwon, Seungwook Lee, Youngnam Hwang
  • Patent number: 10997348
    Abstract: A method of generating an IC layout diagram includes positioning one or more cells in an IC layout diagram and overlapping the one or more cells with a first metal layer cut region based on a first metal layer cut region alignment pattern. The first metal layer cut region alignment pattern includes a pattern pitch equal to a height of the one or more cells.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Chan Yang, Fong-Yuan Chang, Li-Chun Tien, Ting Yu Chen
  • Patent number: 10902176
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 26, 2021
    Assignee: Synopsys, Inc.
    Inventors: Erdem Cilingir, Srinivasa R Arikati, Weiping Fang, Marco Hug
  • Patent number: 10896278
    Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Michitaka Hashimoto, Ryo Mizutani
  • Patent number: 10896476
    Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 19, 2021
    Assignee: NetSpeed Systems, Inc.
    Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
  • Patent number: 10891413
    Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Paul D. Kundarewich, Grigor S. Gasparyan, Mehrdad Eslami Dehkordi, Guenter Stenz
  • Patent number: 10860489
    Abstract: Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 8, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shomit N. Das, Matthew Tomei, David A. Wood
  • Patent number: 10831955
    Abstract: A method for predicting post-placement timing-analysis results includes obtaining, for a logic design, logic-synthesis data and logic-planning data. The method also includes inputting, into a neural network, the logic-synthesis data and logic-planning data. The neural network is trained to correlate logic-synthesis data and logic-planning data with post-placement timing-analysis results. The method also includes receiving, from the neural network, predicted post-placement timing-analysis results.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew A. Cooke, Zhichao Li, Kai Liu, Su Liu, Manjunath Ravi
  • Patent number: 10810790
    Abstract: A device may determine temporal ages of a first signal and a second signal provided in a graphical model generated in a technical computing environment, where the first signal is different than the second signal. The device may determine whether the temporal age of the first signal is equivalent to the temporal age of the second signal at a particular block of the graphical model. The device may either display an indication that the first signal is synchronized with the second signal when the temporal age of the first signal is equivalent to the temporal age of the second signal, or may display another indication that the first signal is not synchronized with the second signal when the temporal age of the first signal is not equivalent to the temporal age of the second signal.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 20, 2020
    Assignee: TheMathWorks, Inc.
    Inventors: Pieter J. Mosterman, Justyna Zander
  • Patent number: 10810563
    Abstract: Technologies are described herein for a payments portal. A payments portal can be configured to support payments by generating and embedding widgets in webpages hosted by merchant sites associated with a marketplace. The widgets can provide specific payment functionality for users, thereby providing consistent payment experiences across merchant sites without updating the merchant sites. The widgets can be dynamic or static. Interactions with the widgets can cause a browser displaying the widgets to access data hosted by the payments portal and/or other systems, devices or services in communication with the payments portal.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 20, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Alan G. Davison, Amitpal Singh Bhutani, Justin Michael Bonnar, Robert Benjamin Brydon, Bryan Christopher Castillo, Dennis Scott Doctor, Thomas L. Kovarik, Aatish S. Mandelecha, John Matthew Nienart
  • Patent number: 10803225
    Abstract: A system having design tools and methods using the same design tools in designing an integrated circuit (IC) are described.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: EFINIX, INC.
    Inventor: James Schleicher
  • Patent number: 10789403
    Abstract: Embodiments of the invention are directed to a computer-implemented method of logic verification. The method includes obtaining a netlist of a circuit comprising a plurality of observable gates. A first observable gate is grouped together with a second observable gate based on a portion of a fan-in logic of the first observable gate being equal to a portion of a fan-in logic of the second observable gate. The group is expanded by including a third observable gate, based on a first strongly connected component (SCC) in the group having a similarity greater than a first threshold to a second SCC in the fan-in logic of the third observable gate. The group is further expanded by including a fourth observable gate, based on the distance of a portion of the fan-in logic of the fourth observable gate from a fan-in logic of at least one observable gate in the group of observable gates.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rohit Dureja, Jason Raymond Baumgartner, Alexander Ivrii, Robert Kanzelman
  • Patent number: 10769330
    Abstract: A method for determining signal electromigration in a circuit includes selecting partitions from a netlist of the circuit is provided, each of the partitions including independent signal paths. The method includes determining a size of a partition, applying input vectors to a signal path in a large partition to obtain a signal toggle in an output, determining a current in the signal path, and identifying an electromigration result from the current flow. The method includes generating an output database for the partition, comprising an electromigration result for the first component, and combining the output database for the partition with a second output database from a second partition, the second output database including a second electromigration result for a second component in the second partition to generate an electromigration report for the netlist of the integrated circuit.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jalal Wehbeh, Harsh Vardhan, Federico Politi, Ajish Thomas, Aswin Ramakrishnan
  • Patent number: 10757128
    Abstract: Security policies may be utilized to grant or deny permissions related to the access of computing resources. Two or more security policies may be compared to determine whether the policies are equivalent, whether one security is more permissive than another, and more. In some cases, it may be possible to identify whether there exists a security permission that is sufficient to determine two security policies lack equivalency. Propositional logics may be utilized in the evaluation of security policies.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: John Cook, Neha Rungta, Catherine Dodge, Jeff Puchalski, Carsten Varming
  • Patent number: 10755013
    Abstract: Creating a high-level language (HLL) callable library for a hardware core can include automatically querying, using computer hardware, a metadata description of a core to determine a plurality of available ports of the core, automatically determining, using the computer hardware, an argument of a first function specified in a header file corresponding to the core, mapping, using the computer hardware, the argument to a first port of the plurality of available ports, and automatically generating and storing, using the computer hardware, an HLL library specifying a mapping of the argument to the first port of the core. The HLL library is configured for inclusion with a user application during compilation.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 25, 2020
    Assignee: Xilinx, Inc.
    Inventors: Zhenman Fang, James L. Hwang, Samuel A. Skalicky, Tom Shui, Michael Gill, Welson Sun, Alfred Huang, Jorge E. Carrillo, Chen Pan
  • Patent number: 10747930
    Abstract: An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 18, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10740519
    Abstract: The disclosure is directed to the design and manufacture of synchronous digital systems, such as integrated circuits (IC), to employ dynamic frequency boosting. The proposed technique overcomes limitations of conventional synchronous clock design by boosting operating clock frequency despite critical path time constraints and without violating the correct functionality. In accordance with an exemplary embodiment, ICs are configured to set the clock frequency during each state event by selecting a more optimum clock frequency, on a clock cycle basis, thus improving system performance in terms of throughput while maintaining the benefits and design approach of synchronous digital systems.
    Type: Grant
    Filed: July 8, 2017
    Date of Patent: August 11, 2020
    Assignee: TRIMSIGNAL IP LLC
    Inventor: Nikolaos Zompakis
  • Patent number: 10740517
    Abstract: Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a generalized refactoring engine which supports multiple representation forms and (v) a Boolean resynthesis flow, which combines these techniques.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 11, 2020
    Assignee: Synopsys, Inc.
    Inventors: Luca Gaetano Amaru, Patrick Vuillod, Jiong Luo
  • Patent number: 10740518
    Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10732971
    Abstract: A method for generating dynamical systems that can be instantiated on reconfigurable computing platforms for solving instances of the Boolean satisfiability problem (SAT) is disclosed. When the SAT instance can be satisfied by an appropriate assignment of the variables, the dynamical system has a fixed point attractor that corresponds to a satisfying assignment of variables. When the SAT instance cannot be satisfied by any assignment of variables, there is no such fixed point attractor. Exemplary embodiments represent a physically-realizable computing device that solves SAT problems outside the Turing machine paradigm. Exemplary embodiments detect when the system reaches a fixed point attractor.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 4, 2020
    Inventor: Andrew Pomerance
  • Patent number: 10715038
    Abstract: A circuit includes a first TSCP (tri-stage charge pump), a second TSCP, a third TSCP, a fourth TSCP, a fifth TSCP, and a load. The first TSCP receives a first phase and a third phase of a five-phase clock and outputs a first current to an output node. The second TSCP receives a second phase and a fourth phase of the five-phase clock and outputs a second current to the output node. The third TSCP receives a third phase and a fifth phase of the five-phase clock and outputs a third current to the output node. The fourth TSCP receives a fourth phase and the first phase of the five-phase clock and outputs a fourth current to the output node. The fifth TSCP receives a fifth phase and the second phase of the five-phase clock and outputs a fifth current to the output node. The load terminates the output node.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: July 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10699795
    Abstract: A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 30, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Norman Card, Steven Lee Gregor
  • Patent number: 10698661
    Abstract: According to at least one aspect, a system for collecting computer usage information is provided. The system includes a hardware processor, a display coupled to the hardware processor to display a user interface, and a computer-readable storage medium storing processor-executable instructions that cause the hardware processor to receive an indication of an action being performed by a user on the system, gather contextual information associated with the action responsive to the action performed by the user, store information indicative of the action and the contextual information in a volatile memory as an event, determine whether at least one event stored in the volatile memory includes personal information of the user, and write the at least one event stored in the volatile memory to an event log in a non-volatile memory responsive to a determination that the at least one event does not include personal information of the user.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: June 30, 2020
    Assignee: Soroco Private Limited
    Inventors: Yoongu Kim, Abdul Qadir, Arjun Narayanaswamy, Rohan Narayan Murty, Shane Barratt, George Peter Nychis
  • Patent number: 10665553
    Abstract: A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: May 26, 2020
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Liwei Li, Yuejun Zhang, Bo Chen, Gang Li
  • Patent number: 10664035
    Abstract: In certain aspects, an integrated circuit comprises a first circuit macro having a first power delivery network, a second circuit macro having a second power delivery network. The integrated circuit further comprises a coupling circuit couples to the first power delivery network and to the second power delivery network.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 26, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Mikhail Popovich, Juan Sebastian Ochoa Munoz
  • Patent number: 10664564
    Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 26, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier A Delacruz, Eric Nequist, Jung Ko, Kenneth Duong
  • Patent number: 10635843
    Abstract: A method for enabling user-customization of a controller design for simulation comprises accessing at least one library of individual simulation component models for controller components. The method further comprises receiving information describing an architecture of a customized controller design corresponding to a controller that controls communications between other parts of a first target system. The method additionally comprises generating a controller simulation model for the customized controller design based on the first architectural information, the controller simulation model including instances of a plurality of the simulation component models.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: April 28, 2020
    Assignee: Synopsys, Inc.
    Inventors: Amit Garg, Ashutosh Pandey, Nitin Gupta
  • Patent number: 10628544
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Patent number: 10614187
    Abstract: An exemplary system, method and computer-accessible medium can be provided which can include, for example, generating a super control dataflow graph(s) (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit, determining an upper bound(s) number and a lower bound(s) number based on a number of CDFGs in the super CDFG(s)—with each number being one metric of a capability of the integrated circuit to resist reverse engineering attack—, and inserting a component(s) into a register transfer level netlist to effectuate a modification of the upper bound(s) and the lower bound(s).
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 7, 2020
    Assignee: New York University
    Inventors: Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
  • Patent number: 10614260
    Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 7, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsiu Tsai, Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Patent number: 10606558
    Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 31, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Patent number: 10586007
    Abstract: A multi-dimensional placement methodology, system and computer readable medium is presented. A plurality of data sets is ordered by need. A plurality of storage areas are defined based on a storage device type, an associated compression algorithm, and a plurality of parameters associated with different properties of the particular storage device and the compression algorithm being used. A data set is placed in a selected storage area based on a determination of which storage area provides a desired combination of the storage device type and compression.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 10, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Ron Bigman
  • Patent number: 10572624
    Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Erez Barak, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach
  • Patent number: 10568203
    Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ofer Geva, Shiran Raz, Limor Elizov, Yaniv Maroz
  • Patent number: 10558774
    Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for generating electronic design element symbols for electronic circuit design tool libraries and designs in any desired format. In embodiments, such electronic design element symbols can be generated from a datasheet or any other image using image processing, graphical shape and text recognition techniques. Embodiments use step by step processing to extract feature vectors from a symbol/design image, apply text and graphical shapes recognition using models, apply techniques for data association and write the final output for targeted systems. These and other embodiments can feed back the output data for further refinement of the recognition models.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 11, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Hitesh Mohan Kumar, Raghav Sharma
  • Patent number: 10554496
    Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 4, 2020
    Assignee: NetSpeed Systems
    Inventors: Eric Norige, Sailesh Kumar
  • Patent number: 10540468
    Abstract: A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Raj Kumar Gajavelly, Jason R. Baumgartner, Robert L. Kanzelman, Alexander Ivrii, Pradeep Kumar Nalla
  • Patent number: 10540469
    Abstract: A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware design model configured to receive a startup state and send digital output values. Hardware processor(s) are used for generating a plurality of initial states. Hardware processor(s) are used for computing, using each one of the first and second hardware design models, at least one specific output value for each one of the plurality of initial states. Hardware processor(s) are used for selecting corresponding initial states that produce equivalent at least one specific output value between the first hardware design model and the second hardware design model. Hardware processor(s) are used for storing the selected corresponding initial states as mappings between the first hardware design model and the second hardware design model.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Ivrii, Haim Kermany, Ziv Nevo
  • Patent number: 10515173
    Abstract: An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 24, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David A. Roberts, Dean Gonzales
  • Patent number: 10503504
    Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: December 10, 2019
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
  • Patent number: 10496772
    Abstract: Disclosed herein are embodiments for generating hierarchical rotating pcells (parametrized cells) design from a user provided static hierarchical design. An EDA (Electronic Design Automation) tool may receive a hierarchical static design and allow the user to instantiate a top level hierarchical rotating pcell using one or more parameters including an angle parameter to indicate a rotation angle. Based on the one or more parameters, the EDA tool may recursively identify, in the user's static hierarchical design, lower level static cells and replace them with the hierarchical rotating pcells based on the angle parameter in the already instantiated upper level hierarchical rotating pcells. The EDA tool may instantiate and re-instantiate hierarchical rotating pcells until leaf-level cells have been reached to dynamically generate an IC (integrated circuit) design with hierarchical rotating pcells from the user's static hierarchical design such that rotation can be accomplished without flattening the IC design.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Jean-Noel Pic
  • Patent number: 10496767
    Abstract: The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse response characterization, wherein the random input pattern is based upon, at least in part, an electronic circuit simulation associated with the electronic circuit design.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Hui Qi, Kenneth Robert Willis, Xuegang Zeng
  • Patent number: 10489541
    Abstract: Disclosed approaches for translating a hardware description language (HDL) specification include inputting an HDL specification of a circuit design, generating a design graph of the circuit design from the HDL specification, and determining matches between modules of the HDL specification and blocks in a library. The design graph is translated into a data model that describes matching blocks, interfaces from the library, and connections between the blocks based on the matches determined between modules of the HDL specification and blocks of the library. The data model is compatible with a graphical design environment.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 26, 2019
    Assignee: XILINX, INC.
    Inventors: Anindita Patra, Nabeel Shirazi
  • Patent number: 10460060
    Abstract: A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 29, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Or Davidi, Roy Armoni
  • Patent number: 10460069
    Abstract: Electronic design automation systems and methods for functional reactive parameterized cells (FR-PCells) are described. In one embodiment, a PCell includes a reactive parameter that is based on context information regarding other cells or elements of an overall circuit design. Processing of the FR-PCell may then depend on processing of other PCells or other elements of a circuit design. Similarly, an FR-PCell may provide context information to other FR-PCells. In some embodiments, processing of an FR-PCell to generate an instance of the FR-PCell is managed by a reaction engine that monitors updates to context information or other PCells to automatically adjust instances of the FR-PCells.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 29, 2019
    Assignees: Cadence Design Systems, Inc., Robert Bosch GmbH
    Inventors: Thomas Burdick, Peter Herth, Göran Jerke, Christel Bürzele, Daniel Marolt, Vinko Marolt
  • Patent number: 10445461
    Abstract: The present disclosure provides a method to maximize the overall chip yield. This method combines a PV-aware deterministic circuit sizing process with a hybrid OPC operation, and integrates them into an analog layout migration platform, which attempts to efficiently compose a layout by inheriting knowledge from a legacy layout and imposing new specifications, circuit sizing and constraints. The present method provides a sizing process, which explores robust circuit sizes under different PV conditions, especially considering mismatch effects on sensitive analog devices. The analog layout migration is conducted along the sizing flow for efficient layout synthesis with a unique benefit to better evaluation of the PV-related post-layout effects. After finishing the sizing process, a hybrid OPC operation, which adopts global rule-based OPC and local model-based OPC along with the PV-band shifting, is performed as a post-processing step.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 15, 2019
    Inventors: Lihong Zhang, Xuan Dong
  • Patent number: 10436841
    Abstract: A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 8, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Ido Bourstein, Ofer Shalev
  • Patent number: 10432405
    Abstract: Systems and methods related to processing transaction verification operations in decentralized applications via a fixed pipeline hardware architecture are described herein. The fixed pipeline hardware architecture may include and/or support at least a crypto engine and a read set validation engine. The crypto engine may itself comprise a hardware architecture configured to perform cryptographic operations necessary to validate signatures for transactions in decentralized applications. In various implementations, the hardware architecture of a crypto engine may include a scheduler and a series of crypto execution units configured to operate in parallel. The scheduler may be configured to decode an algorithm associated with cryptographic signatures to be verified and coordinate the performance of various cryptographic operations amongst individual cryptographic execution units.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 1, 2019
    Assignee: Accelor Ltd.
    Inventors: Shiwen Hu, Xiaohan Ma, Guojun Chu