Abstract: A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Abstract: This application discloses a design verification tool to generate an interconnect between portions of a circuit design in a mixed language environment. The design verification tool can select an interconnect generation technique based on characteristics for the portions of the circuit design and, during elaboration of the circuit design, utilize the selected interconnect generation technique to generate the interconnect. The design verification tool can generate the interconnect without the circuit design including code to identify the selected interconnect generation technique to the design verification tool. The design verification tool can perform functional verification operations on the elaborated circuit design, and modify results of the functional verification operations to remove an intermediate hierarchy utilized to generate the interconnect during elaboration. The modified results can show the portions of the circuit design being directly connected by the interconnect.

Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.

Abstract: The present invention is to provide an automatic IP core generation system that can reduce the loads on both an IP core vendor and a user. The present invention provides an automatic IP core generation system that generates an IP core in accordance with parameter information input from a user. The automatic IP core generation system includes: a parameter acquisition unit that acquires the parameter information; a meta IP core information storage unit that stores a meta IP core model as a model for generating various IP cores; a component library information storage unit that stores a component to be used in the IP core and the meta IP core model; an IP core generation unit that generates a package containing the IP core in accordance with the parameter information; and a package output unit that outputs the package.

Abstract: This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.

Abstract: A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.

Abstract: Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.

Abstract: An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.

Abstract: A method of simulating an electronic circuit including an N-stage charge pump includes generating a charge pump macro model corresponding to the N-stage charge pump, and simulating the charge pump macro model. The charge pump macro model includes an output terminal, a behavioral block defined by a modeling language, and a passive device block including at least one passive device connected to the output terminal and the behavioral block.

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.

Abstract: Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

Abstract: A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

Abstract: An apparatus for performing multi-tier domain pre-characterization for floating random walk capacitance extraction of a semiconductor structure includes a processor configured to recursively execute a floating random walk algorithm, over a plurality of points for a plurality of conductors, to permit determination of a potential at a plurality of points on a Gaussian surface around each of a plurality of conductors and determination of a coupling capacitance between the plurality of conductors, each iteration of the floating random walk algorithm comprising selection of a domain about an initial boundary point on the Gaussian surface of the respective one of the plurality of conductors and determination of a new boundary point on the new domain, from which a successive boundary point is selected with a corresponding successive domain centered thereabout, this process continuing until a corresponding successive domain terminates at a boundary having a known potential, whereupon the processor determines the pote

Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.

Abstract: In one embodiment, a device generator automatically generates a circuit, firmware, and assembly instructions for a programmed electronic device based on behaviors that are specified via mappings between triggers and actions. In operation, the device generator generates a circuit based on the mappings. The circuit specifies instances of electronic components and interconnections between the instances. Subsequently, the device generator generates firmware based on code fragments associated with the triggers and actions included in the mappings that specify the high-level behavior. In addition the device generator generates assembly instructions based on the interconnections between the instances. Advantageously, the device generator provides an automated, intuitive design process for programmed electronic devices that does not rely on the designers possessing any significant technical expertise.

Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.

Abstract: According to one general aspect, a method may include receiving a digital circuit model. The digital circuit model may include models of a clock mesh configured to provide a clock signal to a plurality of logic circuits, and a plurality of logic circuits, each logic circuit at least partially controlled by an application of the clock signal to one or more clock-gater cells. The method may include identifying a group of clock-gater cells having common input signals. The method may include calculating at least one clustered sub-portion of the group of clock-gater cells based upon a set of bounding dimensions, wherein each clustered sub-portion includes a plurality of clock-gater cells. The method may further include, for each clustered sub-portion, de-cloning in the digital circuit model the clock-gater cells by reducing the clock-gater cells to a new clock-gater cell and replacing the each clock-gater cell with a matching buffer cell.

Abstract: A method for simulating an integrated circuit design is provided. The method includes forming a partition of an IC netlist into blocks based on a performance value from at least a portion of a parameter space and forming a table with parameter values including multiple instances of at least one block of the partition. The computer-implemented method also includes analyzing a direct-current (DC) solution of at least one block by combining at least a first instance of a first block with a second instance of a second block based on the performance value from the portion of the parameter space, and performing a transient analysis where signals change over time for the at least one block.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: A scheduling result file (103) indicates that one or more processes are assigned to each of a plurality of process steps to be executed sequentially. A target specification section (120) specifies a target process that is a process performing computation and an identical-type process that is a process assigned to a process step executed after a process step to which the target process has been assigned and performing computation which is identical in type to the target process among processes in the scheduling result file. A destination specification section (130) specifies, as a destination step, a process step that enables a computing unit to be shared between the target process and the identical-type process when the target process is assigned. A scheduling change section (150) changes description of the scheduling result file to description in a state in which the target process has been assigned to the destination step.

Abstract: A method of managing memory in a network of nodes includes identifying memory resources for each of the plurality of nodes connected to the network, storing memory resource information describing the memory resources, and based on the stored memory resource information, allocating a portion of the memory resources for execution of instructions in a workload, where at least a first node of the plurality of nodes is configured to execute the workload using the allocated portion of the memory resources.

Abstract: In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.

Abstract: This disclosure relates generally to Very Large Scale Integrated (VLSI) chips and more particularly to methods and systems for reducing congestion in VLSI chip design. In one embodiment, a method includes applying a placement constraint with at least one hot-spot logic cell, wherein the placement constraint restricts placement of new logic cells within a predefined distance from each of the at least one hot-spot logic cell; applying a routing constraint on a metal layer in a node of the VLSI chip, wherein the node includes the at least one hot-spot logic cell; and restricting fresh placement of the post route database of the at least one hot-spot logic cell to original location extracted using feedback received after culmination of routing procedure while applying the placement constraint and the routing constraint.

Abstract: The present invention provides an image processing package comprising: an image sensor for receiving an image of a subject, which is incident from the outside, in the form of light and converting the image of the subject into an image signal; and an image signal processor for processing the image signal which is output from the image sensor and reproducing the image of the subject, wherein the image processing package has a structure in which the image sensor is vertically stacked on the image signal processor.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

Abstract: A programmable logic device such as an integrated circuit may receive user-defined configuration data from a circuit design system. The user-defined configuration data may include a minimal number of user-defined configuration variables necessary to configure the programmable logic device when combined with hardware-defined configuration variables generated in resolution engines in the programmable logic device based on the user-defined configuration variables. The resolution engines may process multiple hardware-defined configuration variables simultaneously and in parallel. A temporary storage device in the programmable logic device may store the user-defined configuration variables, the hardware-defined configuration variables, and preloaded configuration data. The resolution engines may generate a configuration bitstream to configure a configuration random access memory on the device using the configuration data stored on the temporary storage.

Abstract: A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer; selecting one member of the possible values set to be the first pitch; and placing standard spare cells into a logic area of the layout according to the first pitch; wherein at least one of the generating, selecting and placing is executed by a processor of a computer.

Abstract: A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.

Abstract: A device includes first circuit cells. Each of the first circuit cells includes isolation transistors, a first type transistor, a second type transistor, and a first gate contact. The isolation transistors are arranged adjacent to another one circuit cell of the plurality of first circuit cells. The first type transistor includes a first gate electrode. The second type transistor includes a second gate electrode, in which the second gate electrode is disposed with respect to the first gate electrode. The first gate contact is coupled between the first gate electrode and the second gate electrode.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.

Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.

Abstract: One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

Abstract: An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.

Abstract: Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Abstract: A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the physical memory, associations of physical memories with the logical memory, enabling conditions, and data needed to test the memory.

Abstract: A computing device configured to execute an instruction set is provided. The computing device includes a system call hooker for hooking system calls that occur by the instruction set while the instruction set is executed, a category extractor for extracting a category to which each of the hooked system calls belongs with reference to category information associated with a correspondence relationship between a system call and a category, a sequence extractor for extracting one or more behavior sequences expressed in an N-gram manner from a full sequence of the hooked system calls with reference to the extracted category, and a model generator for generating a behavior pattern model of the system calls that occur when the instruction set is executed, based on a number of times that each of the extracted behavior sequences occurs.

Abstract: In examples described herein, methods for via pillar placement and an integrated circuit design including a via pillar are described. In some instances, a path within an integrated circuit or proposed integrated circuit design can be identified as having negative slack. In such instances, in particular where the path includes a fanout to input pins of receivers, a via pillar can be inserted at a location prior to fanout of the path. The via pillar can be inserted, for example, proximate to the fanout, but between the fanout and an output pin of a driver that is connected to the path.

Abstract: A source/drain epitaxial electrical monitor and methods of characterizing epitaxial growth through capacitance measurements are provided. The structure includes a plurality of fin structures; one or more gate structures, perpendicular to and intersecting the plurality of fin structures. The structure further includes a first connection by a first contact at one fin-end of every other fin structure of the plurality of fin structures, and a second connection by a second contact at one end of an alternate fin structure of the plurality of fin structures.

Abstract: A method of designing an acoustic microwave filter in accordance with frequency response requirements.

Abstract: A computer system may obtain a first schematic design netlist for a first IC design and a second schematic design netlist for a second IC design. The computer system may normalize the first netlist and the second netlist. The computer system may determine that the normalized first netlist is the same as the normalized second netlist. The computer system may obtain a first layout design data for the first IC design and a second layout design data for the second IC design. The computer system may determine that the first layout data is the same as the second layout data. The computer system may copy a sign-off data of the first IC design to the second IC design.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: In one general aspect, a method can include receiving at least one set of correction instructions, validating the at least one set of correction instructions for use by a debugger when debugging an application program, and generating a debug script. The debug script can include text for automatically implementing the validated at least one set of correction instructions in the debugger when debugging an application program. The method can further include generating a plurality of data structures for use by the debug script based on the validated at least one set of correction instructions, and outputting the debug script to the debugger for use by the debugger when debugging the application program.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: A method displays documentation about a machine on a preferably portable display device. The method is distinguished by the fact that the display device communicates with the machine via a data link. The portable display device communicates with the machine via a data link and the documentation contains partial items of documentation. The states of the machine are registered by a computer of the machine, and that the parts of the documentation matching the registered machine states are selected automatically and displayed on the display device.

Abstract: Methods and systems are disclosed for placement and routing of a circuit design. A set of timing constraints is retrieved that specifies timing for objects included in a first shell circuit design configured to provide an interface for communication between the circuit design and the set of dedicated hardware resources on an IC. One or more objects of the first shell circuit design that do not affect timing of the circuit design are identified and removed from the first shell circuit design to produce a second shell circuit design. The circuit design is placed and routed according to timing constraints specified for objects of the first shell circuit design that are included in the second shell circuit design. The placed and routed circuit design is stored in a memory circuit.