Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

Abstract: Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.

Abstract: A digital circuit for accelerating computations of an artificial neural network model includes a pairs selection unit that selects different subsets of pairs of input vector values and corresponding weight vector values to be processed simultaneously at each time step; a sorting unit that simultaneously processes a vector of input-weight pairs wherein pair values whose estimated product is small are routed with a high probability to small multipliers, and pair values whose estimated product is greater are routed with a high probability to large multipliers that support larger input and output values; and a core unit that includes a plurality of multiplier units and a plurality of adder units that accumulate output results of the plurality of multiplier units into one or more output values that are stored back into the memory, where the plurality of multiplier units include the small multipliers and the large multipliers.

Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

Abstract: Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

Abstract: Techniques and systems for solving Boolean satisfiability (SAT) problems are described. Some embodiments solve SAT problems using efficient construction of truth tables. Some embodiments can improve performance of SAT solvers by using truth tables instead of incurring the overhead of Conjunctive Normal Form (CNF) conversion.

Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor that creates module partitioning candidates of a plurality of software codes including one or more input nodes from a plurality of input nodes in a data flow graph and calculates a cost corresponding to a bit width of a signal line of the module partitioning candidates for each of the created plurality of module partitioning candidates, and selects one or more module partitioning candidates having a given cost from the plurality of module partitioning candidates as a partitioning target module based on the calculated cost.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Abstract: A method for constructing a parameterized quantum circuit according to an embodiment includes inputting learning data to a quantum circuit, receiving output data for the learning data from the quantum circuit and calculating an error rate therefrom, and updating, based on the error rate, parameters for at least one sub-circuit block to be updated among one or more sub-circuit blocks included in the quantum circuit.

Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

Abstract: Systems and methods to place latches during hierarchical integrated circuit development obtain an initial floor plan indicating a blocked region, two or more regions, and initial locations of components including the latches. A method includes identifying a subset of the latches that belong to a vector as a vector of latches, the subset of the latches being single-bit latches that must be placed in a same one of the two or more regions, and identifying a center of gravity (COG) of the vector of latches, the COG being a mean of geometric points corresponding with the subset of the latches. All of the subset of the latches are placed at the COG to generate an intermediate floor plan based on determining that the COG is not in the blocked region. A final design of the integrated circuit that is obtained based on the intermediate floor plan is provided for fabrication.

Abstract: A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Abstract: A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.

Abstract: The disclosure provides a compilation method and system for heterogeneous computing platform, and a runtime method and system for supporting program execution on the heterogeneous computing platform. Inputting a trained neural network model to a Neural Network (NN) optimizing compiler to generate an NN assembly file corresponding to the neural network; inputting the NN assembly file to an NN assembler to generate an NN binary file corresponding to the neural network; compilation and assembling a neural network application developed by users in a high-level language using a host compiler toolchain to generate a corresponding host assembly file and a host binary file in sequence; and linking the NN binary file and the host binary file using a host linker to generate a single hybrid linking executable file. The technical solution of the present disclosure has the advantages such as good computing performance, strong scalability, strong compatibility and high flexibility.

Abstract: A method for establishing sensorimotor programs includes specifying a concept relationship that relates a first concept to a second concept and establishes the second concept as higher-order than the first concept; training a first sensorimotor program to accomplish the first concept using a set of primitive actions; and training a second sensorimotor program to accomplish the second concept using the first sensorimotor program and the set of primitive actions.

Abstract: Using high level synthesis (HLS) and linked hardware description language (HDL) libraries to implement a circuit design includes generating, using computer hardware, a data flow graph from a model that includes an HDL model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code, and dividing, using the computer hardware, the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block. Using the computer hardware, a first HDL core is generated from the first sub-graph, synthesizable program code is generated form the second sub-graph, HLS is performed on the synthesizable program code to generate a second HDL core, and the circuit design is generated including the first HDL core connected to the second HDL core.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing physical synthesis with an overall placement process. One of the methods includes receiving an initial netlist of a circuit design for an IC. A global placement process is performed that assigns to some components in the initial netlist a respective initial location on the IC. One or more physical synthesis processes are performed to generate a modified netlist before assigning a final location to all components in the circuit design by an overall placement process. A subsequent placement process is performed to assign a final location on the IC to all components in the modified netlist.

Abstract: Method and apparatus for global routing optimization are provided herein. Optimizing global routing of a circuit, includes recursively generating, in parallel, a plurality of candidate wiring layouts for an integrated circuit, wherein each candidate wiring layout of the plurality of candidate wiring layouts corresponds to a respective parameter super-group of a plurality of parameter super-groups, wherein the plurality of parameter super-groups form a parameter set; calculating a Quality of Result (QoR) measure for each candidate wiring layout in an iteration; combining selected parameter super-groups of the iteration, based on the QoR measure, to form a new plurality of parameter super-groups for a next iteration; and determining a best parameter super-group from the parameter sets for use in globally routing the circuit.

Abstract: Data is received that characterizes a software system. Thereafter, a threat model is generated, using at least one machine learning model, that optimally characterizes cybersecurity threats associated with the software system and provides security measures to counter such threats. The at least one machine learning model is trained using a plurality of historically generated threat models for a plurality of differing software systems. Subsequently, data can be provided that includes or otherwise characterizes the generated threat model.

Abstract: A current fingerprint that is a function of an operation node and an input storage node is generated. The current fingerprint is compared to a previously generated fingerprint associated with an output storage node and a task associated with performing the operation node on the input storage node is generated.

Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.

Abstract: Computer-implemented methods can transform a corpus of meaningful text sequences into a generalized computer-usable repository of neurolinguistic information that can be applied by one or more computer systems. The computer system(s) can use the neurolinguistic information to neurolinguistically analyze meaningful text sequences to derive statistical information and identify dominant cognitive motivation orientations expressed in those text sequences. The identified dominant cognitive motivation orientations can be used to improve the efficacy of both human-generated and machine-generated communications. The computer system(s) thereby transform a meaningful text sequence into actionable information about the dominant cognitive motivation orientation(s) of the author of that text sequence within the context in which the text sequence was composed. Computer systems and computer-program products for implementing the methods are also described.

Abstract: Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based on the logic-function identifier and the arrival-time-pattern identifier to obtain an optimized combinational-logic-cone. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Abstract: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to include only those designated cover cells. Non-designated cover cells and other geometric data are flattened into the designated cover cells. The hierarchy of the modified file is then redefined to be less than or equal to the hierarchy limit of the mask writing tool.

Abstract: An emulation environment includes a host system and an emulator. The host system configures the emulator to load a design under test (DUT) and the emulator emulates the DUT. The emulator includes one or more design field-programmable gate arrays (FPGAs) that emulate the DUT. In addition, the emulator includes at least one system FPGA with a logic analyzer and multiple virtual FPGA. The virtual FPGAs emulate sections of the DUT. By the virtual FPGAs emulating sections of the DUT, the logic analyzer is able to obtain for performing logic analysis certain signals from the virtual FPGAs, rather than from the design FPGAs.

Abstract: On-chip data transport network architectural units are assigned preferred placement locations based on architecture-level constraints. The preferred placement locations are used to generate placement constraints for a place and route tool. The placement constraints are applied to cells that are synthesized from each architectural unit. Constraints are blockages, fences, regions, and guides. Preferred placement locations are mapped to grid elements. Each grid elements defines a cell placement constraint.

Abstract: A method and system of merging one-bit cells in an integrated circuit layout, comprising a database to store the layout, a placer in communication with the database to update the layout, and a merger in communication with the placer. The merger is configured to: identify a set of one-bit cells in the integrated circuit layout; determine a set of merge cells, from among the identified set of one-bit cells, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and generate instructions to the placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.

Abstract: A workflow interpreter service that interprets a workflow definition language for specifying a workflow definition. Further, the workflow definition language provides features for maintaining control over data flows for data that is passed from one state to another among states of a state machine for a workflow. Such control over data flow in between states allows for a given workflow to be processed incrementally, and among multiple different computing resources.

Abstract: An information processing system includes a optimal-load arrangement means containing a load analysis means, a load distribution means, and program information. The load-computation execution means contains a hardware processing means and a software computation means. The program information includes resource information and information pertaining to data to be processed and the content of the processing to be performed thereon. The load analysis means has the ability to perform community assignment in which, of the data to be processed, data in regions having heavy loads and communication volumes that can be reduced is assigned to a hardware community and data in other regions is assigned to a software community. The load distribution means divides up the data to be processed such that the data assigned to the hardware community is processed by the hardware processing means and the data assigned to the software community is processed by the software computation means.

Abstract: A method is provided for allowing process overruns while guaranteeing satisfaction of various timing constraints. At least one latest start time for an uncompleted process is computed. If an uncompleted process does not start at its latest start time, then at least one of the predetermined constraints may not be satisfied. A timer is programmed to interrupt a currently executing process at a latest start time. In another embodiment, information about ordering of the end times of the process time slots in a pre-run-time schedule is used by a run-time scheduler to schedule process executions. Exclusion relations can be used to prevent simultaneous access to shared resources. Any process that does not exclude a particular process is able to preempt that particular process at any appropriate time at run-time, which increases the chances that a process will be able to overrun while guaranteeing satisfaction of various timing constraints.

Abstract: A system, method and software product shares a software design. A design sharer having machine readable instructions stored within memory of a development server and executable by a processor of the development server interacts with a first user to select a first portion of a first hierarchical software design. The design sharer saves the first portion within a public workspace. The design sharer interacts with a second user having access to the public workspace to select the first portion and inserts the first portion into a second hierarchical software design.

Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.

Abstract: A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second, and third netlists. Incremental placement and routing are performed on portions of the hybrid netlist that are new to the first compilation.

Abstract: Computer-implemented methods can transform a corpus of meaningful text sequences into a generalized computer-usable repository of neurolinguistic information that can be applied by one or more computer systems. The computer system(s) can use the neurolinguistic information to neurolinguistically analyze meaningful text sequences to derive statistical information and identify dominant cognitive motivation orientations expressed in those text sequences. The identified dominant cognitive motivation orientations can be used to improve the efficacy of both human-generated and machine-generated communications. The computer system(s) thereby transform a meaningful text sequence into actionable information about the dominant cognitive motivation orientation(s) of the author of that text sequence within the context in which the text sequence was composed. Computer systems and computer-program products for implementing the methods are also described.

Abstract: A method for generating a design for a system implemented on a target device includes presenting a user with an interface that allows the user to weight objectives for an interconnect architecture of the design. The interconnect architecture is generated in response to weighted objectives provided by the user.

Abstract: Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

Abstract: Computational techniques for mapping a continuous variable objective function into a discrete variable objective function problem that facilitate determining a solution of the problem via a quantum processor are described. The modified objective function is solved by minimizing the cost of the mapping via an iterative search algorithm.

Abstract: An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based on the reference frequency and a clock generator that receives the local reference clock signal and generates local design clocks based on the local reference clock signal. Because each local design clock generator is synchronized by the same reference clock over a low skew line, the edges of the local design clocks are aligned.

Abstract: Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

Abstract: One or more artifact drafts may be associated with each of a plurality of artifacts, each of the artifact drafts representing a state of the associated artifact at a point in time and one or more commands in a command stack that transformed the artifact draft's parent into the artifact draft. Multiple traceability links and traceability vertices represent connections between the artifact drafts of the artifacts. A traceability link includes an edge between an artifact draft of an artifact and an artifact draft of another artifact. A module is operable to navigate through said one or more artifacts of the plurality of artifacts from a reference temporal point via the plurality of traceability links.

Abstract: Aspects of the invention relate to techniques for using retiming to reduce circuit switching activity. Switching activity values at output ports of circuit elements of a circuit design are first computed based on switching activity values at input ports of the circuit elements and scaling factors associated with the circuit elements. Based on the switching activity values at the output ports of the circuit elements, one or more regions of the circuit design for retiming are identified. Retiming location information is then determined for the one or more regions. Finally, the identified one or more regions are then retimed to reduce switching activity based on the retiming location information.

Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.