Abstract: A static verification program according to the present invention reads a circuit description and property. In a static verification step, static verification of the circuit description is performed on the basis of the property and the number of states that can be reached and the number of states that is reached are calculated. In a search coverage value calculation step, a search coverage value is calculated on the basis of the number of states that can be reached and the number of states that is reached. In a display step, the search coverage value is displayed in a state in which the search coverage value can be visually checked.

Abstract: One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.

Abstract: An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.

Abstract: A simulation method, to be implemented in a computer, carries out a simulation of a semiconductor integrated circuit. The simulation method carries out a layout analysis based on layout data of a circuit formed by cells and stores values of layout parameters obtained by the layout analysis. Basic cell characteristics of the cells are read from a net list representing the extracted basic cell characteristics by the layout parameters and the basic cell characteristics represented by the layout parameters are stored. The stored values of the layout parameters are read and substituted into the basic cell characteristics represented by the layout parameters to obtain cell characteristics, and the cell characteristics are stored. An operation of the circuit is analyzed using the cell characteristics that are obtained.

Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.

Abstract: Simulating an application. A method that may be practiced in a computing environment configured for simulating an application modeled by an application model deployed in a performance scenario of a computing system by deploying service models of the application model to device models modeling devices. The method includes referencing a performance scenario to obtain a transaction being modeled as originating from a first device model. The transaction invokes of a first service model. The first service model specifies hardware actions for simulation. The first service model is referenced to determine the hardware actions for simulation and the next referenced service. The next referenced service specifies hardware actions to be added to the transaction and may specify invocation of other service models. A chain of hardware actions is generated by following the invocation path of the service models. The hardware actions are applied to device models to simulate the transaction.

Abstract: A maximum delay of a combinational circuit is accurately reduced in consideration of a correlation between variations in delays of devices (transistors etc.) and interconnects. Circuit modification candidate information about a circuit modification candidate for improving a delay of a circuit to be designed is generated based on circuit information about the circuit to be designed, technology information about a distribution of a characteristic of a device and/or an interconnect based on a process to be designed, delay distribution information about a distribution of the delay in the circuit to be designed, and delay correlation information about a correlation between variations in the delay in the circuit to be designed.

Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit elements(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

Abstract: Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.

Abstract: A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.

Abstract: A method of designing an asynchronous integrated circuit is provided. A global clock network of a synchronous circuit is replaced with a plurality of handshaking circuits. Data validity is encoded into a communication path between a first pipeline stage and a second pipeline stage of the synchronous circuit. A control logic for the first pipeline stage is implemented using a template that contains characterization information for timing to generate an asynchronous circuit design.

Abstract: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Abstract: A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

Abstract: A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a sequential circuit to be verified and a timing specification that indicates a timing constraint in the hardware description; converting the hardware description into a control flow graph that expresses a flow of control in the sequential circuit; indentifying, from the control flow graph and as a combination of conditional branch descriptions having a hierarchical relation, conditional branch descriptions that are connected in parallel; extracting, from among identified combinations of conditional branch descriptions, a combination having a potential to satisfy specified conditions; creating a simulation program that, at a timing satisfying the timing specification, causes the conditional branch descriptions included in the extracted combination to satisfy the specified conditions; and outputting, as assertion information of the sequential circuit, the simu

Abstract: A method and systems are provided for screening and rapid evaluation of routed nets in a post-layout circuit environment, such as in the design of printed circuit boards. A portion of nets are selected for determination of associated signal quality factors. Signal channels containing one or more selected nets are then built. A reference input stimulus is propagated along each of the signal channels in a frequency based simulation for generating characteristic responses of the selected nets' signal channels. A signal channel quality factor is obtained for each signal channel based upon its characteristic response. The signal channels and their nets are then comparatively analyzed according to corresponding signal channel quality factors to selectively identify any aberrant nets warranting supplemental evaluation for faults.

Abstract: A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design.

Abstract: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.

Abstract: Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems.

Abstract: A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.

Abstract: A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.

Abstract: An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level being smaller than the first reference level; a redesign module adapted to redesign the target circuit when at least one of the variations of the power supply voltages is larger than the first reference level; a delay variation calculation module adapted to correct circuit delay data of the respective instances based on the variations of the power supply voltages of the respective instances; a static timing analysis tool performing timing verification of the target integrated circuit.

Abstract: A behavioral synthesis system has a scheduling unit and a mode control unit. The scheduling unit performs scheduling of a behavioral level description with reference to a resource quantity data indicating resource constraint and a resource delay data indicating delay times of respective resources. A single process described in the behavioral level description is divided into a plurality of description blocks, and a scheduling mode among a plurality of scheduling modes is designated with respect to each of the plurality of description block. The mode control unit refers to a mode designation code that indicates the designated scheduling mode and controls such that the scheduling unit performs the scheduling with respect to each description block in accordance with the designated scheduling mode indicated by the mode designation code.

Abstract: An iterative method for generating a series of output signal values from a series of input signal values is described. Iterations of the method comprise the steps of obtaining a current input signal value for the current iteration, comparing the current input signal value with an output signal value determined in a previous iteration, updating a counter value determined in the previous iteration based on the result of the comparison between the current input signal value and the previous output signal value such that the updated counter value replaces the counter value determined in the previous iteration, determining a slew value based on the counter value; and adding the slew value to the previously determined output signal value to generate a new current output signal value. Thus different slew values may be added to the previous output signal to obtain a new output signal. The counter value is updated so that its value reflects recent trends in the input signals. E.g.

Abstract: The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Abstract: An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing analysis based on the selected maximum voltage and the selected minimum voltage. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., a delay between an input change to an output change for a corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on a modified timing window of previous cells in the timing path, to reduce the computational requirement.

Abstract: A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

Abstract: A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

Abstract: A computer implemented method, system and/or computer program product efficiently manage timing parameters in a circuit. Multiple instances of a definition are implemented onto a circuit. A set of related pins from the multiple instances are defined, and a common assertion value is asserted against all pins in the set of related pins.

Abstract: Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation.

Abstract: Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.

Abstract: A method implemented at a computer aided design tool includes preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances. Preferentially placing the fill regions includes preferentially placing the fill regions adjacent to transistors of a first conductivity type as compared to placing the fill regions adjacent to transistors of a second conductivity type that is opposite the first conductivity type.

Abstract: Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.

Abstract: Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes.

Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow.

Abstract: A system, method and computer program product are provided for optimizing an altered hardware design utilizing power reports. In use, a first hardware design is synthesized. Additionally, a first power report is generated for the synthesized first hardware design. Further, the first hardware design is altered. Further still, the altered hardware design is synthesized. Also, a second power report is generated for the synthesized altered hardware design. Furthermore, the altered hardware design is optimized utilizing the first power report and the second power report.

Abstract: The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed.

Abstract: Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least one path comprising logical user defined delay segments and a timing point may be associated with both a common point and no delay. An original clock signal may propagate along the logical path without incurring delay until arriving back at the common point, along with the original signal. All other clocks may be ignored or prevented from propagating long the path. Multiple replicated copies may be accomplished without requiring additional hardware.

Abstract: Various approaches for improving clock speed for a circuit design. In one embodiment, a graph having nodes and edges that represent the circuit design is generated. The nodes represent flip-flops of the design, the edges represent couplings of data inputs and outputs of the flip-flops, and the edges have associated delay values for respective durations of signal delays of the couplings. A smallest period is determined for which subtracting each delay value from the smallest period and associating the difference with the associated edge does not create a negative cycle in the graph. A path in the graph is selected, the path including selected flip-flops and connecting edges. The circuit design is modified by replacing the selected flip-flops with latches, and the smallest period is output.

Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

Abstract: A computer-implemented method of circuit design can include receiving clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system (305) and receiving a cost function that is dependent upon the clock frequencies of the plurality of clock domains (310). A feasibility result can be determined according to the clock frequency constraints and the cost function (315). The feasibility result can indicate whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint. The feasibility result can be output (315).

Abstract: An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

Abstract: Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

Abstract: Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

Abstract: A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.