Abstract: Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

Abstract: Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

Abstract: A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.

Abstract: A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.

Abstract: The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract: A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

Abstract: A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.

Abstract: The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: A computing device may include a memory to store instructions and a processor. The processor may execute the instructions to conduct an initial cell optimization for an integrated circuit layout; designate clock loads associated with a first-level clock buffer; receive, after the initial standard-cell optimization, a set of initial placement locations; align the clock loads according to the set of placement locations; conduct, using the aligned clock loads, a re-optimization of the integrated circuit layout; and store, in the memory, a circuit layout based on the re-optimization.

Abstract: A delay simulation system comprises an input unit configured to input a netlist, a library, and information including load capacitances; and a simulation unit; the library defines a plurality of distortion patterns of input waveforms of the cells and defines delay values in correspondence with the plurality of distortion patterns of the input waveforms, slopes of the input waveforms, and the load capacitances; and the simulating unit is configured to calculate the delay time in such a manner that the simulating unit selects a distortion pattern of an input waveform according to a logic state of the cell, obtains a slope of the input waveform based on a load capacitance, and obtains a delay value corresponding to the distortion pattern of the input waveform, the slope of the input waveform and the load capacitance, from the library.

Abstract: Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.

Abstract: Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design.

Abstract: A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.

Abstract: A set of respective first delay values for paths from a clock source to nodes of the integrated circuit is generated. Respective second delay values for the paths are generated from the clock source through the clock tree to the nodes. Each first delay value corresponds to one of the second delay values for one of the nodes, and each is greater than the corresponding second delay value. A set of common delay values is generated, with each common delay value being a delay for a shared portion of the paths from the clock source through the clock tree to two of the nodes. The determined clock skew is based on the first delay value for a first node, the second delay value for a second node, and the common delay value for the shared portion of the paths from the clock source to the first and second nodes.

Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.

Abstract: A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.

Abstract: Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.

Abstract: In general, according to one embodiment, a designing apparatus includes a clock tree generator, a logic modifier, a layout modifier, and an outputting module. The clock tree generator is configured to generate a clock tree. The logic modifier is configured to logically insert a delay element in such a manner that a hold violation is modified without considering a setup timing with respect to circuit data corresponding to the clock tree generated by the clock tree generator. The layout modifier is configured to modify a layout of a semiconductor integrated circuit based on a processing result of the logic modifier. The outputting module is configured to output the layout of the semiconductor integrated circuit. The layout is modified by the layout modifier.

Abstract: A semiconductor device which can only load a logical value of an arbitrary memory element is rendered possible to allow a logical value of an arbitrary signal to be loaded at a high speed. A circuit diagram of the semiconductor device is input and a memory element required for calculating a desired signal is detected. The logical value of the memory element is loaded from the semiconductor device, and the logical value of the desired signal is determined in accordance with the logical value of the memory element and the circuit configuration.

Abstract: A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.

Abstract: Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.

Abstract: Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell.

Abstract: Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.

Abstract: Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.

Abstract: A computer-implemented timing verification method for obtaining delay time for a signal propagated through a signal path and performing timing verification. The method stores a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry, extracts a wiring structure of the signal path from a storage unit, extracts a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table, generates an on-chip-variation coefficient from the extracted wiring resistance variation amount and wiring capacitance variation amount, and calculates delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient.

Abstract: A method (100) of estimating a performance characteristic of an integrated circuit (IC) design having an intellectual property (“IP”) core pre-characterizes an element type of the IC design to provide an estimation result of the element type (102-108). Mid-level elements of the IP are acquired (116). A user selects a value of a parameter of the IP core and the IC design is run on a design tool using the estimation result to model the mid-level elements of the IP core (118) to return a performance value of the IC design (120).

Abstract: Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.

Abstract: A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.

Abstract: A computer-implemented method of predicting timing characteristics within a semiconductor device can include determining configuration information for the semiconductor device and determining a measure of timing degradation for data signals of the semiconductor device according to the configuration information. The measure of timing degradation for the data signals can be output.

Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.

Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

Abstract: Methods for analyzing circuit distortion based on contributions from separate circuit elements are presented. Local approximations that do not require high-order derivatives of device models are developed near an operating point for calculating distortion summaries including compression summaries and second-order intermodulation (IM2) distortion summaries.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point.

Abstract: An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a filler cell is placed at a selective location of the device design based on the designation.

Abstract: A computer-readable, non-transitory medium stores therein a verification support program that causes a computer to execute first detecting a state change in a circuit and occurring when input data is given to the circuit; second detecting a state change in the circuit and occurring when the input data partially altered is given to the circuit; determining whether a difference exists between a series of state changes detected at the first detecting and a series of state changes detected at the second detecting; and outputting a determination result obtained at the determining.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, mulitple trace status tables are received, and each of the trace status tables contains a trace error identified by a formal verification engine that was utilized to perform a relative timing (RT) verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.

Abstract: A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the method. In one embodiment, the system includes: (1) a timing violation identifier configured to identify at least some timing violations in a circuit based on a timing analysis, (2) an unsensitizable path identifier configured to identify at least some unsensitizable paths in the circuit and (3) a repair list generator coupled to the timing violation identifier and the unsensitizable path identifier and configured to generate a repair list based on both the at least some timing violations and the at least some unsensitizable paths.