Abstract: Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

Abstract: A method implemented in a computer infrastructure having computer executable code having programming instructions tangibly embodied on a computer readable storage medium. The programming instructions are operable to receive a current waveform of a communication between a plurality of participants. Additionally, the programming instructions are operable to create a voiceprint from the current waveform if the current waveform is of a human voice. Furthermore, the programming instructions are operable to determine one of whether a match exists between the voiceprint and one library waveform of one or more library waveforms, whether a correlation exists between the voiceprint and a number of library waveforms of the one or more library waveforms and whether the voiceprint is unique.

Abstract: A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

Abstract: A packaging design aiding device, including a storage unit to store component information that specifies another electronic component to be connected with an electronic component and a constraint that specifies a range of a wiring distance, a wiring determination unit to specify the electronic component and the another electronic component to be connected based on the component information and to determine a wiring there between, a wiring distance calculation unit to calculate the wiring distance between the electronic component, a display form determination unit to determine a display form based on the calculated wiring distance and the constraint, and a display control unit to display the wiring that connects the electronic component and the another electronic component in the determined display form.

Abstract: Embodiments of the invention provide systems and methods for parallelizing simulation of circuit partitions. A circuit is divided into a number of partitions, for example, according to channel-connected regions. In some embodiments, the partitions are sequenced and assigned to multiple threads for parallel analysis. Iterative timing analysis (ITA), or some other form of analysis, is performed on the partitions over a series of integration time steps. Using the multiple threads, some partitions are solved at later integration time steps while the ITA continues toward relaxation convergence for a current integration time step.

Abstract: Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: A semiconductor device includes: a control target circuit section; and a voltage control section configured to dynamically control a supply voltage to the control target circuit section. The control target circuit section includes: a delay monitor circuit configured to measure a delay in the control target circuit section as a monitor delay; and a target delay register configured to store a target delay data which shows a target delay as a target value of the monitor delay. The delay monitor circuit compares the monitor delay and the target delay shown by the target delay data and sends a comparison resultant signal to the voltage control section to show a result of the comparison. The voltage control section controls the supply voltage based on the comparison resultant signal such that the monitor delay approaches to the target delay.

Abstract: Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Abstract: A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.

Abstract: In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

Abstract: Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof.

Abstract: A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

Abstract: A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: An integrated circuit designing apparatus for designing a semiconductor integrated circuit. The designing includes verifying the timing based on delay information included in the design data, the delay information is extracted from results of placing and wiring of the semiconductor integrated circuit; determining whether each value of hold-time errors generated as a result of the timing verification is smaller than a criteria value; extracting, when the value of a hold-time error is smaller than the criteria value, a wiring line in which the hold-time error is improved by performing a wiring line extension process, the wiring line is included in a path having the hold-time error; calculating, for the extracted wiring line, a wiring line extension distance corresponding to an insertion delay value that improves the hold-time error; and performing the wiring line extension process to extend the extracted wiring line by the calculated wiring line extension distance.

Abstract: A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information.

Abstract: The present invention discloses a method and system for clock tree planning for an ASIC, the method comprising: determining a netlist and a timing constraint file of the ASIC; creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group. The ASIC design method improved by using this method will reduce the design cycle from weeks to days, and enable designer to quickly plan the clock tree, thus reducing the design time and improving the design efficiency.

Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each power domain can be propagated during the full circuit graph-based STA to accurately perform STA without enumerating all paths. Some embodiments can use a tag-based engine to track power-domain crossing(s) during graph-based STA. If a power-domain is crossed in a path, pessimism may be added to the cumulative delay at the end point of the path. For those paths that do not cross a power domain, pessimism may be removed from the cumulative delay at their end points. In some embodiments, pessimism may be removed from the cumulative delay at end points for paths that cross power domains.

Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: A computer-implemented method, system, and computer program product are provided for implementing timing pessimism reduction for parallel clock trees. A common path tracing algorithm in a static timing tool is enhanced to include a proximity credit used for pairs of gates in two clock trees that are placed in close proximity to each other. The proximity credit given is equal to a predefined fraction of a proximity component of a gate delay.

Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.

Abstract: A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group.

Abstract: A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential performance optimization opportunities in the logic used to implement such circuits. Logic in various units of an integrated circuit design that is amenable to being replaced with comparatively faster logic may be identified during timing budget apportionment, such that the magnitude of the slack reported for those units can be adjusted to account for such potential performance improvements. Then, when timing budgets are reapportioned using the slack calculated for each unit, additional slack is available to be reapportioned to those units needing larger timing budgets.

Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying one or more first portions (e.g., islands) of a design of a circuit, where each of the one or more first portions contains a set of elements interconnected via timing critical nets; and reporting inter-dependency between portions of the circuit in view of the one or more first portions. In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying a first portion (e.g., island) of a design of a circuit, the first portion containing a set of elements interconnected via timing critical nets; and performing a synthesis transformation of the first portion to isolate timing dependency of the first portion on a non-critical net connected to an element of the first portion.

Abstract: A simulation method of a logic circuit is provided. The simulation method includes operations dividing the logic circuit into a plurality of divided circuits, determining the divided circuit constructing a path circuit of the logic circuit, determining an auxiliary divided circuit that is the divided circuit not constructing the path circuit and affects on a simulation result of the path circuit. The method also includes executing a simulation calculation of a part of the circuit including the divide circuit constructing the path circuit and the auxiliary divided circuit.

Abstract: A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.

Abstract: A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.

Abstract: A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.

Abstract: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.

Abstract: The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to the test points in the timing constraint file to establish a directed graph; searching for all directed cycles of the directed graph; and for each directed cycle, if the sum of the weights of the directed edges constituting the directed cycle satisfies a required condition, determining that a timing constraint conflict exists among the test points and the timing constraints constituting the directed cycle. The method and apparatus can automatically detect timing constraint conflicts with one hundred percent to reduce design turnaround time and engineer resources in ASIC projects.

Abstract: A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.

Abstract: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.

Abstract: A method of measuring setup time measures a first delay time from an input signal to a clock signal and a second delay time from the clock signal to an output signal, and determines a setup time using the first delay time and the second delay time. The method of measuring setup time is used in designing a semiconductor IC including a pulse-based flip-flop circuit. The semiconductor IC designed by using the method of measuring setup time absorbs a clock jitter and allows a time borrowing between adjacent pipelines.

Abstract: A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.

Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.

Abstract: A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values.

Abstract: Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.

Abstract: A circuit design support apparatus for supporting design of a semiconductor integrated circuit includes an upper limit path delay determining unit that sorts circuit paths included in the semiconductor integrated circuit by probability distributions for the delay values of the circuit paths, selects a worst path having a largest delay value in the circuit paths, and determines a maximum delay value as an upper limit path delay value that does not affect an operational timing of the semiconductor integrated circuit, a cell size optimization processor that replaces cells by modifying their cell sizes on the basis of the upper limit path delay value, and a critical path determining unit that determines critical paths that are capable of affecting the upper limit path delay value if the cell size optimization processor replaces cells included in the circuit paths.

Abstract: A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified.

Abstract: An object of the present invention is to largely reduce a period required for a layout design of a semiconductor integrated circuit device by simplifying a hierarchical layout process. It is necessary to couple a signal line between a circuit belonging to a top and a signal terminal of a block, and there is such an inadequate situation that the signal line cannot be coupled to a predetermined location of the signal terminal of the block or the signal line needs to be largely detoured depending on congestion conditions of the other signal lines in the block and the signal lines of the top coupled to the other blocks. Accordingly, location information of the signal terminal is deleted before the signal line is coupled, so that the signal line can be coupled irrespective of the location information of the signal terminal of the block.

Abstract: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.

Abstract: A method for manufacturing a semiconductor integrated circuit includes: generating first data by performing floor planning based on semiconductor integrated circuit information and monitor path circuit information; generating second data by arranging at least one monitor path flip-flop and at least one monitor path circuit element in the first data based on monitor path position information; generating third data by performing arrangement or wiring based on the second data; generating a first timing analysis result by performing timing analysis on data corresponding to the semiconductor integrated circuit information of the third data; generating a second timing analysis result by performing timing analysis on data corresponding to the monitor path circuit information of the third data; modifying the semiconductor integrated circuit information by comparing the first timing analysis result with the second timing analysis result; and manufacturing the semiconductor integrated circuit based on the modified semi