Defect Analysis Patents (Class 716/112)
  • Patent number: 11403564
    Abstract: A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the hotspot clusters and centroids of the non-hotspot clusters. The system also creates a plurality of kernels configured to identify hotspots, where each kernel is constructed using the extracted critical features of the non-hotspot clusters and the extracted critical features from one of the hotspot clusters, and each kernel is configured to identify hotspot topologies different from hotspot topologies that the other kernels are configured to identify.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 2, 2022
    Assignee: Synopsys, Inc.
    Inventors: Charles C. Chiang, Yen-Ting Yu, Geng-He Lin, Hui-Ru Jiang
  • Patent number: 11397134
    Abstract: A tool for monitoring a part condition includes a computerized device having a processor and a memory. The computerized device includes at least one of a camera and an image input and a network connection configured to connect the computerized device to a data network. The memory stores instructions for causing the processor to perform the steps of providing an initial micrograph of a part to a trained model, providing a data set representative of operating conditions of the part to the trained model, and outputting an expected state of the part from the trained model based at least in part on the input data set and the initial micrograph.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 26, 2022
    Assignee: Raytheon Technologies Corporation
    Inventors: Nagendra Somanath, Anya B. Merli, Ryan B. Noraas, Michael J. Giering, Olusegun T. Oshin
  • Patent number: 11392113
    Abstract: Determining an installation sequence for a system assembly comprising a number of system branches attached to respective terminations is provided. The method comprising receiving schematics for a product into which the system assembly is to be installed, wherein the product comprises a number of openings. A largest termination in the assembly is compared the diameter of an opening through which it is to be routed. If the termination diameter is larger than the opening, an error is generated. If the termination is smaller opening, the diameter of the opening is decremented by a diameter of the system branch attached to termination. The steps are iteratively repeated for the next largest termination in the assembly until an error signal is generated for a termination or all terminations in the system assembly intended to pass through the opening are added as steps in the installation sequence.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: July 19, 2022
    Assignee: The Boeing Company
    Inventor: Guillaume Jean-Baptiste Laurent
  • Patent number: 11385986
    Abstract: A report of results of validating a circuit can simplify a large number of error events, that can be generated when designing electrical circuits using computer aided design tools, by first filtering the large number of error events according to a user defined filter criteria. The filter results are processed by one or more report rules. Each of the report rules may generate one or more report results based on, at least, the filtered error events.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 12, 2022
    Assignee: Siemens Industry Software Inc.
    Inventor: Michael Alam
  • Patent number: 11379753
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 5, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tulio Paschoalin Leao, Gabriel Guedes de Azevedo Barbosa, Artur Melo Mota Costa, Alberto Manuel Arias Drake, Guilherme Seminotti Braga, Rodrigo Fonseca Rocha Soares, Rogério de Souza Moraes, Paula Selegato Mathias, Tales Bontempo Cunha
  • Patent number: 11378742
    Abstract: In one aspect, a method for displaying incompatible ports at the schematic design stage comprises the following. A schematic of a photonic integrated circuit is accessed. The schematic comprises a plurality of optical components that have ports, and the optical components are connected at their ports. A processor determines the structures of the ports. Typically, the structure of a port is determined by the cross-sectional shape and the material(s) of the port. The schematic of the photonic integrated circuit is displayed, with different visual indicators for ports with different structures. For example, ports with different structures may be represented by symbols of different colors, different outlines, different fill patterns or other types of non-textual visual indicators.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: July 5, 2022
    Assignee: Synopsys, Inc.
    Inventor: Thomas Hakkers
  • Patent number: 11366951
    Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11354477
    Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: June 7, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jasleen Kaur Ahuja, Taranjit Singh Kukal, Vikrant Khanna, Nikhil Gupta, Rohit Shukla, Kunal Gupta, Charu Kapoor
  • Patent number: 11354483
    Abstract: Improved parasitic analysis of a design of an electrical circuit (e.g. a PCB coupled to an IC package) can use a first parasitic analysis to identify a first set of pins having excessive parasitic values (“hotspots” in the design) and then identify a second set of pins that do not have excessive parasitic values. The pins in the second set can be clustered (e.g. using a grid of cells) to reduce a model size for calculations in a second parasitic analysis, and the pins in the first set can be analyzed in the second parasitic analysis either individually or in clusters of similar pins with excessive parasitic values.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: June 7, 2022
    Assignee: ANSYS, INC.
    Inventor: Prakash Vennam
  • Patent number: 11341310
    Abstract: A method is disclosed including analyzing a layout netlist including a first set of nodes against a schematic netlist including a second set of nodes. Each node of the first and second sets of nodes is assigned a matching type for identifying matching nodes between the first and second sets of nodes. The method includes determining one or more unmatched nodes between the first set of nodes and the second set of nodes based on the matching type. The method includes generating a convergence graph comprising nodes of the first set of nodes that have a corresponding matching node in the second set of nodes based on the matching type, and the one or more unmatched nodes.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 24, 2022
    Assignee: Synopsys, Inc.
    Inventors: Chiu-Yu Ku, Wei-Shun Chuang, Chia-Wei Hsu
  • Patent number: 11330751
    Abstract: There is provided a board work machine (a component mounting machine) including a data registration section for registering in advance multiple data (ultra-high precision data, high precision data, normal precision data) for each characteristic of a member constituting a base material for a circuit board in accordance with the type and characteristic of the member; a work performing section (a part camera) for performing work using the member or performing work on the member while selecting one item of data from the multiple data for reference; and an automatic data switching section for automatically switching among the multiple member data that the work performing section refers to in accordance with the performing situation of the work performed by the work performing section.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 10, 2022
    Assignee: FUJI CORPORATION
    Inventors: Mitsuru Sanji, Shigenori Sengoku
  • Patent number: 11314229
    Abstract: A spatial model of a printed circuit board assembly is generated based on an input file. The spatial model is used to determine a spatial feature not directly specified in the input file. A manufacturing parameter is determined based at least in part on the determined spatial feature. A proposal to manufacture the printed circuit board assembly is generated programmatically based at least in part on the determined manufacturing parameter.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 26, 2022
    Assignee: Tempo Automation, Inc.
    Inventors: Jeffrey McAlvay, Shannon Lincoln, Jesse Koenig, Thomas Anderson, Jonas Neubert, Shashank Samala, Ryan Saul
  • Patent number: 11257207
    Abstract: Disclosed are methods and apparatus for inspecting a photolithographic reticle. A near field reticle image is generated via a deep learning process based on a reticle database image produced from a design database, and a far field reticle image is simulated at an image plane of an inspection system via a physics-based process based on the near field reticle image. The deep learning process includes training a deep learning model based on minimizing differences between the far field reticle images and a plurality of corresponding training reticle images acquired by imaging a training reticle fabricated from the design database, and such training reticle images are selected for pattern variety and are defect-free.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 22, 2022
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Hawren Fang, Abdurrahman Sezginer, Rui-fang Shi
  • Patent number: 11244099
    Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: February 8, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bentian Jiang, Natarajan Viswanathan, Zhuo Li, Yi-Xiao Ding
  • Patent number: 11200364
    Abstract: A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia Cheng Chen, Ching-Fang Chen, Huang-Yu Chen, Jen Ping Hsu
  • Patent number: 11194949
    Abstract: A routability optimization engine comprising a hotspot prediction engine to predict locations of a plurality of hotspots in a circuit layout based on a machine learning system, a white space calculator to calculate white space around each of the plurality of hotspots, and a cell spreader engine to redistribute white space around each of the plurality of hotspots to improve routability of the circuit layout.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 7, 2021
    Assignee: Synopsys, Inc.
    Inventors: Prashant Saxena, Wei-Ting Chan, Pei-Hsin Ho
  • Patent number: 11188068
    Abstract: A monitoring system and method for monitoring an operational operation to predict a fault in the operational operation. The operational operation monitors a number of manufacturing stages within a manufacturing system. The monitoring is accomplished using a number of sensors directed to measuring aspects of the manufacturing system, and detecting trends indicating a potential fault of the system according to a prediction model. The prediction model may be updated during online operation of the monitoring system.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 30, 2021
    Assignees: Robert Bosch LLC, Robert Bosch GmbH
    Inventors: Fabian Borowski, James Kressler, Uwe Roehm, Stefan Reichardt, Luis Alonso Loya Acosta, Edgar Baur
  • Patent number: 11176306
    Abstract: A method, a system, and non-transitory computer readable medium for level package routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. The objects of the set of nets are represented by a respective center point during triangulation. The method also includes generating a route between the objects of the set of nets based on at least a total cost. The total cost is determined based on at least the routing resource graph. The method also includes altering the route based on a determination that a constraint rule is unmet and outputting routing information comprising the route for the set of nets.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 16, 2021
    Assignee: Synopsys, Inc.
    Inventors: About Liao, Bing Chen, Happy Wang, Pagan Chou, Cheng-chieh Chen, Philippe Aubert McComber, Siarhei Lekhtsikau
  • Patent number: 11170151
    Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified to bring non-compliant periphery chip regions into compliance, in response to the determination that the portion of the first chip layout inside the tile area fails to comply with the one or more design rules. A multi-chip wafer is fabricated that includes the chip layouts.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Larry Wissel
  • Patent number: 11170149
    Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang
  • Patent number: 11132282
    Abstract: A cloud-based accelerator manager manages cloud-based hardware accelerators. The accelerator manager monitors computer programs running in the cloud and generates a trace that indicates which accelerators were used and when. The trace may be for a single computer program or may be for multiple computer programs. Thus, the trace can be program-specific, showing all accesses to accelerators by a single program, or may be accelerator-specific, showing all accesses to each accelerator by all computer programs. The cloud-based accelerator manager detects a failure in one of the computer programs executing in the cloud. The cloud-based accelerator manager provides the trace to a user, who can then analyze the trace to determine whether the failure was due to an accelerator. The cloud-based accelerator manager thus helps detect when cloud-based accelerators are the reason for failures for computer programs running in a cloud.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Schardt, Jim C. Chen, Lance G. Thompson, James E. Carey
  • Patent number: 11120186
    Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Chou Liu, Yi-Kuang Lee, Lie-Szu Juang
  • Patent number: 11099137
    Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an augmented-reality or virtual-reality (AR/VR) image of the model that shows a 3D shape of the model and provides the AR/VR image to an AR/VR viewing device for display.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 24, 2021
    Assignee: KLA Corporation
    Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
  • Patent number: 11058040
    Abstract: An operation checking device of an electronic component mounting machine is provided with a first memory section configured to memorize an operation program of the electronic component mounting machine including at least a collection operation of an electronic component by a collecting device; a second memory section configured to memorize shape data of the electronic component and shape data of the collecting device; a first acquiring section configured to acquire information of the electronic components and information of the collecting device based on the operation program required for a current operation memorized on the first memory section; and a second acquiring section configured to acquire corresponding shape data of the electronic component and shape data of the collecting device from the second memory section based on the information of the electronic component and the information of the collecting device acquired by the first acquiring section.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: July 6, 2021
    Assignee: FUJI CORPORATION
    Inventor: Minoru Yoriki
  • Patent number: 11042683
    Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 22, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Elene Chobanyan, Karl J. Bois
  • Patent number: 11038349
    Abstract: A method for generating electric substation load transfer control parameters includes adjusting elements in a fundamental scale matrix according to a condition change of a power grid, wherein the fundamental scale matrix is constructed based on the topology structure of the power grid, and the elements in the fundamental scale matrix represent switch information and risk values of paths between nodes of the power grid, wherein the switch information represents number of switching times required for connecting two nodes of the power grid; and performing operations on the adjusted fundamental scale matrix to generate switch information and risk values of paths for electric substation load transfer control, as electric substation load transfer control parameters.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 15, 2021
    Assignee: Utopus Insights, Inc.
    Inventors: Zhen Huang, Feng Jin, Qi Ming Tian, Wen Jun Yin, Ya Nan Zhang, Ming Zhao
  • Patent number: 11031385
    Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woo Seo, Jin Tae Kim, Tae Joong Song, Hyoung-Suk Oh, Keun Ho Lee, Dal Hee Lee, Sung We Cho
  • Patent number: 11010659
    Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 18, 2021
    Assignee: INTEL CORPORATION
    Inventors: Kamal Sinha, Balaji Vembu, Eriko Nurvitadhi, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Farshad Akhbari, Narayan Srinivasa, Feng Chen, Dukhwan Kim, Nadathur Rajagopalan Satish, John C. Weast, Mike B. MacPherson, Linda L. Hurd, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Patent number: 11003829
    Abstract: A cell library stores a plurality of standard layout cells. A functional integrated circuit design is received, and a plurality of the standard layout cells are selected from the cell library based on the received functional integrated circuit design. A first standard layout cell from the cell library that is selected based on the received functional integrated circuit design includes a buffer circuit having an input terminal, an output terminal, a first voltage terminal and a second voltage terminal, and an antenna protection circuit connected between the input terminal and the second voltage terminal.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kenan Yu, James Deng
  • Patent number: 10990747
    Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Patent number: 10990746
    Abstract: A method of designing an integrated circuit (IC) device includes specifying a set of criteria corresponding to an IC manufacturing process, using a processor to generate a design rule by applying a design rule instruction to the set of criteria, generating a design rule manual (DRM), the DRM being an electronic file comprising the design rule, using the design rule from the DRM to perform a design rule check (DRC) on a layout of at least a portion of the IC device, and, based on verifying the layout by performing the DRC, storing an IC layout diagram comprising the layout on a non-transitory computer-readable medium.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 27, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC CHINA COMPANY, LIMITED
    Inventor: Ya-Min Zhang
  • Patent number: 10970445
    Abstract: Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit. During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. Circuit design tools may be used to extract parasitics from the ASIC design, compute low-level interconnect delays, convert the interconnect delays to higher-level port-to-port delays, convert the port-to-port delays to timing constraints, and generate corresponding configuration data for programming the programmable integrated circuit to emulate the ASIC design. The programmable integrated circuit may then be tested for functional and performance integrity.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: Mohamed Farag
  • Patent number: 10970456
    Abstract: A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 6, 2021
    Assignee: Synopsys, Inc.
    Inventors: Wei-shun Chuang, Chiu-yu Ku
  • Patent number: 10963609
    Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shen Lin, Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee
  • Patent number: 10949600
    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
  • Patent number: 10943047
    Abstract: A circuit design method is provided, including the steps of: designing a plurality of paths, wherein each path includes a plurality of elements; determining a specific path of the plurality of paths by performing a timing analysis; replacing the specific element in the specific path with the configurable logic gate array cell; and selectively changing a connection mode of a metal layer to make the configurable logic gate array cell have another function. The timing analysis includes: for each path of the plurality of paths, determining whether a chip area meets a constraint condition and whether a timing violation will occur when a specific element in each path is replaced with a configurable logic gate array cell; and when both conditions are met, determining that path as the specific path.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 9, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Shih-Hsiang Tai
  • Patent number: 10909296
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 2, 2021
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Patent number: 10897813
    Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 19, 2021
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Chun-Lin Liao
  • Patent number: 10867107
    Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Min Huang, Ching-Hung Lai, Jia-Guei Jou, Yin-Chuan Chen, Chi-Ming Tsai
  • Patent number: 10860762
    Abstract: Methods and apparatus relating to subsystem-based System on Chip (SoC) integration are described. In one embodiment, logic circuitry determines one or more components of a subsystem. The subsystem supports an architectural feature to be implemented on a System on Chip (SoC) device. A first interface communicatively couples a first component of the subsystem to a first component of another subsystem. A second interface communicatively couples at least one component of the subsystem to at least one chassis component of the SoC device or communicatively couples the at least one component of the subsystem to at least one non-chassis component of the other subsystem. In an embodiment, components of the subsystem may be packaged such that the packaging generates a reusable collateral that allows for fast integration of all aspects of design in any SoC device with a compatible chassis prior to manufacture.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corpration
    Inventors: Robert P. Adler, Husnara Khan, Satish Venkatesan, Ramamurthy Sunder, Mukesh K. Mishra, Bindu Lalitha, Hassan M. Shehab, Sandhya Seshadri, Dhrubajyoti Kalita, Wendy Liu, Hanumanth Bollineni, Snehal Kharkar
  • Patent number: 10840052
    Abstract: A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Patent number: 10831976
    Abstract: A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Dongbing Shao, Yufei Wu, Zheng Xu
  • Patent number: 10783057
    Abstract: Technology is described for Testing as a Service (TaaS) for a video game. In one embodiment, a method includes an operation for receiving a game application for testing for one or more bugs. The method further provides for executing, by an automated game testing module, a plurality of automated sessions of the game session while implementing testing inputs for the plurality of automated sessions, the testing inputs include control inputs, game states, system parameters and network parameters. The method further includes operations for detecting an occurrence of a bug during the said executing the plurality of sessions for generating a snapshot file including a portion of the control inputs, the game state data, and a video component associated with the occurrence of the bug.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Justin Beltran, Kyle Cannon, Nathan Gross, Dylan Butler
  • Patent number: 10783309
    Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, ??={(L×?×?t×E)/(D×T)}×m×?×?×?; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Akiko Matsui, Naoki Nakamura
  • Patent number: 10776543
    Abstract: Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josiah Hamilton, David J. Geiger, Mihir Choudhury, Alexander J. Suess
  • Patent number: 10769347
    Abstract: A Physical Fault Analysis (PFA) outcome prediction tool utilizes previously-generated evaluation data and associated PFA outcome data to generate a Bayesian Generalized Linear Model (BGLM), and then utilizes the BGLM to generate a PFA outcome prediction for newly-submitted evaluation data that operably characterizes measured operating characteristics of an IC chip that is being developed. The BGLM generation methodology by utilizing a Generalized Linear Model (GLM) in a Bayesian framework to form a hierarchical model representing the evaluation data and associated PFA outcome data as a linear combination. The PFA outcome prediction includes a credible interval of a posterior distribution that effectively represents a cross-sectional portion of the BGLM corresponding to the newly-submitted evaluation data.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Synopsys, Inc.
    Inventor: Christopher W. Schuermyer
  • Patent number: 10740410
    Abstract: Disclosed are methods and apparatus for commenting on interactive content. One of the methods includes reproducing the interactive content in accordance with a branched scenario including a plurality of branches, each of which is matched to a trigger, receiving a touch input for inputting a comment on the interactive content, selecting a comment target trigger from the triggers, matching the comment to the selected comment target trigger, determining a comment target object, which is an object located closest to a touch point at the time when the touch input is made among candidate objects related to the comment target trigger, the candidate objects comprise objects of a response being reproduced at the time when the touch input is made, among all responses of the comment target trigger; and transmitting comment information comprising information of the comment target trigger, a trigger log and content data of the comment.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 11, 2020
    Assignee: STUDIO XID KOREA, INC.
    Inventors: Soo Kim, Jae Won Song
  • Patent number: 10726797
    Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 28, 2020
    Assignee: NVIDIA Corporation
    Inventor: Tom J. Verbeure
  • Patent number: 10691867
    Abstract: A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 23, 2020
    Assignee: Synopsys, Inc.
    Inventors: Wei-shun Chuang, Chiu-yu Ku
  • Patent number: 10691858
    Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 23, 2020
    Assignee: Pulsic Limited
    Inventor: Graham Balsdon