Defect Analysis Patents (Class 716/112)
  • Patent number: 10909296
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 2, 2021
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Patent number: 10897813
    Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 19, 2021
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Chun-Lin Liao
  • Patent number: 10867107
    Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Min Huang, Ching-Hung Lai, Jia-Guei Jou, Yin-Chuan Chen, Chi-Ming Tsai
  • Patent number: 10860762
    Abstract: Methods and apparatus relating to subsystem-based System on Chip (SoC) integration are described. In one embodiment, logic circuitry determines one or more components of a subsystem. The subsystem supports an architectural feature to be implemented on a System on Chip (SoC) device. A first interface communicatively couples a first component of the subsystem to a first component of another subsystem. A second interface communicatively couples at least one component of the subsystem to at least one chassis component of the SoC device or communicatively couples the at least one component of the subsystem to at least one non-chassis component of the other subsystem. In an embodiment, components of the subsystem may be packaged such that the packaging generates a reusable collateral that allows for fast integration of all aspects of design in any SoC device with a compatible chassis prior to manufacture.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corpration
    Inventors: Robert P. Adler, Husnara Khan, Satish Venkatesan, Ramamurthy Sunder, Mukesh K. Mishra, Bindu Lalitha, Hassan M. Shehab, Sandhya Seshadri, Dhrubajyoti Kalita, Wendy Liu, Hanumanth Bollineni, Snehal Kharkar
  • Patent number: 10840052
    Abstract: A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Patent number: 10831976
    Abstract: A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Dongbing Shao, Yufei Wu, Zheng Xu
  • Patent number: 10783057
    Abstract: Technology is described for Testing as a Service (TaaS) for a video game. In one embodiment, a method includes an operation for receiving a game application for testing for one or more bugs. The method further provides for executing, by an automated game testing module, a plurality of automated sessions of the game session while implementing testing inputs for the plurality of automated sessions, the testing inputs include control inputs, game states, system parameters and network parameters. The method further includes operations for detecting an occurrence of a bug during the said executing the plurality of sessions for generating a snapshot file including a portion of the control inputs, the game state data, and a video component associated with the occurrence of the bug.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Justin Beltran, Kyle Cannon, Nathan Gross, Dylan Butler
  • Patent number: 10783309
    Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, ??={(L×?×?t×E)/(D×T)}×m×?×?×?; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Akiko Matsui, Naoki Nakamura
  • Patent number: 10776543
    Abstract: Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josiah Hamilton, David J. Geiger, Mihir Choudhury, Alexander J. Suess
  • Patent number: 10769347
    Abstract: A Physical Fault Analysis (PFA) outcome prediction tool utilizes previously-generated evaluation data and associated PFA outcome data to generate a Bayesian Generalized Linear Model (BGLM), and then utilizes the BGLM to generate a PFA outcome prediction for newly-submitted evaluation data that operably characterizes measured operating characteristics of an IC chip that is being developed. The BGLM generation methodology by utilizing a Generalized Linear Model (GLM) in a Bayesian framework to form a hierarchical model representing the evaluation data and associated PFA outcome data as a linear combination. The PFA outcome prediction includes a credible interval of a posterior distribution that effectively represents a cross-sectional portion of the BGLM corresponding to the newly-submitted evaluation data.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Synopsys, Inc.
    Inventor: Christopher W. Schuermyer
  • Patent number: 10740410
    Abstract: Disclosed are methods and apparatus for commenting on interactive content. One of the methods includes reproducing the interactive content in accordance with a branched scenario including a plurality of branches, each of which is matched to a trigger, receiving a touch input for inputting a comment on the interactive content, selecting a comment target trigger from the triggers, matching the comment to the selected comment target trigger, determining a comment target object, which is an object located closest to a touch point at the time when the touch input is made among candidate objects related to the comment target trigger, the candidate objects comprise objects of a response being reproduced at the time when the touch input is made, among all responses of the comment target trigger; and transmitting comment information comprising information of the comment target trigger, a trigger log and content data of the comment.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 11, 2020
    Assignee: STUDIO XID KOREA, INC.
    Inventors: Soo Kim, Jae Won Song
  • Patent number: 10726797
    Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 28, 2020
    Assignee: NVIDIA Corporation
    Inventor: Tom J. Verbeure
  • Patent number: 10691867
    Abstract: A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 23, 2020
    Assignee: Synopsys, Inc.
    Inventors: Wei-shun Chuang, Chiu-yu Ku
  • Patent number: 10691858
    Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 23, 2020
    Assignee: Pulsic Limited
    Inventor: Graham Balsdon
  • Patent number: 10651201
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Patent number: 10628551
    Abstract: Methods according to the disclosure identify at least one corner violation including a pair of fill cells of the fill region having a corner-to-corner shape profile that violates a manufacturing specification for the fill region of the IC layout; creating an exclusion layer for the at least one corner violation of the IC layout; removing the at least one corner violation from the fill region using the exclusion layer to form a modified IC layout, wherein at least a portion of each of the pair of fill cells remains in the modified IC layout after removing the at least one corner violation; and manufacturing the modified IC layout to include a fill shape based on the fill region after removing the at least one corner violation, the fill shape being compliant with the manufacturing specification for the fill region of the IC layout.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Gazi M. Huda
  • Patent number: 10616103
    Abstract: A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to t
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Harald Folberth, Sven Nitzsche, Sven Peyer
  • Patent number: 10605745
    Abstract: A candidate defect may be identified at a semiconductor wafer. A determination may be made as to whether the candidate defect at the semiconductor wafer corresponds to a systematic defect or a random defect. In response to determining that the candidate defect at the semiconductor wafer corresponds to a systematic detect, the candidate defect at the semiconductor wafer may be provided to a defect review tool for review by the defect review tool.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 31, 2020
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Yotam Sofer, Boaz Cohen, Saar Shabtay, Eli Buchman
  • Patent number: 10606974
    Abstract: In an electronic circuit design system, dynamic visual guidance for relative placement of mutually paired electronic components, such as a bypass capacitance portion and a power pin in a power domain, is provided. A first, selected component is adaptively paired with one of a plurality of second components eligible for pairing with the first component, according to predetermined pairing criteria such as proximity criteria. A mutual placement zone between the paired components is generated to define a locus of valid placement locations of the paired first and second components one with respect to the other according to predetermined placement criteria therefor. Visual indicia to represent the mutual placement zone is generated, thereby providing visual guidance to reposition the first component.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 31, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Amiya Acharya, Vikas Kohli
  • Patent number: 10606978
    Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexey Y. Lvov, Gi-Joon Nam, Gustavo Enrique Tellez
  • Patent number: 10596219
    Abstract: A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 24, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Fedor G. Pikus, Patrick D. Gibson, Padmaja Susarla
  • Patent number: 10599807
    Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Patent number: 10592635
    Abstract: A computer-implemented method, computer program product, and computer processing system are provided for generating synthetic layout patterns. The method includes receiving, by a processor, a set of physical design layouts that include a variety of layout patterns for neural network training. The method further includes generating, by the processor, a set of training layout pattern images for the neural network training by performing automatic image capturing on the set of physical design layouts with scripts. The method also includes training, by the processor, a feedforward neural network (FFNN)-based Variational Autoencoder (VAE) with the set of training layout pattern images. The method additionally includes generating, by the processor using the FFNN-based VAE, new synthetic layout images.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Patent number: 10594137
    Abstract: A method for generating electric substation load transfer control parameters includes adjusting elements in a fundamental scale matrix according to a condition change of a power grid, wherein the fundamental scale matrix is constructed based on the topology structure of the power grid, and the elements in the fundamental scale matrix represent switch information and risk values of paths between nodes of the power grid, wherein the switch information represents number of switching times required for connecting two nodes of the power grid; and performing operations on the adjusted fundamental scale matrix to generate switch information and risk values of paths for electric substation load transfer control, as electric substation load transfer control parameters.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 17, 2020
    Assignee: Utopus Insights, Inc.
    Inventors: Zhen Huang, Feng Jin, Qi Ming Tian, Wen Jun Yin, Ya Nan Zhang, Ming Zhao
  • Patent number: 10585998
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10572620
    Abstract: A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 25, 2020
    Assignee: Oracle International Corporation
    Inventors: David L. Toub, Larry B. Edwards, Terry L. Maness, Johan Bastiaens
  • Patent number: 10565342
    Abstract: A system and method for an interactive circuit layout design that provides spatially adaptive overlay indicative of parametric properties. A physical layout of an electrical circuit product is rendered on a display. At least one net of the physical layout is delineated into a plurality of net segments each having at least one physical property parametrically specified in a value therefor. For each net segment, a corresponding segment indicator is selectively rendered on the display, adaptively positioned and spatially mapped to the net segment corresponding thereto as a symbolic surrogate for the corresponding net segment within the physical layout. Selection of a net segment actuates determination of a behavior of the electrical circuit product during an operation consistent with an electrical response of the corresponding net segment. Editing of a net of the physical layout delineates a plurality of updated net segments for the edited net exclusive of other nets.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 18, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Arnold Ginetti, Sunil Prasad Todi, Hitesh Marwah
  • Patent number: 10553574
    Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woo Seo, Jin Tae Kim, Tae Joong Song, Hyoung-Suk Oh, Keun Ho Lee, Dal Hee Lee, Sung We Cho
  • Patent number: 10552882
    Abstract: Methods and software that allow one or more users to utilize custom pricing in the context of an electronic marketplace. Such custom pricing can be implemented by transmitting specifications of custom pricing engines and/or custom design document interrogator engines to the marketplace along with or independently from one or more design documents containing structures to be priced. Various corresponding and related methods and software are described.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: February 4, 2020
    Assignee: Desprez, LLC
    Inventors: James L. Jacobs, II, John E. Cronin, Christopher M. Huffines, Steven M. Lynch
  • Patent number: 10540470
    Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 21, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Paul W. Kollaritsch
  • Patent number: 10521539
    Abstract: A method, a non-transitory computer-readable medium, and an apparatus for optimizing a design layout of an integrated circuit (IC) includes: selecting layout regions from a full-chip design layout for the IC; determining pixel images for the layout regions by performing pixel-based mask optimization for the layout regions, in which each pixel image corresponds to a respective layout region; determining a backpropagation (BP) artificial neural network (ANN) model using the pixel images and the layout regions; and determining a full-chip pixel image for the full-chip design layout using the BP ANN model, in which the BP ANN model uses the full-chip design layout as input.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 31, 2019
    Assignees: Shenzhen Jingyuan Information Technology Limited, Dongfang Jinigryuan Electron Limited
    Inventors: Zongchang Yu, Shengrui Zhang, Weijie Shi
  • Patent number: 10521545
    Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang
  • Patent number: 10503865
    Abstract: A photonic design automation (PDA) tool to facilitate design of semiconductor photonic devices is described. In one example, the PDA tool includes a process design library including one or more photonics parameterized cells (pCells), a plurality of processor-executable photonics design functions including a design rule check (DRC) violation removal function, and a semiconductor technology-dependent parameter file including a plurality of design rules that define allowed semiconductor design patterns to be converted to a plurality of semiconductor fabrication mask designs in a first semiconductor technology. The PDA tool supports a graphical user interface (GUI) to provide access to the library of photonic pCells to create intuitive physical property layers for a photonic device, and processes the physical property layers using the DRC violation removal function and the design rules to automatically generate a plurality of mask design layers for a “DRC clean” physical layout of the photonics device.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 10, 2019
    Assignee: Massachusetts Institute of Technology
    Inventor: Luca Alloatti
  • Patent number: 10504038
    Abstract: In one embodiment, a learning machine device initializes thresholds of a data representation of one or more data features, the thresholds specifying a first number of pre-defined bins (e.g., uniform and equidistant bins). Next, adjacent bins of the pre-defined bins having substantially similar weights may be reciprocally merged, the merging resulting in a second number of refined bins that is less than the first number. Notably, while merging, the device also learns weights of a linear decision rule associated with the one or more data features. Accordingly, a data-driven representation for a data-driven classifier may be established based on the refined bins and learned weights.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 10, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Vojtech Franc, Karel Bartos, Michal Sofka
  • Patent number: 10489609
    Abstract: Disclosed approaches for limiting use or a programmable IC involve a provider of programmable ICs generating, using one or more private keys of the provider, one or more signed configuration bitstreams from one or more circuit designs received from a customer. The provider changes the general purpose programmable IC into an application programmable IC that can only be programmed by the one or more signed configuration bitstreams. The application programmable IC and the one or more signed configuration bitstreams are provided from the provider to the customer.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: November 26, 2019
    Assignee: XILINX, INC.
    Inventors: John E. McGrath, Brendan Farley, Anthony J. Collins, Matthew H. Klein
  • Patent number: 10489549
    Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree, and specific portions of the design are routed individually from other portions of the design.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Mario Wilkosz, Hoi-Kuen Lam, Chung-Do Yang
  • Patent number: 10481585
    Abstract: A spatial model of a printed circuit board assembly is generated based on an input file. The spatial model is used to determine a spatial feature not directly specified in the input file. A manufacturing parameter is determined based at least in part on the determined spatial feature. A proposal to manufacture the printed circuit board assembly is generated programmatically based at least in part on the determined manufacturing parameter.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 19, 2019
    Assignee: Tempo Automation, Inc.
    Inventors: Jeffrey McAlvay, Shannon Lincoln, Jesse Koenig, Thomas Anderson, Jonas Neubert, Shashank Samala, Ryan Saul
  • Patent number: 10467371
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chayan Majumder, Arnold Jean Marie Gustave Ginetti
  • Patent number: 10445460
    Abstract: A via model generation method includes: acquiring via arrangement information including a hole diameter of a via formed in a board including a plurality of wiring layers, a clearance distance between a ground conductor formed in one wiring layer of the plurality of wiring layers and the via, and a ground via distance between the via and a ground via coupled to the ground conductor; acquiring board information including a relative dielectric constant of the board; calculating a capacitance component of the via by a first electromagnetic field analysis using the hole diameter of the via, the clearance distance, and the relative dielectric constant of the board; calculating an inductance component of the via by a second electromagnetic field analysis using the hole diameter of the via, the ground via distance, and the relative dielectric constant of the board; and generating a via model including the capacitance and inductance components.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 15, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kumiko Teramae, Hikoyuki Kawata, Takashi Fukuda, Megumi Tanaka
  • Patent number: 10445458
    Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 15, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Elene Chobanyan, Karl J Bois, Charles Andrew Hartman
  • Patent number: 10423751
    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
  • Patent number: 10410356
    Abstract: A method for processing the Library Exchange Format (LEF) diagram of a layout includes the following steps: Step 1, breaking the LEF diagram into multiple rectangular segments; Step 2, numbering all rectangular segments; and Step 3, combining rectangular segments to obtain a larger rectangular segment and replacing corresponding uncombined rectangular segments with the larger combined rectangular segment. The method reduces the data size of the LEF file and increase the data transmission efficiency of the LEF file.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 10, 2019
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Xingzhou Zhang
  • Patent number: 10402531
    Abstract: A method of manufacturing a printed circuit board (PCB) includes determining a weft direction of the PCB, and defining a routing design of differential pairs. The routing design is designed to have a fixed region in the weft direction. The method further includes manufacturing the PCB according to the routing design.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 3, 2019
    Assignee: Ciena Corporation
    Inventors: Robert Bisson, Marko Antonic
  • Patent number: 10379446
    Abstract: This disclosure includes a variety of methods of describing a shape in a hierarchical manner, and uses of such a hierarchical description. In particular, this disclosure includes a method comprising: fitting one or more sub-shapes of a first order against a shape; determining an error of the fitting; and fitting one or more sub-shapes of a second order against the error.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 13, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Alok Verma, Sinatra Canggih Kho, Adriaan Johan Van Leest
  • Patent number: 10380304
    Abstract: An information processing apparatus for design assistance including: a memory storing first correspondence relationship information in which feature information of a circuit and a value to be set to a parameter for use to cause an integrated circuit capable of configuring the circuit therein to configure the circuit are associated with each other, and second correspondence relationship information in which each of multiple values settable to the parameter and an improvement level of a performance of the circuit configured by the integrated circuit with the value set to the parameter are associated with each other; and a processor receives feature information related of a target circuit to be designed; if a value of a parameter set to the integrated circuit to configure the target circuit satisfies a predetermined constraint, the received feature information and the value are stored and accumulated in the first correspondence relationship information.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 13, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Michitaka Hashimoto, Ryo Mizutani
  • Patent number: 10372857
    Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 6, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Benjamin Toby, Karl J. Bois
  • Patent number: 10354037
    Abstract: Disclosed are methods, systems, and articles of manufacture for manipulating a hierarchical structure of the electronic design. These techniques identify a set of layout components instantiated from a layout of an electronic design. This set of layout components may constitute, for example, a FigGroup. One or more schematic instances and corresponding schematic connectivity information may be identified from a schematic design of the electronic design, and the one or more schematic instances correspond to the set of layout components. A layout cell or a figure group may be generated for the set of layout components based in part or in whole upon the schematic connectivity information. The original layout may then be transformed into a transformed layout at least by replacing the set of layout components with the generated layout cell or figure group.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 10346581
    Abstract: A method for validating the design of an electronic circuit uses a static checker tool to verify the circuit design against rules and attributes of the components of the circuit. A power intent of the circuit, pins for power, ground and data signal inputs and outputs for each component, and a model for attributes and parameters of the pins are defined. The attributes of the components are defined in terms of input and output voltages; input and output currents; input and output voltage, current and data signal timing; and input and output voltage and current ranges and tolerances. A netlist of interconnections representing the designed circuit is validated against the power intent and the model for the attributes. A report is output describing the validity of the circuit based on the compatibility of the netlist, the power intent, and the model for the attributes of the components.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Benjamin Kerr
  • Patent number: 10346576
    Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Patent number: 10331832
    Abstract: A method for floating node reduction uses a capacitance matrix that specifies coupling capacitances between signal nodes and floating nodes of an interconnect structure. Random walks are performed from a first signal node to the other signal nodes, wherein each of the random walks traverses one or more of the floating nodes. Each of the random walks is directed based on probabilities derived from the coupling capacitances of the capacitance matrix. A count is maintained for each of the other signal nodes, wherein each count specifies a number of the random walks that end on the corresponding signal node. The indirect coupling capacitance from the first signal node to a second signal node is selected to correspond with the total indirect coupling capacitance of the first signal node, times the count associated with the second signal node, divided by the total number of random walks.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 25, 2019
    Assignee: Synopsys, Inc.
    Inventors: Alexei Svizhenko, Arindam Chatterjee, Arthur B. Nieuwoudt