Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A computing system configured to verify design of an integrated circuit (IC) includes a memory and a processor. The memory is configured to store computer executable instructions. The processor is configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language (HDL) code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the HDL code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Ground rule verification (“GRV”) design layouts may be automatically generated based on one or more design macros. The GRV design layout may be tested based on the one or more design macros by violating one or more ground rules using one or more GRV ranges. The testing may include electrical testing of the one or more GRV design layouts based on the one or more design macros. The one or more ground rules may be automatically selected and approved the based upon a degree of violation acceptability.

Abstract: An optimization device includes an output data acquisitor that acquires output data having a second number of dimensions obtained by performing an experiment or a simulation, an evaluation value calculator that calculates and outputs an evaluation value of the output data, a features extractor that extracts an output data features having a third number of dimensions different from the second number of dimensions, an input parameter converter that generates a conversion parameter related to the output data features predicted from the input parameters, a next input parameter determinator that determines a next input parameter to be acquired by the output data acquisitor, based on the conversion parameter and the corresponding evaluation value, and an iterative determinator that repeats processes of the output data acquisitor, the input/output data storage, the evaluation value calculator, the features extractor, the input parameter converter, and the next input parameter determinator.

Abstract: A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a corresponding node propagates to the observation point. The method further includes determining a weighted soft error probability for each logic element of the plurality of logic elements and determining a weighed soft error failure mode distribution for the cone of influence.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for correcting finite floating-point numerical simulation and optimization. Defining a loss function within a simulation space composed of a plurality of voxels each having an initial degree of freedom, the simulation space encompassing one or more interfaces of the component; defining an initial structure for the one or more interfaces in the simulation space; calculating, using a computer system with a finite floating-point precision, values for an electromagnetic field at each voxel using a finite-difference time domain solver to solve Maxwell's equations; and determining, for each voxel, whether to increase a respective numerical precision of respective values representing behavior of the electromagnetic field at the voxel above a threshold precision by the computer system and, in response, assigning one or more additional degrees of freedom to the voxel.

Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for designing a multimodal photonic component. In one aspect, a method includes defining a loss function within a simulation space including multiple voxels and encompassing features of the multimodal photonic component. The loss function corresponds to a target output mode profile for an input mode profile, where the target output mode profile includes a relationship between a set of operating conditions and one or more supported modes of the multimodal photonic component at a particular operative wavelength. The initial structure is defined for one or more features, where at least some of the voxels corresponding to features have a dimension smaller than a smallest operative wavelength of the multimodal photonic component, and values for structural parameters for the features are determined so that a loss according to the loss function is within a threshold loss.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

Abstract: A surface mounted technology (SMT) process prediction tool for intelligent decision making on PCB quality is disclosed.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: Failure-in-time (FIT) evaluation methods for an IC are provided. Data representing a layout of the IC is accessed, and the layout includes a metal line and a plurality of vertical interconnect accesses (VIAs). The metal line is divided into a first sub-line with a first line width and a second sub-line with a second line width. A plurality of nodes are picked along the first and second sub-lines of the metal line. The metal line is divided into a plurality of metal segments based on the nodes. FIT value is determined for each of the metal segments to verify the layout and fabricate the IC. The first line width is greater than the second line width.

Abstract: Motion detection is performed using layouts of different resolutions. A plurality of layouts at different resolutions are generated using an image. Sets of bounding boxes for the different layouts are generated based on areas indicative of motion for the respective layout. The different sets of bounding boxes are combined and motion of one or more objects represented in the image is detected based on combined set of bounding boxes.

Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.

Abstract: A method and system disclosed for validating technology file design rules, including obtaining a technology file with design rules that are to be validated. An input test case library is obtained with design rule cell-views for each corresponding design rules. The design rule cell-view includes a first set of failed test cases. An output data is generated by using Design Rule Driven (DRD) tool, to test the design rules based on the design rule cell-views. The test output data provides a second set of failed test cases associated with the corresponding design rule. A validation result is determined for each of the plurality of design rules based on the first set of failed test cases and the second set of failed test cases associated with the design rule. Finally, a validation report is generated including the validation result for each design rules.

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

Abstract: Aspects described herein relate to physical verification of a design of an integrated circuit to be manufactured on a semiconductor die. One example method involves inserting a virtual partition cell in a parent cell of a layout of a design of an integrated circuit. A child cell of the parent cell has a first portion that overlaps the virtual partition cell and a second portion that is outside of the virtual partition cell. The method also includes creating, by one or more processors, a hierarchy of cells having the child cell and the virtual partition cell descending from the parent cell, wherein the child cell has multiple instances in the hierarchy of cells, and performing a design rule check runset on the parent cell based on the hierarchy.

Abstract: In some embodiments, techniques for creating a fabricable segmented design for a physical device are provided. A computing system receives a design specification. The computing system generates a proposed segmented design based on the design specification. The computing system determines one or more fabricable segmented designs based on the proposed segmented design. The computing system determines an overall fabrication loss value based on the one or more fabricable segmented designs. The computing system backpropagates a gradient of the overall fabrication loss value to create an updated design specification.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.

Abstract: Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

Abstract: Disclosed is a method of placing a semiconductor device, the method being performed by a computing device, the method including: receiving information about a prohibited area designated so that a semiconductor device is not placed; and training a neural network model to place a semiconductor device based on characteristic information of the semiconductor device and the information about the prohibited area.

Abstract: In one embodiment, a computing system may access design data of a printed circuit board to be produced by a manufacturing process. The system may determine one or more corrections for the design data of the printed circuit board based on one or more correction rules for correcting one or more parameters associated with the printed circuit board. The system may automatically adjust one or more of the parameters associated with the design data of the printed circuit board based on the one or more corrections. The adjusted parameters may be associated with an impedance of the printed circuit board. The one or more corrections may cause the impendence of the printed circuit board to be independent from layer thickness variations of the printed circuit board to be produced by the manufacturing process.

Abstract: Disclosed herein are a cloud computing-based simulation apparatus and a method for operating the simulation apparatus. The method for operating a cloud computing-based simulation apparatus includes profiling a simulation in consideration of a simulation model and setup items that are requested by a user, when there is a history corresponding to results of the profiled simulation, calculating a resource configuration probability distribution for the simulation using the history, replicating the simulation environment to multiple simulation environments by selecting resource configurations in N simulation environments depending on the resource configuration probability distribution, where N is an integer of 2 or more, and simultaneously executing simulations in the multiple simulation environments.

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

Abstract: A method for detecting an open/short circuit on a PCB design layout includes: reading PCB data of a to-be-checked PCB design layout, to output an image of each PCB layer included in the PCB design layout; performing a first connectivity analysis on the image of each PCB layer to classify pad patterns connected with each other in the same layer into a corresponding child network group; performing a second connectivity analysis to classify child network groups in which pad patterns connected by the same electroplated hole, into a corresponding parent network group; reading IPC netlist data of the PCB design layout, to obtain a netlist network group in which each pad pattern is; and determining whether a netlist network relationship of the pad patterns is consistent with a network relationship obtained after the second connectivity analysis in order to determine whether there is an open/short circuit.

Abstract: According to an aspect of the present disclosure, a substrate state determining apparatus includes: an image capturing unit that captures an image of a substrate placed on a stage; a learning unit that executes a machine learning using training data in which information indicating a state of the substrate is attached to the image of the substrate, so as to generate a substrate state determination model in which the image of the substrate is taken as an input and a value related to the state of the substrate corresponding to the image of the substrate is taken as an output; and a determination unit that determines the state of the substrate corresponding to the image of the substrate captured by the image capturing unit, using the substrate state determination model generated by the learning unit.

Abstract: A 3D model evaluation system includes: a loading unit that loads 3D model data created by 3D CAD; a history checking unit that checks a creation history which is added to the 3D model data loaded by the loading unit and which is obtained in a case where the 3D model data is created by the 3D CAD; and an evaluation unit that evaluates a degree of coincidence between the creation history of the 3D model data checked by the history checking unit and a predetermined rule.

Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Embodiments relate to the layout of photonic integrated circuits using fixed coordinate grids. In some embodiments, a method includes receiving a request to place a first photonic component within a layout of a photonic integrated circuit. Positionings of components within the layout are represented in a design database utilizing a grid with fixed coordinates. The method further includes calculating, by a processor, precise coordinates and snapped coordinates for positioning of the first photonic component. The snapped coordinates have a precision consistent with the fixed coordinate grid and the precise coordinates have a higher precision than the snapped coordinates. The method further includes, in a design database, representing the positioning of the first photonic component utilizing both the precise coordinates and the snapped coordinates.

Abstract: A system enhances a system design to incorporate safety measures. The system receives a system design for processing through various stages of design using design tools, for example electronic design automation tools for introducing safety features in a circuit design. The system receives safety requirements for the system design, the safety requirements specifying safety measures for the system design. The system generates from the safety requirements, a safety specification storing a set of commands. The system generates a system design enhanced with safety measures. The enhanced system design it generated for at least a subset of the plurality of tools. A tool processes the generated safety specification to implement safety measures in the system design according to the received safety requirements.

Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.

Abstract: Embodiments of the invention include protecting against antenna violations in a macro having a clock mesh. Aspects include obtaining a design of the macro, the design including a clock layer having a plurality of clock pins and determining a longest vertical wire and a longest horizontal wire allowed based on a design of the clock mesh. Aspects also include identifying, based at least in part on the longest vertical wire and the longest horizontal wire, a plurality of checkbox regions for a clock pin of the plurality of clock pins and calculating a total diffusion area for each of the plurality of checkbox regions. Aspects further include adding, to the design of the macro, an antenna diode to the clock pin based on a determination that the total diffusion area for any of the plurality of checkbox regions is less than a threshold value.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.

Abstract: A method includes the following operations: receiving design rule violations of a first layout; classifying, according to first chip features of the first layout, a first violation of the design rule violations into a first class of predefined classes; generating a first vector array for at least one of the first chip features of the first layout, that is associated with the first violation; selecting, according to the first vector array, first operations from pre-stored operations; generating a second layout based on the first layout and the first operations.

Abstract: Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body.

Abstract: A method includes assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net. The voltage value associated with the net and included in the modified IC schematic is based on a comparison between the assigned default voltage value and the simulation voltage value of the net.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the hotspot clusters and centroids of the non-hotspot clusters. The system also creates a plurality of kernels configured to identify hotspots, where each kernel is constructed using the extracted critical features of the non-hotspot clusters and the extracted critical features from one of the hotspot clusters, and each kernel is configured to identify hotspot topologies different from hotspot topologies that the other kernels are configured to identify.

Abstract: A tool for monitoring a part condition includes a computerized device having a processor and a memory. The computerized device includes at least one of a camera and an image input and a network connection configured to connect the computerized device to a data network. The memory stores instructions for causing the processor to perform the steps of providing an initial micrograph of a part to a trained model, providing a data set representative of operating conditions of the part to the trained model, and outputting an expected state of the part from the trained model based at least in part on the input data set and the initial micrograph.

Abstract: Determining an installation sequence for a system assembly comprising a number of system branches attached to respective terminations is provided. The method comprising receiving schematics for a product into which the system assembly is to be installed, wherein the product comprises a number of openings. A largest termination in the assembly is compared the diameter of an opening through which it is to be routed. If the termination diameter is larger than the opening, an error is generated. If the termination is smaller opening, the diameter of the opening is decremented by a diameter of the system branch attached to termination. The steps are iteratively repeated for the next largest termination in the assembly until an error signal is generated for a termination or all terminations in the system assembly intended to pass through the opening are added as steps in the installation sequence.

Abstract: A report of results of validating a circuit can simplify a large number of error events, that can be generated when designing electrical circuits using computer aided design tools, by first filtering the large number of error events according to a user defined filter criteria. The filter results are processed by one or more report rules. Each of the report rules may generate one or more report results based on, at least, the filtered error events.