Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

Abstract: A method implemented by computer, for selecting representative paths for the analysis of the behavior of an integrated circuit according to a predefined analysis strategy, comprises the identification of the set of paths of the integrated circuit having logic gates and the construction of a list of the set of the paths. The method comprises: the selection of several criteria related to the behavior of the integrated circuit, chosen from among the following types: topology, usage, sensitivity, environment, criticality; the determination of values of the selected criteria for each of the identified paths; the application of a correlation function to aggregate the set of the values of criteria to define an aggregation criterion value; and the selection of a subset of representative paths from among the list of the paths, as a function of the value of the aggregation criterion of the paths and of the predefined analysis strategy.

Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.

Abstract: The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.

Abstract: An approach is described for implementing a GUI that provides a user interface for reviewing and correcting design rule violations within a CAD program. According to some embodiments, a user may enter a serial review process which may utilize contextual information to determine where to start that review process. Further, the serial review process may enable the user to review rule violations in an individual manner for a respective object. Furthermore, a dynamic directional violation identifier may be used to identify additional errors in the direction of movement, such as by processing a set of rules and parameters with respect to objects in the direction of movement. The serial review process and the dynamic directional violation identification may be combined in a single process such that as violations are reviewed, and corrections are attempted, they may be verified to determine if they generate additional violations.

Abstract: In various embodiments, a data integration system is disclosed which enables users to create a logical design which is platform and technology independent. The user can create a logical design that defines, at a high level, how a user wants data to flow between sources and targets. The tool can analyze the logical design, in view of the user's infrastructure, and create a physical design. The logical design can include a plurality of components corresponding to each source and target in the design, as well as operations such as joins or filters, and access points. Each component when transferred to the physical design generates code to perform operations on the data. Depending on the underlying technology (e.g., SQL Server, Oracle, Hadoop, etc.) and the language used (SQL, pig, etc.) the code generated by each component may be different.

Abstract: A design aware system, method, and computer program product are provided for detecting overlay-related defects in multi-patterned fabricated devices. In use, a design of a multi-patterned fabricated device is received by a computer system. Then, the computer system automatically determines from the design one or more areas of the design that are prone to causing overlay errors. Further, an indication of the determined one or more areas is output by the computer system to an inspection system for use in inspecting a multi-patterned device fabricated in accordance with the design.

Abstract: Techniques are disclosed for performing flood-fill operations on vector artwork. In one embodiment, a region under a point of interest (POI) of vector artwork is rasterized and flood-filled, and an initial bounding shape around that area is used as a first guess as to the area to be filled. In other cases, the initial bounding shape is created around some initial area that includes the POI (no rasterization). In any such case, vector objects having bounding shapes that intersect the initial bounding shape are identified and fed into a planar map. After map planarization, a new bounding shape is created around a new area resulting from the planarizing and that includes the POI. In response to that bounding shape not extending beyond the initial bounding shape, a vector-based flood-fill operation can be performed on that new area. The process repeats if a new bounding shape extends beyond previous bounding shape.

Abstract: Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.

Abstract: A method for generating electric substation load transfer control parameters includes adjusting elements in a fundamental scale matrix according to a condition change of a power grid, wherein the fundamental scale matrix is constructed based on the topology structure of the power grid, and the elements in the fundamental scale matrix represent switch information and risk values of paths between nodes of the power grid, wherein the switch information represents number of switching times required for connecting two nodes of the power grid; and performing operations on the adjusted fundamental scale matrix to generate switch information and risk values of paths for electric substation load transfer control, as electric substation load transfer control parameters.

Abstract: A method for generating electric substation load transfer control parameters includes adjusting elements in a fundamental scale matrix according to a condition change of a power grid, wherein the fundamental scale matrix is constructed based on the topology structure of the power grid, and the elements in the fundamental scale matrix represent switch information and risk values of paths between nodes of the power grid, wherein the switch information represents number of switching times required for connecting two nodes of the power grid; and performing operations on the adjusted fundamental scale matrix to generate switch information and risk values of paths for electric substation load transfer control, as electric substation load transfer control parameters.

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

Abstract: Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design.

Abstract: A spatial model of a printed circuit board assembly is generated based on an input file. The spatial model is used to determine a spatial feature not directly specified in the input file. A manufacturing parameter is determined based at least in part on the determined spatial feature. A proposal to manufacture the printed circuit board assembly is generated programmatically based at least in part on the determined manufacturing parameter.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.

Abstract: Integrated circuit design layout files are partitioned into one or more design layout files containing data for Front-End-Of-Line sub-circuits and one or more design layout files containing data for Back-End-Of-Line sub-circuits. By sending each of the files to a separate foundry for manufacture, an intellectual property owner can ensure integrity of his property as no individual file alone contains sufficient information to deduce the overall function of the integrated circuit.

Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.

Abstract: A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates, and the design rule comprises N design constraints numbered 1 to N, wherein N is greater or equal two and each design constraint is a boolean-valued function of one or more of the coordinates. The set of test layouts includes: one or more zero-error layouts; one or more one-error layouts; and one or more two-error layouts. A zero-error layout is a layout that satisfies all of the design constraints. A one-error layout is a layout that violates exactly one of the design constraints. A two-error layout is a layout that violates exactly two of the design constraints.

Abstract: Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.

Abstract: Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.

Abstract: Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.

Abstract: A method, system, and computer program product to manage a network comprising a plurality of interconnected components are described. The method includes obtaining a set of all the components that are part of the network over time, and identifying one or more repeating patterns of components among the set of all the components as corresponding lower-level definitions to generate a hierarchical set of all the components. The method also includes obtaining time-varying information regarding topology and operational values within the network, and creating a representation of the network at a set of times based on the hierarchical set of all the components and the time-varying information.

Abstract: A method, system, and computer program product to manage a network comprising a plurality of interconnected components are described. The method includes obtaining a set of all the components that are part of the network over time, and identifying one or more repeating patterns of components among the set of all the components as corresponding lower-level definitions to generate a hierarchical set of all the components. The method also includes obtaining time-varying information regarding topology and operational values within the network, and creating a representation of the network at a set of times based on the hierarchical set of all the components and the time-varying information.

Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

Abstract: A computer-implemented method for designing an integrated circuit includes determining a timing slack associated with a first cell of the integrated circuit that is physically adjacent to a second cell of the integrated circuit, the second cell including an implant region that is in violation of an implant width design rule associated with the integrated circuit, determining that the timing slack is greater than a change in timing slack associated with expanding the implant region into the first cell, and, in response, expanding the implant region from first cell into the second cell to form a larger implant region.

Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

Abstract: Computer-implemented techniques are disclosed for verifying circuit designs using dynamic problem generation. A device under test (DUT) is modeled as part of a test bench where the test bench is a random process. A set of constraints is solved to generate stimuli for the DUT. Problem generation is repeated numerous times throughout a verification process with problems and sub-problems being generated and solved. When a problem is solved, the problem structure can be stored in a cache. The storage can be based on entropy of variables used in the problem. The problem storage cache can be searched for previously stored problems which match a current problem. By retrieving a problem structure from cache, the computational burden is reduced during verification. Problems can be multi-phase problems with storage and retrieval of problem structures based on the phase level. Caching can be accomplished using an information theoretic approach.

Abstract: A computer-implemented method includes receiving layout information associated with a circuit design at an extractor, and generating three-dimensional (3-D) heat source grid information based on the layout information, an extracted netlist, and wire information. The method also includes sending the wire information to an electromigration(EM)/current(IR) analyzer, sending the extracted netlist to a circuit simulator, and sending the 3-D heat source grid information to a thermal analysis component. The circuit simulator is configured to generate temperature waveforms and current waveforms based on the extracted netlist. The thermal analysis component is configured to generate heat source information to be provided to the EM/IR analyzer. The method further includes determining, at the EM/IR analyzer, an electromigration risk associated with a wire based on the wire information, the current waveforms, and the heat source information.

Abstract: Disclosed herein are embodiments of an interactive design tool for designing electronic and photonic circuits, where features of the design may be displayed on the interactive layout GUIs as design objects. Design objects in a design database may include various types of design features, such as circuits, pins or ports, wires, and photonic waveguides. The design objects may be displayed on interactive layout GUIs according to the attribute data stored in the design database. The design objects may also be displayed according to a type of design feature represented by the design object. For example, the embodiments described herein may represent a “port” as having a shape and size that comports with the eccentricities of both electrical and photonic designs. A port may be a hierarchical connection element in the database allowing the logical and physical connection between an instance and the geometries in the corresponding instance master.

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design including a first net and a second net. The method may include identifying a shortest path between the first net and the second net and determining at least one common shape associated with the shortest path. The method may also include identifying one or more adjacent shapes to the at least one common shape and identifying at least one fork associated with each of the one or more connectivity reference points. The method may further include analyzing an intermediate fork of the at least one fork to identify an electrical short associated with the electronic design.

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Abstract: A method of determining a device type and device properties includes receiving an input file including information related to a device, and identifying at least one layer set within the input file. The method further includes identifying at least one feature present in layer set. The method further includes analyzing a relationship between the at least one feature formed by the first layer and at least one feature formed by the second layer to determine at least one layer set relationship. The method further includes comparing the layer set relationship with at least one template layer set relationship. The method further includes determining the device type of the device based on the comparison between the layer set relationship and the template layer set relationship. The method further includes determining the device properties of the device based on the layer set relationship, the device type or the at least one feature.

Abstract: An information processing apparatus includes a processor and a memory configured to store therein correspondence information defining an association relationship between position of the connection point of circuits and information of wiring which has one end located at the position of the connection point. The processor is configured to identify a first circuit from a group of multiple images representing an overall circuit, acquire, based on the correspondence information, information of a first position of a connection point of a second circuit at which the identified first circuit is coupled and information of a first wiring which one end is located at the first position, extract, from the second image, a partial image that includes images of the first wiring and the connection point at the first position based on the acquired information of the first position and the first wiring, and output the extracted partial image.

Abstract: A mechanism is provided in a data processing system for detecting lithographic hotspots. The mechanism receives a design layout. The mechanism generates spatial pattern clips from the design layout. The mechanism performs a transform on the spatial pattern clips to form frequency domain pattern clips. The mechanism performs feature extraction on the frequency domain pattern clips to form frequency domain features. The mechanism utilizes the extracted features on a set of training samples to train a machine learning classifier model. The mechanism classifies a set of previously unseen patterns, based on frequency domain features of the previously unseen patterns using the trained machine learning classifier model, into hotspots and non-hotspots.

Abstract: A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.

Abstract: A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.

Abstract: A method for detecting static-current failure devices in a chip is provided. The method includes providing a chip and determining existence of a static-current failure device in the chip. The method also includes detecting positions of a plurality of hotspots in the chip when the existence of the static-current failure devices is determined; and selecting a common circuit path according to position information of the hotspots in a circuit layout file of the chip. Further, the method includes converting a circuit layout of the common circuit path into a corresponding electrical diagram and marking the positions of the plurality of hotspots on corresponding positions on the electrical diagram; and detecting a shared device of the hotspots in the electrical diagram. Further, the method includes marking a position of the shared device in the circuit layout as a position of a static-current failure device.

Abstract: A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s), and includes 13-CPP and 17-CPP D flip-flop cells, is disclosed, along with wafers, chips and systems constructed from such cells.

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract: A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 layer is disclosed, along with wafers, chips and systems constructed from such cells.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of the device using a device design, a device model and a simulation scenario; and one or more violation monitor for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule of the one or more violation rules during the executing the simulation of the device and, for each violation, determine information representing the respective violation, wherein the detecting the one or more violations comprises comparing a simulated parameter against a threshold.

Abstract: A method for designing a layout of a semiconductor integrated circuit device includes placing a plurality of standard cells respectively constituting a plurality of functional blocks in a part of a logic circuit placement region, placing a plurality of basic cells in a part of regions of the logic circuit placement region in which no standard cells are placed, and placing at least one diode cell in at least a part of regions of the logic circuit placement region in which no standard cells and no basic cells are placed, the diode cell including a first and a second diode, the first diode being connected between a gate electrode of a predetermined transistor and a first power supply line and the second diode between the gate electrode and a second power supply line.