Verification Patents (Class 716/111)
  • Patent number: 11150304
    Abstract: Examples described herein include examples of method for predicting battery performance of a battery comprising collecting battery data corresponding to a plurality of batteries with characteristics similar to the battery during a first time period, storing the collected battery data in a staging memory, generating a logarithmic regression based on the collected battery data, and predicting battery performance for the battery based on the logarithmic regression.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 19, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matheus Eichelberger, John Landry, Marcio Maraschin, Roberto Argenta Coutinho
  • Patent number: 11100270
    Abstract: A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical layout of connectors (414) and pad pins (416). For each identified instance (402, 404) of the pattern (300) within the design image (400), the mapping of connections is assigned to respective connectors (414) and pad pins (416) in the identified instance (402, 404).
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 24, 2021
    Assignee: Synopsys, Inc.
    Inventors: Xun Liu, Shamik Saha
  • Patent number: 11092901
    Abstract: Critical dimension values can be obtained from wafer structures at predefined measurement sites. Coefficients of a preset model and another model with a different term are determined using critical dimension values from the measurement sites. The models approximate the critical dimension values, the process parameters and/or correction values of the process parameters as a function of at least two position coordinates. An updated model is selected from the models based on a criterion weighting the residuals between approximated critical dimension values, the number of terms of the model and/or the order or the terms of the model.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 17, 2021
    Assignee: Qoniac GmbH
    Inventors: Stefan Buhl, Philip Groeger, Patrick Lomtscher
  • Patent number: 11018084
    Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
  • Patent number: 10984161
    Abstract: The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rajdeep Mukherjee, Ravi Prakash, Benjamin Meng-Ching Chen, Habeeb Farah, Ziyad Hanna
  • Patent number: 10977416
    Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yen-Hung Lin
  • Patent number: 10936785
    Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang, Jia Han Lin
  • Patent number: 10901025
    Abstract: Methods and systems for measuring degradation includes measuring an initial electrical characteristic of a test device in a ring oscillator that includes multiple oscillator stages and a test stage having a delay stage and the test device. The ring oscillator is operated for a period of time. The electrical characteristic of the test device is measured after operating the ring oscillator. A level of degradation in the test device is determined using a processor based on the measurements of the electrical characteristic of the test device.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Barry P. Linder, Keith A. Jenkins
  • Patent number: 10853553
    Abstract: Improving an initial via in a circuit comprises: obtaining layout information associated with an initial via structure in a circuit, the initial via comprising an initial lower metal enclosure and an initial upper metal enclosure connected by an initial cut; determining layout information associated with a multiconnection via structure comprising a plurality of sibling vias having at least one additional upper metal enclosure and at least one additional lower metal enclosure; updating the layout information associated with the initial via with the layout information associated with the multiconnection via structure; and outputting the updated layout information. The plurality of sibling vias are connected by a plurality of corresponding sibling cuts, and the multiconnection via structure has lower resistance than the initial via structure. In some embodiments, the multiconnection via is efficiently represented in using a master template.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Avatar Integrated Systems, Inc.
    Inventors: Ping-San Tzeng, Mingsheng Han, Yucheng Wang
  • Patent number: 10834600
    Abstract: An example method includes obtaining a plurality of data items. Each data item includes an indication of a particular location, an indication that a wireless signal from a first access point was observed at that location, and an indication of a time at which the wireless signal from the first access point was observed at that location. The method also includes determining a locational stability of the first access point based on the data items. Determining the locational stability of the first access point includes clustering the plurality of data items into one or more clusters based on the locations indicated in the plurality of data items, determining whether the N most recent data items are associated with a common cluster, and determining whether a time span between the N most recent data items exceeds a threshold period of time.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: Margaret H. Tam, David Benjamin Millman, Brian Stephen Smith, Benjamin A. Detwiler
  • Patent number: 10831939
    Abstract: For printed circuit board (“PCB”) design, methods, systems, and apparatuses are disclosed. One apparatus includes a component ID module that identifies a PCB component to be placed on a current board design; a search module that displays one or more instances of previous board designs containing the identified PCB component, wherein displaying the one or more instances of previous board designs containing the identified PCB component comprises displaying a region surrounding the identified PCB component; and an import module that imports a selected portion of a board design into the current board design from a selected one of the instances of previous board designs containing the identified PCB component.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Christo, David Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10776556
    Abstract: A wiring board design support apparatus, in which a plurality of vias are arranged on a wiring board, includes a design information storage unit that stores design information of vias and wirings to be arranged on the wiring board, and a wiring board via arrangement unit that moves, on a basis of the design information, positions of lattice points arranged with same intervals in vertical and horizontal directions by a given moving amount in a vertical direction and a horizontal direction while alternately changing a moving direction in the horizontal direction of the lattice points for each row of the lattice and alternately changing a moving direction in the vertical direction of the lattice points for each column of the lattice, so as to arrange vias at positions of the lattice points after movement.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 15, 2020
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Katsushi Mikuni, Ryuichi Yagisawa, Akitsugu Yamaguchi
  • Patent number: 10628623
    Abstract: A recording medium recording a detour wiring check program, the processing includes: acquiring target feature information regarding a target path in a target circuit and target positional information indicating a position of each cell on the target path; using a storage storing size information regarding a size of a frame used to determine whether there is a possibility that a wiring which couples cells on a path in a circuit detours; determining whether each cell between transmission and reception cells in the target path is included in a frame, which has a size based on target size information corresponding to the target feature information; and outputting that there is the possibility that the wiring which couples each cells on the target path detours when it is determined that at least one cell among the cells between the transmission and reception cells is not included in the frame.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Michitaka Hashimoto
  • Patent number: 10564706
    Abstract: A power source analysis method includes receiving a target number, performing voltage drop analysis on a plurality of power sources in a power delivery network (PDN) to determine respective supply currents of the power sources, sorting the supply currents of the power sources, and selecting a plurality of target power sources from the power sources according to a sorted result. The total number of the selected target power sources equals the target number.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 18, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu Lin, Ding-Ming Kwai, I-Hsuan Lee
  • Patent number: 10546090
    Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: January 28, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Gary B Nifong, Jun Chen, Karthikeyan Muthalagu, James Lewis Nance, Zhen Ren, Ying Shi
  • Patent number: 10540474
    Abstract: A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 21, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Sheng-Tsai Wu, Ming-Ji Dai, Chih-Ming Shen
  • Patent number: 10540475
    Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10523186
    Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Arm Limited
    Inventors: Balaji Venu, Reiley Jeyapaul, Xabier Iturbe, Matthew James Horsnell, David Michael Gilday
  • Patent number: 10504853
    Abstract: An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive feature. The bumps are disposed on the first semiconductor die and are connected to the first conductive feature. The substrate includes a second conductive feature. The bumps are electrically connected to the second conductive feature. The first conductive feature, the bumps, and the second conductive feature are configured to form at least one ring structure.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 10, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10474785
    Abstract: A device receives void configuration information that identifies a set of rules for generating void information based on printed circuit board (PCB) design information, and receives, based on receiving the void configuration information, the PCB design information that identifies via information of a PCB. The device compares, based on receiving the PCB design information, the set of rules, associated with the void configuration information, and the via information associated with the PCB design information, and generates the void information based on comparing the set of rules, associated with the void configuration information, and the via information associated with the PCB design information. The void information includes a set of parameters associated with a set of voids to be included in the PCB. The device performs an action based on generating the void information.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 12, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Venkata G Ramanan, John P. Nguyen, Santosh Kumar Pappu
  • Patent number: 10467370
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: November 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Arnold Jean Marie Gustave Ginetti, Preeti Chauhan, Nikhil Gupta, Vikas Aggarwal, Vikrant Khanna
  • Patent number: 10444276
    Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Hoe Cheon, Chan Seok Hwang
  • Patent number: 10423741
    Abstract: A method including selecting multiple input parameters of a device configuration environment to perform multiple simulations on an electronic device defined by the device configuration environment is provided. The method with multiple values for the multiple input parameters and a value of an output parameter resulting from the multiple simulations, and extracting a distribution of output parameter values and a distribution of input parameter values from a database. The method also includes finding a correlation involving the multiple input parameters and the output parameter based on a target range of the output parameter, and identifying an expected value of the output parameter using a range of values of the multiple input parameters in the correlation involving the multiple input parameters and the output parameter. A system and a nontransitory, computer-readable medium including instructions to perform the above method are also provided.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 24, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Michele Petracca, Yosinori Watanabe, Yael Kinderman, Shlomi Uziel, Ido Avraham
  • Patent number: 10372865
    Abstract: Disclosed aspects relate to facilitating system design based on unified chip specification. It can be determined based on the system design that a first interface of a first chip is to be connected to a second interface of a second chip. Then a first configuration of the first interface and a second configuration of the second interface are determined based on a unified specification. The unified specification at least specifies configurations of a plurality of chip interfaces for respective usages. A hardware design may be automatically generated based on the first and second configurations. The hardware design may include a hardware-level connection between the first and second interfaces.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yang Liu, Yong Lu, Peng LM Shao, Jiang Yu
  • Patent number: 10311194
    Abstract: According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Andrew P. Hoover, Chandrakanth Ramesh, David A. Petermann
  • Patent number: 10289583
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device emulates a first serial port at the embedded-system device. The embedded-system device exposes the first serial port to a host of the embedded-system device through a USB connection. The embedded-system device receives first command or data from the host through the first serial port. The embedded-system device processes the first command or data.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 14, 2019
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Venkatesan Balakrishnan, Padma Devaraj, Anand Krishnan Vadivelu
  • Patent number: 10263380
    Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 16, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Darko R. Popovic
  • Patent number: 10262092
    Abstract: A method for determining mismatch variation of circuit components in a circuit is provided. The method includes determining a mismatch contribution for a specification of an integrated circuit design and displaying a list of components in the circuit design sorted according to the mismatch contribution. The method also includes displaying an adjustable scale for a size of the component, modifying the circuit design according to with the size of the component adjusted according to a user input to the adjustable scale, determining an adjusted mismatch contribution of the component, and displaying in the list of components a modified value of the mismatch contribution, and a modified value of an overall standard deviation for the specification in the circuit design.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 16, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu, Catherine Bunting
  • Patent number: 10247769
    Abstract: Methods and systems for measuring degradation includes measuring an initial electrical characteristic of a test device in a ring oscillator that includes multiple oscillator stages, each having a delay stage and one or more fan-out devices, and a test stage having a delay stage and the test device. The ring oscillator is operated for a period of time. The electrical characteristic of the test device is measured after operating the ring oscillator. A level of degradation in the test device is determined using a processor based on the measurements of the electrical characteristic of the test device.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barry P. Linder, Keith A. Jenkins
  • Patent number: 10120037
    Abstract: A power inductor evaluation apparatus includes a storage unit and a determination unit. The storage unit stores the simulation model of a DC-DC converter. The simulation model includes the equivalent circuit model of a power inductor, including a DC superimposition characteristics slope ? and a saturation current Isat as parameters. The determination unit inputs the DC superimposition characteristics slope ? and the saturation current Isat into the simulation model of the DC-DC converter and performs simulation, and determines whether or not the power inductor having the DC superimposition characteristics slope ? and the saturation current Isat is usable on the basis of whether or not the simulation results satisfy design requirements (e.g, a permissible ripple voltage and a peak current).
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: November 6, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Ko Yamanaga
  • Patent number: 10095640
    Abstract: A computer-implemented method for transferring data over a bus from a host to a device is presented. The method includes determining a size of the data to be transferred, transferring the data using normal mode when the size is below a threshold, and transferring the data using burst mode when the size is equal to or larger than the threshold.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 9, 2018
    Assignee: SYNOPSYS, INC.
    Inventor: Frédéric Dumoulin
  • Patent number: 10095827
    Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10083272
    Abstract: Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Jason D. Hibbeler, Dongbing Shao, Robert C. Wong
  • Patent number: 10048898
    Abstract: A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 14, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Niles Yang, Xinde Hu, Zhenlei Shen
  • Patent number: 10002218
    Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 19, 2018
    Assignee: Cavium, Inc.
    Inventors: Shahid Ikram, Isam Akkawi, Richard Eugene Kessler, James Ellis, David Asher
  • Patent number: 9996641
    Abstract: A thermal simulation device for an integrated circuit according to the disclosure comprises a thermal analysis unit and a mesh size analysis unit. The thermal analysis unit performs a thermal analysis of the integrated circuit to obtain temperatures of the center point and boundary of each function block. The mesh size analysis unit determines the cell number in the mesh of each function block. The thermal analysis unit computes a temperature of the center point and boundary of each cell in every function block according to the temperatures of the boundary of each function block.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 12, 2018
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Lih-Yih Chiou, Liang-Ying Lu
  • Patent number: 9946626
    Abstract: A runtime of a computer program may be measured by providing the compiled computer program with at least a first watchpoint and a second watchpoint at respective first and second code locations, running the compiled computer program on a computing device, measuring a first time parameter at the first watchpoint and a second time parameter at the second watchpoint, and determining the runtime of at least part of the compiled computer program in terms of the second time parameter and the first time parameter.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 17, 2018
    Assignee: CODESYS Holding GmbH
    Inventors: Wolfgang Haggenmüller, Dieter Hess, Bernhard Werner
  • Patent number: 9934352
    Abstract: A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 9928326
    Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be analyzed, a module that is configured to perform a table look-up for components of the plurality of components, a module that is configured to acquire a result for the condition to be analyzed based on information in a table in which a component of the plurality of components is defined, and a module that is configured to conduct the analysis of the circuit using the result based on the information in the table for the component.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emrah Acar, Rajiv V. Joshi, Tong Li
  • Patent number: 9928327
    Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, acquiring a result for the condition to be analyzed based on information in a table in which a component of the plurality of components is defined, and conducting the analysis of the system using the result based on the information in the table for the component.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emrah Acar, Rajiv V. Joshi, Tong Li
  • Patent number: 9773080
    Abstract: A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 26, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Yeong-Jar Chang, Juin-Ming Lu, Liang-Chia Cheng
  • Patent number: 9768767
    Abstract: A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: September 19, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Miodrag Potkonjak
  • Patent number: 9720478
    Abstract: A storage battery monitoring method receives identification information indicating a storage battery system and characteristic data of a storage battery, the characteristic data including history information which indicates charging and discharging history of the storage battery; determines, based on the received history information, a deterioration model corresponding to the storage battery from among deterioration models managed in a database, the deterioration models each indicating a relationship between a state of health and a number of charging and discharging cycles performed by the battery as indicated by the charging and discharging history; generates control data for suppressing deterioration of the storage battery at a predetermined point in time according to the corresponding deterioration model; and transmits the generated control data to cause the storage battery system to control the storage battery.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: August 1, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Hiroshi Hanafusa
  • Patent number: 9659115
    Abstract: Among other things, one or more systems and techniques for analyzing a tiered semiconductor structure are provided. One or more segments are defined for the tiered semiconductor structure. The one or more segments are iteratively evaluated during electrical simulation while taking into account thermal properties to determine power metrics for the segments. The power metrics are used to determine temperatures generated by integrated circuitry within the segments. Responsive to a segment having a temperature above a temperature threshold, a temperature action plan, such as providing an alert or inserting one or more thermal release structures into the segment, is implemented. In this way, the one or more segments are iteratively evaluated to identify and resolve thermal and reliability issues.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chih-Liang Chen, Jiann-Tyng Tzeng, Shu-Hui Sung, Charles Chew-Yuen Young
  • Patent number: 9582622
    Abstract: A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Raju Balasubramanian, Erich C. Schanzenbach, Howard H. Smith, Anurag P. Umbarkar
  • Patent number: 9557764
    Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 31, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chen-Feng Chiang, Kai-Hsin Chen, Ming-Shi Liou, Chih-Tsung Yao
  • Patent number: 9471745
    Abstract: A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where the potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of the integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 18, 2016
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Ankush Oberai
  • Patent number: 9449140
    Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Chang Hsu, HungLung Lin, Ying-Yu Shen, Wen-Ju Yang, Ken-Hsien Hsieh
  • Patent number: 9436516
    Abstract: A virtual machines management apparatus includes a virtual machine controller, a history storage, and a planning module. The virtual machine controller is configured to migrate virtual machines between plural physical servers. The history storage is configured to store, for each set of first virtual machines that were migrated to a same migration destination physical server parallel in time among the virtual machines migrated, history information. The planning module is configured to determine as to whether it is possible to start migrating a planning target virtual machine to a candidate migration destination physical server at a candidate migration start time based on a residual resource amount of the candidate migration destination physical server, a resource consumption of the planning target virtual machine, a sum of resource consumptions of migration-scheduled virtual machines, and the history information.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yu Kaneko, Shigeo Matsuzawa, Tomonori Maegawa
  • Patent number: 9438242
    Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: September 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anis M. Jarrar, Mark D. Hall, David R. Tipple, Surya Veeraraghavan