Abstract: Methods according to the disclosure identify at least one corner violation including a pair of fill cells of the fill region having a corner-to-corner shape profile that violates a manufacturing specification for the fill region of the IC layout; creating an exclusion layer for the at least one corner violation of the IC layout; removing the at least one corner violation from the fill region using the exclusion layer to form a modified IC layout, wherein at least a portion of each of the pair of fill cells remains in the modified IC layout after removing the at least one corner violation; and manufacturing the modified IC layout to include a fill shape based on the fill region after removing the at least one corner violation, the fill shape being compliant with the manufacturing specification for the fill region of the IC layout.

Abstract: A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to t

Abstract: In an electronic circuit design system, dynamic visual guidance for relative placement of mutually paired electronic components, such as a bypass capacitance portion and a power pin in a power domain, is provided. A first, selected component is adaptively paired with one of a plurality of second components eligible for pairing with the first component, according to predetermined pairing criteria such as proximity criteria. A mutual placement zone between the paired components is generated to define a locus of valid placement locations of the paired first and second components one with respect to the other according to predetermined placement criteria therefor. Visual indicia to represent the mutual placement zone is generated, thereby providing visual guidance to reposition the first component.

Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.

Abstract: A candidate defect may be identified at a semiconductor wafer. A determination may be made as to whether the candidate defect at the semiconductor wafer corresponds to a systematic defect or a random defect. In response to determining that the candidate defect at the semiconductor wafer corresponds to a systematic detect, the candidate defect at the semiconductor wafer may be provided to a defect review tool for review by the defect review tool.

Abstract: A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

Abstract: A computer-implemented method, computer program product, and computer processing system are provided for generating synthetic layout patterns. The method includes receiving, by a processor, a set of physical design layouts that include a variety of layout patterns for neural network training. The method further includes generating, by the processor, a set of training layout pattern images for the neural network training by performing automatic image capturing on the set of physical design layouts with scripts. The method also includes training, by the processor, a feedforward neural network (FFNN)-based Variational Autoencoder (VAE) with the set of training layout pattern images. The method additionally includes generating, by the processor using the FFNN-based VAE, new synthetic layout images.

Abstract: A method for generating electric substation load transfer control parameters includes adjusting elements in a fundamental scale matrix according to a condition change of a power grid, wherein the fundamental scale matrix is constructed based on the topology structure of the power grid, and the elements in the fundamental scale matrix represent switch information and risk values of paths between nodes of the power grid, wherein the switch information represents number of switching times required for connecting two nodes of the power grid; and performing operations on the adjusted fundamental scale matrix to generate switch information and risk values of paths for electric substation load transfer control, as electric substation load transfer control parameters.

Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.

Abstract: A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.

Abstract: A system and method for an interactive circuit layout design that provides spatially adaptive overlay indicative of parametric properties. A physical layout of an electrical circuit product is rendered on a display. At least one net of the physical layout is delineated into a plurality of net segments each having at least one physical property parametrically specified in a value therefor. For each net segment, a corresponding segment indicator is selectively rendered on the display, adaptively positioned and spatially mapped to the net segment corresponding thereto as a symbolic surrogate for the corresponding net segment within the physical layout. Selection of a net segment actuates determination of a behavior of the electrical circuit product during an operation consistent with an electrical response of the corresponding net segment. Editing of a net of the physical layout delineates a plurality of updated net segments for the edited net exclusive of other nets.

Abstract: Methods and software that allow one or more users to utilize custom pricing in the context of an electronic marketplace. Such custom pricing can be implemented by transmitting specifications of custom pricing engines and/or custom design document interrogator engines to the marketplace along with or independently from one or more design documents containing structures to be priced. Various corresponding and related methods and software are described.

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.

Abstract: A method, a non-transitory computer-readable medium, and an apparatus for optimizing a design layout of an integrated circuit (IC) includes: selecting layout regions from a full-chip design layout for the IC; determining pixel images for the layout regions by performing pixel-based mask optimization for the layout regions, in which each pixel image corresponds to a respective layout region; determining a backpropagation (BP) artificial neural network (ANN) model using the pixel images and the layout regions; and determining a full-chip pixel image for the full-chip design layout using the BP ANN model, in which the BP ANN model uses the full-chip design layout as input.

Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.

Abstract: A photonic design automation (PDA) tool to facilitate design of semiconductor photonic devices is described. In one example, the PDA tool includes a process design library including one or more photonics parameterized cells (pCells), a plurality of processor-executable photonics design functions including a design rule check (DRC) violation removal function, and a semiconductor technology-dependent parameter file including a plurality of design rules that define allowed semiconductor design patterns to be converted to a plurality of semiconductor fabrication mask designs in a first semiconductor technology. The PDA tool supports a graphical user interface (GUI) to provide access to the library of photonic pCells to create intuitive physical property layers for a photonic device, and processes the physical property layers using the DRC violation removal function and the design rules to automatically generate a plurality of mask design layers for a “DRC clean” physical layout of the photonics device.

Abstract: In one embodiment, a learning machine device initializes thresholds of a data representation of one or more data features, the thresholds specifying a first number of pre-defined bins (e.g., uniform and equidistant bins). Next, adjacent bins of the pre-defined bins having substantially similar weights may be reciprocally merged, the merging resulting in a second number of refined bins that is less than the first number. Notably, while merging, the device also learns weights of a linear decision rule associated with the one or more data features. Accordingly, a data-driven representation for a data-driven classifier may be established based on the refined bins and learned weights.

Abstract: Disclosed approaches for limiting use or a programmable IC involve a provider of programmable ICs generating, using one or more private keys of the provider, one or more signed configuration bitstreams from one or more circuit designs received from a customer. The provider changes the general purpose programmable IC into an application programmable IC that can only be programmed by the one or more signed configuration bitstreams. The application programmable IC and the one or more signed configuration bitstreams are provided from the provider to the customer.

Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree, and specific portions of the design are routed individually from other portions of the design.

Abstract: A spatial model of a printed circuit board assembly is generated based on an input file. The spatial model is used to determine a spatial feature not directly specified in the input file. A manufacturing parameter is determined based at least in part on the determined spatial feature. A proposal to manufacture the printed circuit board assembly is generated programmatically based at least in part on the determined manufacturing parameter.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.

Abstract: A via model generation method includes: acquiring via arrangement information including a hole diameter of a via formed in a board including a plurality of wiring layers, a clearance distance between a ground conductor formed in one wiring layer of the plurality of wiring layers and the via, and a ground via distance between the via and a ground via coupled to the ground conductor; acquiring board information including a relative dielectric constant of the board; calculating a capacitance component of the via by a first electromagnetic field analysis using the hole diameter of the via, the clearance distance, and the relative dielectric constant of the board; calculating an inductance component of the via by a second electromagnetic field analysis using the hole diameter of the via, the ground via distance, and the relative dielectric constant of the board; and generating a via model including the capacitance and inductance components.

Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

Abstract: A method for processing the Library Exchange Format (LEF) diagram of a layout includes the following steps: Step 1, breaking the LEF diagram into multiple rectangular segments; Step 2, numbering all rectangular segments; and Step 3, combining rectangular segments to obtain a larger rectangular segment and replacing corresponding uncombined rectangular segments with the larger combined rectangular segment. The method reduces the data size of the LEF file and increase the data transmission efficiency of the LEF file.

Abstract: A method of manufacturing a printed circuit board (PCB) includes determining a weft direction of the PCB, and defining a routing design of differential pairs. The routing design is designed to have a fixed region in the weft direction. The method further includes manufacturing the PCB according to the routing design.

Abstract: An information processing apparatus for design assistance including: a memory storing first correspondence relationship information in which feature information of a circuit and a value to be set to a parameter for use to cause an integrated circuit capable of configuring the circuit therein to configure the circuit are associated with each other, and second correspondence relationship information in which each of multiple values settable to the parameter and an improvement level of a performance of the circuit configured by the integrated circuit with the value set to the parameter are associated with each other; and a processor receives feature information related of a target circuit to be designed; if a value of a parameter set to the integrated circuit to configure the target circuit satisfies a predetermined constraint, the received feature information and the value are stored and accumulated in the first correspondence relationship information.

Abstract: This disclosure includes a variety of methods of describing a shape in a hierarchical manner, and uses of such a hierarchical description. In particular, this disclosure includes a method comprising: fitting one or more sub-shapes of a first order against a shape; determining an error of the fitting; and fitting one or more sub-shapes of a second order against the error.

Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.

Abstract: Disclosed are methods, systems, and articles of manufacture for manipulating a hierarchical structure of the electronic design. These techniques identify a set of layout components instantiated from a layout of an electronic design. This set of layout components may constitute, for example, a FigGroup. One or more schematic instances and corresponding schematic connectivity information may be identified from a schematic design of the electronic design, and the one or more schematic instances correspond to the set of layout components. A layout cell or a figure group may be generated for the set of layout components based in part or in whole upon the schematic connectivity information. The original layout may then be transformed into a transformed layout at least by replacing the set of layout components with the generated layout cell or figure group.

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

Abstract: A method for validating the design of an electronic circuit uses a static checker tool to verify the circuit design against rules and attributes of the components of the circuit. A power intent of the circuit, pins for power, ground and data signal inputs and outputs for each component, and a model for attributes and parameters of the pins are defined. The attributes of the components are defined in terms of input and output voltages; input and output currents; input and output voltage, current and data signal timing; and input and output voltage and current ranges and tolerances. A netlist of interconnections representing the designed circuit is validated against the power intent and the model for the attributes. A report is output describing the validity of the circuit based on the compatibility of the netlist, the power intent, and the model for the attributes of the components.

Abstract: A photonic design automation (PDA) tool to facilitate design of semiconductor photonic devices is described. In one example, the PDA tool includes a process design library including one or more photonics parameterized cells (pCells), a plurality of processor-executable photonics design functions including a design rule check (DRC) violation removal function, and a semiconductor technology-dependent parameter file including a plurality of design rules that define allowed semiconductor design patterns to be converted to a plurality of semiconductor fabrication mask designs in a first semiconductor technology. The PDA tool supports a graphical user interface (GUI) to provide access to the library of photonic pCells to create intuitive physical property layers for a photonic device, and processes the physical property layers using the DRC violation removal function and the design rules to automatically generate a plurality of mask design layers for a “DRC clean” physical layout of the photonics device.

Abstract: A method for floating node reduction uses a capacitance matrix that specifies coupling capacitances between signal nodes and floating nodes of an interconnect structure. Random walks are performed from a first signal node to the other signal nodes, wherein each of the random walks traverses one or more of the floating nodes. Each of the random walks is directed based on probabilities derived from the coupling capacitances of the capacitance matrix. A count is maintained for each of the other signal nodes, wherein each count specifies a number of the random walks that end on the corresponding signal node. The indirect coupling capacitance from the first signal node to a second signal node is selected to correspond with the total indirect coupling capacitance of the first signal node, times the count associated with the second signal node, divided by the total number of random walks.

Abstract: Identifying the interactions of a selected cell across a hierarchical diagram of an integrated circuit and mapping the ways in which the cell can interact with other structures in the hierarchy reduces the computational load for design rule checking (DRC) and design rules for manufacturing (DRM). To this end, a cell and multiple instances of the cell are identified within hierarchical design levels of the chip. The interactions between the cell and other cells within the hierarchy are subtracted from the cell boundary, and the results of the subtracting are merged in the cell boundary. By subtracting the results of the merging, identical interactions are identified across the multiple instances of the cell. The results of the subtracting are used to generate a virtual hierarchical layer identical (VHLi) which aids in the simulation and verification of the chip.

Abstract: Systems and methods for removing nuisance data from a defect scan of a wafer are disclosed. A processor receives a design file corresponding to a wafer having one or more z-layers. The processor receives critical areas of the wafer and instructs a subsystem to capture corresponding images of the wafer. Defect locations are received and the design file is aligned with the defect locations. Nuisance data is identified using the potential defect location and the one or more z-layers of the aligned design file. The processor then removes the identified nuisance data from the one or more potential defect locations.

Abstract: A design method for an image sensor device includes providing an initial design for an image sensor device. The initial design includes a pixel array region and a through-via region disposed proximate the pixel array region. The initial design has a first length between the pixel array region and the through-via region. The initial design has a second length that is a width of the through-via region. The design method includes analyzing a ratio of the second length and the first length, and modifying the initial design to achieve a ratio of the second length and the first length within a particular range.

Abstract: Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.

Abstract: Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad.

Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of circuits for managing results from list decode methods. In accordance with some examples disclosed herein, a plurality of potential error patterns for correcting errors in a codeword may be received. The plurality of potential error patterns may be generated using a plurality of different list decode methods. Error patterns among the plurality of potential error patterns may be determined and marked as candidate error patterns using a set of error pattern screens. Error weights may be assigned to the candidate error patterns based on a quantity of bit errors in each symbol included therein. Weights for candidate error patterns that are indicative of a memory device failure may be adjusted using a scaling factor. An error pattern among the candidate error patterns may be selected to correct the errors in the codeword based on the assigned error weights.

Abstract: This application discloses a computing system to receive electromigration design rules defining characteristics of integrated circuits configured to cause electromigration, generate a rules library including machine code implementing electromigration design rule checks for the characteristics defined by the electromigration design rules, and perform the electromigration design rule checks on a layout design of an integrated circuit by executing the machine code implementing the electromigration design rule checks on structures of the integrated circuit described in the layout design.

Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: The source code of a software artifact may be scanned, and a call tree model with leaf nodes may be generated based on the scan. A set of test cases can be executed against the software artifact and log data from the execution can be collected. A set of untested leaf nodes can be detected and a new set of test cases can be generated to test the untested nodes. The new set of test cases are executed and a subset of the test cases which cover the previously untested nodes are added to the existing set of test cases.

Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is not connected to any power rail.

Abstract: Systems and methods for extracting one or more electrical specifications from a prelayout simulation of an integrated circuit design, where the one or more electrical specification are utilized to generate a physical layout of one or more components of an integrated circuit.

Abstract: A design support apparatus for designing a circuit board includes an index indicator configured to obtain an index indicating a degree by which a section of a differential signal line pair, which satisfies a design reference, is occupied in an entire part of the differential signal line pair, and display the index on a display.

Abstract: A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 ?m×2 ?m, orders of magnitude smaller than MMI and directional couplers.