Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

Abstract: An electronic device may include a shaft insertable into a target area, and an electronic component configured to generate a signal. The electronic component may be on or within the shaft. The electronic device may also include at least one antenna on or within the shaft. The electronic device may also include a receiver operatively coupled to the antenna. The receiver may monitor an electrical characteristic of the antenna to identify an effect of an electromagnetic field on the electrical characteristic of the antenna. The electronic device may also include a processor communicatively coupled to the receiver. At least one of the receiver and the processor may predict an effect of the electromagnetic field on the signal generated by the electronic component, based at least in part on the effect of the electromagnetic field on the electrical characteristic of the antenna.

Abstract: A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.

Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

Abstract: In some embodiments, a computer-implemented method of generating a resistor comprises receiving a first resistor value, converting the resistor value into a plurality of resistor layout segments, and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value.

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

Abstract: The present invention discloses a calculation method of eddy current loss in magnetic materials based on magnetic-inductance. The present invention proposes a vector model of a magnetic circuit, an eddy current reaction is equivalent to a magnetic-inductance component in the magnetic circuit, and the eddy current loss can be fast calculated by the vector model of the magnetic circuit. When the frequency is high, the eddy current loss dominates an iron loss and can be estimated as an entire iron loss. The present invention proposes the vector model of the magnetic circuit based on which the calculation method of eddy current loss in magnetic materials is proposed as well. Through the proposed method the eddy current loss in magnetic materials can be directly calculated by using the magnetic-inductance and the magnetic flux in the magnetic circuit, which can provide guidance for design and performance evaluation of high-frequency electrical equipment from a brand new viewpoint.

Abstract: Extraction of capacitance values from a design of an electrical circuit can use a set of trained neural networks to generate extracted capacitance values from the circuit using a representation of the Green's function.

Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

Abstract: A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.

Abstract: An information processing apparatus specifies a first pattern indicating a first layer included in first circuit data. The information processing apparatus generates, based on first wiring included in a second pattern indicating a second layer that is adjacent to the first layer and a slit included in the first pattern, second circuit data by changing the first pattern to a third pattern including second wiring corresponding to the first wiring. The information processing apparatus generates, based on the second circuit data, training data for machine learning.

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.

Abstract: A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design.

Abstract: To check the timing of a signal path involving an integrated circuit block from an outside vendor, a signal path including a driver circuit, an interconnect, and a receiver circuit can be identified in the integrated circuit design. A substitute integrated circuit design can be generated by replacing the driver circuit of the signal path with a primitive standard library cell, providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool, and replacing the receiver circuit with one or more capacitors. A static timing analysis tool can then be executed on the substitute integrated circuit design to determine whether a propagation delay from the driver circuit to the receiver circuit of the signal path satisfies a timing requirement of the integrated circuit design.

Abstract: Disclosed is a technique for estimating crosstalk between a first and second electrical transmission lines. The method comprises obtaining measurements of a received near end crosstalk, NEXT, signal, the NEXT signal being received at a first end of the second transmission line over a time period as a result of an electrical signal sent onto the first transmission line from its first end, the obtained measurements being in the time domain. Subsequently, a crosstalk coupling estimate is obtained per transmission line sub-interval by compensating the obtained measurements in the time domain of the received NEXT signal for round-trip attenuation of the sent signal from the first end of the first line to the sub-interval and back to the first end of the second line, and an estimate of a total crosstalk coupling is obtained by adding together at least some of the obtained crosstalk coupling estimates per transmission line sub-interval.

Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model. Embodiments may also include generating routing information for each routing grid.

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit. The computing system also can implement a machine-learning classifier that, when trained with a training data set, can classify the physical design layout based on physical or electrical characteristics associated with the physical design layout, and can utilize the classification to select a set of scaling coefficients. The computing system can apply the selected set of the scaling coefficients to adjust coupling capacitances in the parasitic model and generate a parasitic netlist for the physical design layout. The computing system can generate the training data set by determining sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.

Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.

Abstract: One example includes a method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT) that includes at least one GaN transistor device. The method includes inserting the GaN transistor DUT into a test fixture comprising an inductor such that the inductor is coupled to the GaN transistor device to form a switching power regulator. The method also includes operating the switching power regulator at a DUT operating voltage to generate an output current through the inductor based on a DUT input voltage and a duty-cycle. The method also includes controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT. The method also includes measuring the output current and the DUT input voltage at least one of during and after the voltage surge-strike. The method further includes storing the measured output current and the measured DUT input voltage in a memory to specify device characteristics of the GaN transistor DUT.

Abstract: Techniques for noise impact on function (NIOF) reduction for an integrated circuit (IC) design are described herein. An aspect includes receiving a list of victim nets in which NIOF failures are present in an IC design. Another aspect includes attempting NIOF correction in each victim net of the list of victim nets. Another aspect includes, based on a failure of a NIOF correction in at least one victim net of the list of victim nets, saving the at least one victim net to a wire promote/demote list. Another aspect includes updating the list of victim nets based on the NIOF correction. Another aspect includes, based on determining that the updated list of victim nets is empty, promoting or demoting the at least one victim net from the wire promote/demote list in the IC design.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.

Abstract: In some embodiments, a method includes receiving an electronic document that comprises a plurality of sections. The method includes marking the plurality of sections as a content section or a non-content section using a visual attribute of the sections that includes at least one of a width of the section, a density of the plurality of hyperlinks in the section, a size of a font of text in the section and whether a title of the electronic document overlaps with text in the section. The method also includes storing the marking of the plurality of sections of the electronic document in a machine-readable medium.

Abstract: Examples described herein provide for a technique for metal track routing with buffer bank insertion in a representation of a hardware design of an integrated circuit. In an example, pins of ports of hardblocks in a placed layout are identified. Logical tracks for nets associated with the pins of the ports are generated and assigned to respective metal layers. Logical tracks and corresponding nets are grouped into respective groups. Buffer bank(s) is inserted into the placed layout. Each buffer bank is for a group of logical tracks and divides each logical track and net of the group of logical tracks. Each buffer bank has pins associated with the respective divided nets. Each pin of the buffer bank(s) is assigned to a middle or higher metal layer. Metal tracks are generated in a representation of a hardware layout based on the logical tracks and pins of the ports and buffer bank(s).

Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: A method for designing an integrated circuit includes steps of selecting a power rail of a cell, determining that a clearance distance for an electrical connection to or around the power rail is not sufficient to fit the electrical connection, selecting a power rail portion of the power rail for modification, and modifying a shape of the power rail portion to provide a clearance distance sufficient to fit the electrical connection. As clearance distances between features in an interconnection structure of an integrated circuit become smaller, manufacturing becomes more difficult and error-prone. Increasing clearance distances improves manufacturability of an integrated circuit. Modifying the shape of an integrated circuit power rail increases clearance distance to and/or around a power rail.

Abstract: A method of modeling a high speed channel in a semiconductor package, the high speed channel including a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, includes: receiving design information of the high speed channel, dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout; and obtaining an integrated modeling result of an entirety of the high speed channel by combining results of the first and second modeling operations.

Abstract: A method for simulating signal integrity of a hybrid model is provided, which includes: establishing a transient simulation link including a front-end chip model, a pre-link model and a terminating impedance model, where the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state; inputting the step response data to an input end of a channel simulation link, where the channel simulation link includes a relay chip model, a post-link model and a back-end chip model, and each of the relay chip model and the back-end chip model is an IBIS AMI model; and inputting a random code signal to the input end of the channel simulation link, and reading a signal outputted from an output end of the back-end chip and forming an eye pattern.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: Systems, apparatuses, and methods for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis or simulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals may be applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die.

Abstract: Embodiments may include receiving an unplaced layout associated with an electronic circuit design and one or more grouping requirements. Embodiments may further include identifying instances that need to be placed at the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may also analyzing one or more instances that need to be placed at the unplaced layout and the one or more areas of the unplaced layout configured to receive the one or more instances. Embodiments may further include determining a location and an orientation for each of the one or more instances based upon, at least in part, the analyzing. Embodiments may also include generating a placed layout based upon, at least in part, the determined location and orientation for each of the one or more instances. Embodiments may further include during the generation of the placed layout, routing the placed layout.

Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.

Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

Abstract: A sensor element includes: a main pump cell constituted by an inner pump electrode facing a first inner space into which a measurement gas is introduced, an external pump electrode provided on an element surface, and a solid electrolyte located therebetween; and a measurement pump cell constituted by the measurement electrode facing a second inner space which is communicated with the first inner space and functioning as a reduction catalyst for NOx, and a solid electrolyte located therebetween. The inner pump electrode has a planar shape in which two parts of a front end part relatively having a large area and a rear end part relatively having a small area are sequentially connected in this order from an upstream side in a longitudinal direction of the sensor element while satisfying requirements of a predetermined size and area.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: A computer-implemented method, and associated system and computer program product, for use in a design process for an integrated circuit (IC) comprises dividing a layout of a metal layer of the IC into a grid comprising a plurality of grid regions, calculating a respective weight for each grid region of the plurality of grid regions, and forming a plurality of groups based on a similarity of the respective weights. Each group of the plurality of groups respectively comprises one or more contiguous grid regions of the plurality of grid regions. The method further comprises assigning each group of the plurality of groups to a respective routing width group type of a plurality of routing width group types, and determining a location for one or more separator cells between adjacent groups of the plurality of groups that are of different routing width group types.

Abstract: The presently disclosed invention astutely turns the potentially detrimental crosstalk effect in nanocircuitry into an advantage by engineering interference among single lines. In one embodiment, a nanocircuit logic gate within an array of nanocircuitry comprises first and second aggressor metal conductive lines; a victim line; and an inverter coupled to the victim line; wherein the first and second aggressor conductive lines are positioned to induce a signal on the victim line. In another embodiment, a nanocircuit logic gate within an array of nanocircuitry comprises first and second aggressor metal conductive lines; a control aggressor metal conductive line; a victim line; and a first inverter coupled to the victim line; wherein the first and second aggressor conductive lines and the control aggressor conductive line are positioned to induce a signal on the victim line. Further embodiments include complex computational and logic structures based on these efficient logic circuits.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: An EDA tool trains a machine-learning optimization tool using quantized optimization solution (training) data generated by conventional optimization tools. Each training data entry includes an input vector and an associated output vector that have quantized component values respectively determined by associated operating characteristics of initial (non-optimal) and corresponding replacement (optimized) circuit portions, where each initial circuit portion is identified and replaced by the corresponding replacement circuit portion during optimization of an associated target IC design. The stored training data entries are used by the machine-learning optimization tool to generate an efficient (e.g., piecewise-linear) prediction function.

Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.

Abstract: Partitioning a set of data using a binary format to more evenly distribute data values across a set of data partitions. By using a system of matching binary indices in a “back to front” manner, data values stored in or associated with data partitions are more evenly balanced.

Abstract: An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.

Abstract: A circuit design apparatus includes a storage that stores a first capacitance of a capacitor associated with one or more usage conditions, and a controller that controls an amount of energy of the capacitor under a specified usage condition of the one or more usage conditions. The controller calculates a second capacitance under the specified usage condition based on a first relationship between the specified usage condition and the first capacitance, and calculates the amount of energy of the capacitor based on the calculated second capacitance.