Abstract: An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: An apparatus and method is described herein for reducing noise in a power distribution network for an interface. The power distribution network is characterized. And based on that characterization, worst case patterns for the interface are predicted and avoided. As one example, characterization includes providing a stimulus, such as a step function stimulus, and determining a mathematical function response, such as a step function response. Then, based on the step function response, a resonant frequency for the power distribution network is determined; from which patterns that cause the resonant frequency are identified/predicted. And when identified patterns are detected, they are scrambled or manipulated to avoid causing a worst-case noise scenario in an interface's power distribution network.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.

Abstract: An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed.

Abstract: Methods, systems and processor-readable media for automatic self-tracking of input deliverables for noise characterization. A noise characterization run to generate a noise model thereof can be automatically initiated. The noise model can be delivered into a repository in response to completing the noise characterization run and generating the noise model. Data associated with the noise model can be tracked for subsequent analysis including checking completeness and a correctness of the noise model delivered into the repository, The data associated with the noise model can then be rendered for the subsequent analysis. Data associated with the noise model can include, for example, information regarding pending tasks, assignment information, and data contained in a noise database.

Abstract: A method for calculating leakage current associated with an integrated circuit, includes selecting a sampling point at which an input signal for the integrated circuit is in a quiescent state and determining the leakage current associated with the integrated circuit using the selected sampling point.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Abstract: A signal generator produces a victim signal having crosstalk emulation by filtering and combining a victim signal waveform record file and an aggressor signal waveform record file generated using parameters selected by a user. A signal channel or a cascaded signal channel is characterized using one or more S-parameter arrays. The S-parameter array or arrays represent a mixed-mode multiple-port device under test. Coefficients of a NEXT filter, a FEXT filter and a forward transmission filter are derived from selected S-parameters of the S-parameter array. The aggressor signal is filtered individually by the NEXT and FEXT filters. The victim signal is summed with the filtered aggressor signal from the NEXT filter with the resulting summed signal being filtered by the forward transmission filter. The filtered signal from the forward transmission filter is summed with the filtered aggressor signal from the FEXT filter to generate a victim signal having crosstalk emulation.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; generating a layout suggestion when the crosstalk value is larger than the predetermined value.

Abstract: A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

Abstract: Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.

Abstract: Techniques generally disclosed herein relate to computation of a guard zone of a three-dimensional object. In some examples, guard zones may be computed by identifying intersection lines that couple adjacent planes of an object, and categorizing an external angle at an intersection line between adjacent planes as concave or convex. In some embodiments, for convex angles, a cylindrical surface can be determined that is located about an outside surface of the object and centered along the intersection line between the adjacent planes. In some embodiments, for concave angles, the external angle can be bisected with a bisection plane. A guard zone may be formed by one or more of (i) providing a guard zone plane parallel to the object that is a tangent to a given cylindrical surface, (ii) providing a guard zone plane parallel to the object that intersects a given bisection plane, and/or (iii) coupling adjacent guard zone planes.

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract: Disclosed are embodiments of a method, system and program storage device for accurately modeling parasitic capacitance(s) associated with a diffusion region of a silicon-on-insulator (SOI) device and doing so based, at least in part, on proximity to adjacent conductive structures. In these embodiments, the layout of an integrated circuit design can be analyzed to determine, for the diffusion region, shape, dimension and proximity information. Then, a formula can be developed and used for determining the parasitic capacitance between the diffusion region and the substrate below (CD-S). This formula can have a perimeter component, including a side edge component and, if applicable, a corner component, both of which account for the fact that CD-S is generally dependent on the distances between the diffusion region and any adjacent conductive structures. Additionally, the parasitic capacitance between the diffusion region and any adjacent conductive structure (CD-D) can be determined based on such distances.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract: In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.

Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.

Abstract: A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first keep out layer, and a reference layer are determined based on the stack-up parameters. The first keep-out layer is placed between the radio frequency layer having a first signal trace disposed thereon and the reference layer. A first keep-out region on the first keep-out layer is formed in corresponding to the first signal trace. Circuit layouts disposed inside the first keep-out region are removed. Consequently, the corresponding keep-out region may be automatically generated in accordance to the signal requirements of the signal trace while designing the circuit layout thereby increase circuit layout quality and efficiency thereof.

Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality of nets in an execution order determined, when one of the checks is passed, on the basis of other noise countermeasure design checks that may be skipped; and performing, if it is determined on the basis of at least a check result of a noise countermeasure design check which has been performed immediately before a corresponding check that there is a next noise countermeasure design check that may not be skipped in the execution order, the next noise countermeasure design check for each of the plurality of nets.

Abstract: Phase compensation in a differential pair of transmission lines, including: identifying, by a phase compensation module, a plurality of direction changes in the differential pair of transmission lines; determining, by the phase compensation module for each direction change in the differential pair of transmission lines, a direction change angle; and determining, by the phase compensation module for each direction change in the differential pair of transmission lines, the geometry of one or more phase correction humps to include in one transmission line of the differential pair of transmission lines in dependence upon the direction change angle.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.

Abstract: A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Abstract: Systems and methods receive a design of a circuit layout. The circuit layout has some available spaces. Such systems and methods automatically insert capacitor arrays in the specified spaces. Each of the capacitor arrays has capacitor cells, and each of the capacitor cells has capacitor structures and a buried implant. The process of inserting the capacitor arrays comprises a process of forming the capacitor arrays to either: grow the capacitor arrays to the size of the specified spaces; grow the capacitor arrays to a specified capacitance value within the restriction of the length dimension or the width dimension of the specified spaces; or grow the capacitor arrays to a specified capacitance value, irrespective of dimensional length dimension or width dimension limitations (where the only limitations are the dimensions of the specified space).

Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: In an embodiment, the design flow is modified to avoid the flattening process but still accurately annotate the transistors with stress parameters. The location-based stress parameters may be generated, but may not be provided to the LVS tool. Instead, a hierarchical LVS process may be performed, black-boxing lower level blocks that already have stress parameter assignments, preserving hierarchy, etc. The output database from LVS thus includes a cross reference between layout devices and schematic devices, as well as locations of the schematic devices. The database may then be queried for the transistors in the non-flattened design, and the stress parameters may be assigned to the transistors based on the location-based stress parameters. In this fashion the stress parameters may be assigned to the desired transistors, permitting annotation of these parameters into the schematics, without flattening the design and doing unnecessary work on blocks to be skipped.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each glitch-sensitive node, a circuit fanin cone is analyzed to look for circuit structures that can produce glitches. The integrated circuit design can be simulated and modified if the simulation indicates that a glitch would occur in the integrated circuit design.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.

Abstract: A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.

Abstract: A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.

Abstract: The invention of novel methods is described for efficient and accurate thermal simulation of a structure that can be primarily constructed using building blocks. These structures may include, but not limited to, semiconductor chips, photovoltaic/solar panels, battery packs, etc. The methods are formulated in hierarchical function spaces, rather than the physical space and provide three-dimensional (3D) steady-state and transient temperature profiles of the structure, which are as detailed as full-scale numerical simulation, using substantially less computational degrees-of-freedom (DOF). The number of DOF required is comparable to that of lumped thermal models, yet no ad-hoc modeling assumptions related to geometry, dimensions, temperature profiles, or heat flow paths are required. The methods can be applied to evaluate temperature profiles at different levels of granularity.

Abstract: In a method for detecting equivalent series inductances (ESL) of an electrical component of a printed circuit board (PCB), the electrical component and one or more signal lines connected with the electrical component are selected from a layout diagram of the PCB. The method selects a standard range of the ESL of the selected electrical component, calculates an ESL between each of the signal lines and a via hole corresponding to the signal line, and determines signal lines having ESL value that are not within the standard range. The method locates attribute data of the determined signal lines and the selected electrical component in the layout diagram of the PCB, and displays the attribute data of the determined signal lines and the selected electrical component on a display device.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: An iterative method may comprise obtaining a current input signal value for a current iteration, comparing the current input signal value with an output signal value determined in a previous iteration, updating a counter value determined in the previous iteration based on the comparison such that the updated counter value replaces the previously determined counter value, determining a slew value based on the counter value, and adding the slew value to the previously determined output signal value to generate a new current output signal value. Different slew values may be added to the previous output signal to obtain a new output signal. The counter value is updated to reflect recent trends in the input signals. For example, if the input signal is on an upward trend, the counter value may be relatively high because it is incremented each time an input signal exceeds a previously determined output signal.