Power (voltage Islands) Patents (Class 716/127)
  • Patent number: 10846452
    Abstract: At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Juhan Kim
  • Patent number: 10749506
    Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within said each power island. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of said one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of said one power island of the plurality of power islands to the target power level.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Patent number: 10642338
    Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Dileep J. Kurian, Pranjali S. Deshmukh, Sriram Kabisthalam Muthukumar, Ankit Gupta, Tanay Karnik, David Arditti Ilitzky, Saurabh Bhandari
  • Patent number: 10417371
    Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: September 17, 2019
    Assignee: ARM Limited
    Inventors: Karen Lee Delk, Marlin Wayne Frederick, Jr., Ravindra Narayana Rao
  • Patent number: 10339206
    Abstract: Aspects of the subject technology relate to systems and methods for representing complex constraints on widgets for a user interface, using a small set of common rules allowing developers to represent arbitrary one-to-one relationships between widgets. A layout tool may be provided that, in operation, displays a layout area to a developer. The layout tool may include a user interface (UI) inference engine that, when one or more widgets are placed and/or moved within the layout area, generates inferred constraints for the one or more widgets. These inferred constraints may be generated, with or without further input from the developer, based on the relative positions of the one or more widgets in the layout area. An infer-constraints button may be provided that, when selected following placement of widgets in the layout area, causes generation of inferred constraints for each of the widgets.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: July 2, 2019
    Assignee: Wing Aviation LLC
    Inventors: John Hoford, Nicolas Roard
  • Patent number: 10282503
    Abstract: Systems and methods relate to cell placement methodologies for improving length of diffusion of transistors. For example, a first transistor with a first diffusion node which is bounded by a first diffusion cut is identified in a transistor level layout. The first diffusion cut is replaced with a first floating gate, and a first filler cell with a first filler diffusion region is added to extend a length of diffusion of the first diffusion node. Increasing the length of diffusion leads to improving drive strength and performance of the first transistor.
    Type: Grant
    Filed: June 25, 2016
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Benjamin John Bowers, Anthony Correale, Jr., Tracey Della Rova
  • Patent number: 10243542
    Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 26, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Patent number: 10200015
    Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Patent number: 10185801
    Abstract: A method may include obtaining a design including cells and a power grid. The method may further include dividing the design into tiles, determining a voltage budget for a tile, calculating a voltage drop for each cell of the tile based on determining an activity factor for the cell and a peak current consumed by the cell, determining, for each cell of the tile and based on the power grid, an affected vicinity for the cell including one or more neighboring cells affected by a current drawn on the cell, determining an affected vicinity for the tile based on the affected vicinity for each cell of the subset, calculating a voltage drop for the tile based on the voltage drop for each cell of the affected vicinity for the tile, and detecting a voltage deviation when a difference between the voltage budget and the voltage drop exceeds a threshold.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 22, 2019
    Assignee: Oracle International Corporation
    Inventors: Kiran Kishore Vedantam, Aparna Ramachandran, James Ballard, Mark Russell O'brien, Sampanna Prashant Pathak
  • Patent number: 10133341
    Abstract: An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. A system power controller controls operation of the component power control circuitry by setting a power mode lock condition therein. When the power mode lock condition is met the component power control circuitry cannot change the selected power mode of the component. Power control over the component is thus partially delegated from the system power controller to the component power control circuitry.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 20, 2018
    Assignee: Arm Limited
    Inventors: Dominic William Brown, Ashley John Crawford, Christopher Vincent Severino, Tessil Thomas
  • Patent number: 10078356
    Abstract: Described is an apparatus which comprises: an Intellectual Property (IP) block; control logic operable to send a first command to the IP block to cause the first IP block to enter a first power state from a second power state; and a communicating fabric coupled to the IP block and to the control logic, the communicating fabric to send multiple packets with a first header from the IP block to the control logic after the first command is processed by the IP block, wherein the multiple packets are associated with multiple registers which are identified as registers whose contents are to be saved.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Vinit M. Abraham, Ramadass Nagarajan
  • Patent number: 9792064
    Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Alon Naveh, Doron Rajwan, Ryan D. Wells, Eric C. Samson
  • Patent number: 9660616
    Abstract: Systems and methods for managing power in an integrated circuit using power islands are disclosed. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 23, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L Hillman, Jon Shiell
  • Patent number: 9384316
    Abstract: According to one embodiment of the present invention, a method for reducing congestion in an integrated circuit design is provided. The method may include identifying a net, wherein the net defines a path on one or more of a plurality of conducting layers in an integrated circuit and the net has an associated signal transit time. The method may further include identifying a first subnet of the net in a congested area of the integrated circuit. The method may further include modifying the first subnet, such that the congested area becomes less congested. The method may further include identifying a second subnet of the net in an uncongested area of the integrated circuit. The method may further include modifying the second subnet, such that the signal transit time of the net decreases.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: July 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Harald Folberth, Sven Peyer, Sourav Saha
  • Patent number: 9166412
    Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: October 20, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L Hillman, Jon Shiell
  • Patent number: 9026973
    Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Chun Tien, Chen-Chi Wu, Kuo-Ji Chen
  • Patent number: 8943452
    Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 27, 2015
    Assignee: Synopsys Taiwan Co., Ltd.
    Inventors: Chih-Neng Hsu, I-Liang Lin, Wen-Chi Feng
  • Publication number: 20150012902
    Abstract: The invention provides an automatic mapping method for a distribution network based on logical layout, comprising (1) pretreating a model of the distribution network model by analyzing it, and partitioning and striping the distribution network model to generate a plurality of partial models; (2) analyzing an automatic mapping algorithm to be utilized by comparing a distribution network graph obtained by the algorithm with the distribution network model, to find out a basis for purposefully improving the partial models or the whole distribution network model; (3) achieving automatic layout of the partial models or the whole distribution network model on the basis of analysis of the automatic mapping algorithm to be utilized by combining with one or more of the force-directed layout algorithm, hybrid layout algorithm, dynamic interactive layout algorithm and an improved grid routing algorithm in order to generate the distribution network graph; and (4) analyzing and treating the automatic layout to achieve the
    Type: Application
    Filed: April 8, 2014
    Publication date: January 8, 2015
    Applicants: State Grid Corporation of China, State Grid Suzhou Power Supply Company, NARI Technology Co., Ltd, Jiangsu Electric Power Company
    Inventors: Jiaqing Zhao, Jianguo Yao, Chunlei Xu, Haodong Shen, Haibing Zhu, Kejun Qian, Zemie Dai, Xuesong Huo, Jiang Tian, Hongwei Du, Huiqun Li, Bing Bing Shen, Hongen Ding, Hong Yang, Chun Li, Yang Lv
  • Patent number: 8930872
    Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Netronome Systems, Incorporated
    Inventor: Gavin J. Stark
  • Publication number: 20140374873
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Application
    Filed: September 12, 2014
    Publication date: December 25, 2014
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • Patent number: 8914764
    Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
  • Patent number: 8910106
    Abstract: A capacitor arrangement assisting method wherein data entered by a user, such as the width w of a power supply wiring, the thickness h of a dielectric between the power supply wiring and a ground plane, the ESLcap of a capacitor, and a target frequency fT and a target impedance ZT of an IC, are received, the maximum allowable wiring length lmax of the power supply wiring is calculated on the basis of the received width w of the power supply wiring, the thickness h of the dielectric, the ESLcap of the capacitor, and the target impedance ZT of the IC at the target frequency fT, and the calculated maximum allowable wiring length lmax is displayed.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: December 9, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hidetoshi Yamamoto, Yusuke Isozumi, Kota Saito
  • Patent number: 8904326
    Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mu-Jen Huang, Chih Chi Hsiao, Wei-Ting Lin, Tsung-Hsin Yu, Chien-Wen Chen, Yung-Chow Peng
  • Publication number: 20140332971
    Abstract: An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Jen TSENG, Ting-Wei CHIANG, Wei-Yu CHEN, Ruei-Wun SUN, Hung-Jung TSENG, Shun Li CHEN, Li-Chun TIEN
  • Patent number: 8868395
    Abstract: In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: October 21, 2014
    Assignee: Synopsys, Inc.
    Inventors: He Dong, Michael Z. Chui, Andrey Y. Tarasevich
  • Publication number: 20140310671
    Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Inventors: Gottfried Beer, Dominic Maier, Gerhard Metzger-Brückl, Rainer Leuschner
  • Patent number: 8856714
    Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Sun Hwang, Sung-Hee Yun, Jae-Hoon Jeong, Won-Cheol Lee, Tae-Heon Lee, Young-Hoe Cheon
  • Patent number: 8856712
    Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 7, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Pancholi, Srikanth Bojja, Bhavin Odedara
  • Publication number: 20140264715
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • Patent number: 8832637
    Abstract: Layout information indicating locations of at least components and conductive layers in a printed circuit board, and layouts of conductive wiring patterns on the respective conductive layers and vias which electrically connect between the conductive layers is obtained from a memory. With reference to the layout information, path information indicating a path of one signal line is generated. With reference to the layout information and path information, a divide portion where a path of a return current corresponding to a signal current of the signal line is divided are detected. With reference to the layout information and path information, information indicating a detour path of the return current in a neighborhood of the divide portion is generated.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 9, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshisato Sadamatsu, Shinichi Hama
  • Patent number: 8826203
    Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: John Darringer, Jeonghee Shin
  • Patent number: 8813016
    Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 8806411
    Abstract: A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 12, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshinao Ishii
  • Patent number: 8789000
    Abstract: A system and design methodology for performing routing in an integrated circuit design is disclosed. An integrated circuit design is first created using standard cells having metal level 2 (M2) power rails. Routing is performed and power rail current density for the integrated circuit is computed. Standard cells that have power rail current density below a predetermined threshold are replaced with a functionally equivalent standard cell that does not have M2 power rails, and the routing operation is performed again, until the design converges.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Lei Yuan, Jongwook Kye, Suresh Venkatesan
  • Patent number: 8782590
    Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 15, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Publication number: 20140189629
    Abstract: Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules.
    Type: Application
    Filed: March 22, 2013
    Publication date: July 3, 2014
    Applicant: Synopsys, Inc.
    Inventors: Yan Lin, Yi-Min Jiang, Phillip H. Tai, Lin Yuan
  • Patent number: 8762923
    Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: June 24, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Patent number: 8756556
    Abstract: Power flow in an electric power network is optimized by first decomposing an optimization problem into a set of disjoint parameterized optimization problems. The disjoint optimization problems are independent of each other, and the decomposition is based on dualized coupled constraints having corresponding multipliers. Each optimization problem is solved independently to obtain a corresponding solution, and a sensitivity of each solution to changes in the parameter. The parameters are updated using the corresponding solutions and the sensitivities, and iterated until reaching a convergence.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 17, 2014
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventor: Arvind U Raghunathan
  • Patent number: 8756552
    Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
  • Publication number: 20140149959
    Abstract: A method for making a matrix device including a matrix of photodetecting or photoemitting elements, the method including designing operations for: a) identifying, from at least one topology of the matrix device, one or more spurious conducting closed circuits; b) selecting at least one photodetecting or photoemitting element of the matrix device belonging to at least one of the spurious conducting closed circuits identified, the at least one element selected being made inactive.
    Type: Application
    Filed: April 12, 2012
    Publication date: May 29, 2014
    Applicants: ISORG, COMMISSARIAT A l "ENERGIE ATOMQUE ET AUX ENE ALT
    Inventors: Christophe Premont, Romain Gwoziecki
  • Patent number: 8726218
    Abstract: A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert L. Maziasz, Vladimir P. Rozenfeld, Iouri G. Smirnov, Alexander V. Zhuravlev
  • Patent number: 8709684
    Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang, Fu-Lung Hsueh
  • Patent number: 8701065
    Abstract: A method of designing an acoustic microwave filter comprises selecting a filter section based on frequency response requirements. The filter section includes an input, an output, and a plurality of circuit elements. The circuit elements have at least in-line acoustic resonators or in-shunt acoustic resonators. The method further comprises selecting a value for each circuit element, selecting a number of filter sections, and cascading the selected number of filter sections to create a cascaded filter circuit design, such that at least one pair of immediately adjacent filter sections are connected to each other via their inputs or their outputs. The method further comprises adding parasitic effects to the cascaded filter circuit design to create a pre-optimized filter circuit design, optimizing the pre-optimized filter circuit design to create a final filter circuit design, and constructing the acoustic microwave filter based on the final filter circuit design.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: April 15, 2014
    Assignee: Resonant LLC
    Inventors: Richard N. Silver, Kurt F. Raihn, Neal O. Fenzi, Robert B. Hammond
  • Publication number: 20140097012
    Abstract: A leadframe for semiconductor packages is provided. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. The leads includes a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad. The first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values. The plurality of leads are disconnected to each other.
    Type: Application
    Filed: December 9, 2013
    Publication date: April 10, 2014
    Applicant: MediaTek Inc.
    Inventor: Tao CHENG
  • Patent number: 8694945
    Abstract: The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hsing Wang, King-Ho Tam, Huang-Yu Chen
  • Publication number: 20140091367
    Abstract: An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output.
    Type: Application
    Filed: December 4, 2013
    Publication date: April 3, 2014
    Inventor: Michael Wagner
  • Publication number: 20140089884
    Abstract: A disclosed design support method includes: dividing an circuit element that is included in a circuit to be designed and is provided on a path that connects between memory circuits into plural circuit elements, based on information concerning circuit elements that can be divided into circuit elements; tracing the path from the memory circuits; and during the tracing, setting a new power supply voltage that is lowed by a predetermined voltage from a voltage, which was set immediately before, to a traced circuit element, which is provided on the path and satisfies a predetermined condition concerning a predetermined lower limit voltage of the traced circuit element.
    Type: Application
    Filed: July 11, 2013
    Publication date: March 27, 2014
    Inventor: Kiyoshi IKENISHI
  • Publication number: 20140068542
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Application
    Filed: February 26, 2013
    Publication date: March 6, 2014
    Applicants: SpringSoft USA, Inc, SpringSoft, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8667445
    Abstract: The invention discloses a power mesh management method utilized in an integrated IC. The integrated circuit includes a macro block including at least a macro block power supplying line growing along a first direction. The management method includes: defining a plurality of first power supplying lines located in a metal layer above the macro block, wherein each of the first supplying lines grows along the first direction; defining a plurality of second power supplying lines located in another metal layer above the macro block, wherein each of the second supplying lines grows along a second direction; defining a partial power supplying line from the plurality of first power supplying lines where the partial power supplying line overlaps the macro block power supplying line; and removing the partial power supplying line from the plurality of first power supplying lines.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 4, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Lin Chuang
  • Patent number: 8656335
    Abstract: A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: February 18, 2014
    Assignee: Atrenta, Inc.
    Inventors: Anshuman Nayak, Samantak Chakrabarti, Brijesh Agrawal, Nitin Bhardwaj