Detailed Patents (Class 716/130)
  • Patent number: 12131109
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Patent number: 12106030
    Abstract: A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang, Yi-Kan Cheng
  • Patent number: 11854882
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 26, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Patent number: 11790149
    Abstract: Embodiments include herein are directed towards a method for electronic circuit design is provided. Embodiments may include allowing, at a graphical user interface, a user to initiate a co-design mode associated with an electronic design. Embodiments may further include allowing, at the GUI, the user to select a shape to trace connectivity from. Embodiments may also include tracing the connectivity of the shape across one or more overlaps and identifying one or more pins associated with the connectivity. Embodiments may further include determining a correct pin from an instance associated with the connectivity and displaying the connectivity at the GUI.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: October 17, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Devendra Ramakant Deshpande, Arnold Jean Marie Gustave Ginetti, Fabien Campana, Harpreet Singh, Tapan Kumar Singh
  • Patent number: 11734487
    Abstract: A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 22, 2023
    Assignee: Siemens Industry Software Inc.
    Inventors: Mohamed Saleh Abouelyazid Saleh, James K. Falbo
  • Patent number: 11720729
    Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: August 8, 2023
    Assignee: Shenzhen Chipuller Chip Technology Co., LTD.
    Inventors: Danielle Morton, Rick Yan
  • Patent number: 11675954
    Abstract: A method of designing a device includes identifying a pin to be inserted into a first layer of the device, wherein the first layer has a plurality of first routing tracks, and each of the plurality of first routing tracks extend in a first direction. The method further includes identifying a blocking shape on a second layer different from the first layer, wherein the second layer has a plurality of second routing tracks, and each of the plurality of second routing tracks extends in a second direction different from the first direction. The method further includes determining at least one candidate location for the pin in the first layer based on the plurality of first routing tracks of the first layer. The method further includes setting a location for the pin in the first layer based on the determined at least one candidate location.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang
  • Patent number: 11658681
    Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 23, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Greg Sadowski, John Kalamatianos
  • Patent number: 11574109
    Abstract: A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes logic and the second level includes memory; and then obtaining a first placement of at least portion of the second level, where the first placement includes placement of a first memory array, where the Circuit includes a plurality of connections between the first level and the second level; and performing a second placement, where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array, where the performing a second placement includes using a placer executed by a computer, where the placer is a part of a Computer Aided Design tool, and where the logic includes a first logic circuit configured to read data from the first memory array.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: February 7, 2023
    Assignee: Monolithic 3D Inc
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 11514221
    Abstract: A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least a first and a second level, where the first level includes logic and the second level includes memory; then performing a first placement of the second level using a placer executed by a computer, the placer is a part of a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the first level and the second level; and performing a second placement of the first level based on the first placement, where memory includes a first memory array, the logic includes a first logic circuit configured so as to write data to first memory array. Performing the first placement includes placing the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: November 29, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 11487928
    Abstract: A method of designing 3D Integrated Circuits including: partitioning at least one design into at least two levels, a first and second level, where the first level includes logic, the second level includes memory; and then receiving a first placement of at least portion of the second level, where the first placement includes a placement of a first memory array, where the Circuit includes a plurality of connections between the first level and second level; performing a second placement of the first level based on the first placement, the performing a second placement includes using a placer computer executed, where the placer is a part of a Computer Aided Design tool, where the logic includes a first logic circuit configured to write data to the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: November 1, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 11449659
    Abstract: An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: September 20, 2022
    Assignee: Synopsys, Inc.
    Inventor: Thomas Cecil
  • Patent number: 11055469
    Abstract: An integrated circuit includes two buried power rails located beneath a first metal layer overlying the substrate, and two upper power rails in a second metal layer overlying the first metal layer. The two upper power rails are perpendicular to the two buried power rails. The integrated circuit includes a power pick-up cell having a functional circuit. The functional circuit includes a conductive segment beneath the first metal layer and a power pad in the first metal layer. The power pad is conductively connected to one of the upper power rails through a first via. The first power pad is conductively connected to the first conductive segment through a second via. The first conductive segment is conductively connected to one of the buried power rails through a third via.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10977414
    Abstract: System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sven Peyer, Christian Schulte
  • Patent number: 10860758
    Abstract: A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 8, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Cheng Liu, Shih-Chih Liu, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 10747936
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a two stage routing analysis, wherein a first stage analysis is an intra-row routing analysis and a second stage is an inter-row routing analysis. Embodiments may also include generating an optimized routing of the one or more nets and displaying the optimized routing at a graphical user interface.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 18, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hua Luo, Regis R. Colwell, Wangyang Zhang
  • Patent number: 10719653
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 21, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Chien-Hung Lu, Chun-Chen Chi, Tung-Chieh Chen, Kai-Chih Chi
  • Patent number: 10691865
    Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gazi M. Huda, Samuel O. Nakagawa
  • Patent number: 10566996
    Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 18, 2020
    Assignee: Advanced Mirco Devices, Inc.
    Inventors: Greg Sadowski, John Kalamatianos
  • Patent number: 10509887
    Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Ming-Huei Tsai, Shao-Huan Wang, Shu-Yu Chen, Wen-Hao Chen, Chun-Chen Chen
  • Patent number: 10509878
    Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Zhuo Li, Wen-Hao Liu
  • Patent number: 10503859
    Abstract: A computer-implemented method of generating a layout of a circuit block of an integrated circuit comprises: receiving input data defining a logical operation of the circuit block; accessing a cell library providing a plurality of candidate cells; determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer; in which the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cell
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 10, 2019
    Assignee: ARM Limited
    Inventor: Jean-Luc Pelloie
  • Patent number: 10372864
    Abstract: A method includes receiving a routing grid that includes nets each net having a bounding box maximum dimension, a net length and a number of pins associated with each of the nets, generating a list of the nets, the list of the nets sorted in order by the bounding box maximum dimension, the net length, and the number of pins associated with each of the nets, calculating a sum of the number of pins, calculating a sum of the length of the nets, identifying a net for which a difference of the sum of the number of pins and the sum of the length of the nets is a maximum value, determining the bounding box maximum of the identified net, calculating a tile size as a function of the bounding box maximum, performing a global routing process using the calculated tile size to generate a global routing design.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Karsten Muuss
  • Patent number: 10289795
    Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Charles Jay Alpert, Zhuo Li
  • Patent number: 10268795
    Abstract: A method for timing optimization is disclosed. The method includes obtaining information on detour locations of a chip by performing a routing operation, establishing, through machine learning, a model that describes a relationship between an image map and the detour locations, generating predicted detour locations based on the model and the image map, determining the probability of detouring in a region of the predicted detour locations, determining a predicted detour net for a path in a region having a high probability of detour, and determining sensitivity of the path.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Lin Chuang, Chih-Tien Chang, Kuan-Hua Su, Szu-Ju Huang
  • Patent number: 10198548
    Abstract: Yield excursions in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. Techniques are disclosed herein for efficiently identifying the root-cause of a manufacturing yield excursion by analyzing fail data collected from the production test environment. In particular, statistical hypothesis testing is used in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the cause of the yield excursion.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 5, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Manish Sharma, Robert B. Benware
  • Patent number: 9990456
    Abstract: The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part, the generated change.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 5, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Brett Allen Neal, Richard Allen Woodward, Jr., Edmund J. Hickey
  • Patent number: 9953922
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 24, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9818221
    Abstract: At least one processor may organize a plurality of primitives of a scene in a hierarchical data structure, wherein a plurality of bounding volumes are associated with a plurality of nodes of the hierarchical data structure. The at least one processor may rasterize a representation of each of the plurality of bounding volumes to an off-screen render target in the memory. The at least one processor may determine, based at least in part on a pixel in the off-screen render target that maps to a ray in the scene, a non-root node of the hierarchical data structure associated with the pixel as a start node to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine whether the ray in the scene intersects one of the plurality of primitives.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Juraj Obert
  • Patent number: 9715568
    Abstract: The wiring length measurement apparatus includes a distance calculation unit, by using a plurality of coordinates of bending points and a wiring width of CAD data of a high-density wiring including a meander wiring, seeking each endpoint that exists on an edge in a wiring width direction and is a flexion point of each inner circuit side, and calculating distances between each adjacent endpoint and a measurement unit measuring a wiring length of the high-density wiring by calculating a sum of the distances between each endpoint calculated by the distance calculation unit.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 25, 2017
    Assignee: LIQUID DESIGN SYSTEMS INC.
    Inventors: Shinichi Maeda, Katsuhiko Iwase
  • Patent number: 9564394
    Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires compared to the signal transition in conventional interconnect circuitry. At the same time, sub-optimal wire stitching in a routing tile that connects a wire that ends in the next routing tile to a wire that starts in the routing tile, whereby the two wires overlap each other may enable beneficial crosstalk, which may further improve signal transition time.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: February 7, 2017
    Assignee: Altera Corporation
    Inventors: Aron Joseph Roth, Jeffrey Christopher Chromczak, Michael Chan
  • Patent number: 9552451
    Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha
  • Patent number: 9542084
    Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design. The method may further include receiving an indication that a cursor is hovering over an overlap associated with the electronic design and in response to receiving the indication, computing one or more via parameters, based upon, at least in part, a topology associated with the overlap. The method may also include displaying, at a graphical user interface, a potential via and allowing, at the graphical user interface, adjustments to the one or more via parameters.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Stephane Colancon, Gerard Tarroux, Mark Nitters, Fabien Campana
  • Patent number: 9455223
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: September 27, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9185808
    Abstract: The invention discloses a printed circuit board compensation processing method for fabricating a BGA despite a small distance between a line and a pad of the BGA. The method includes compensating a pad and/or a line under a predetermined condition, and removing a portion of the pad facing the line by a second predetermined width when the shortest distance between the compensated line and pad is smaller than a first predetermined distance. The invention further discloses a device for performing the method and a PCB fabricated using the method.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 10, 2015
    Assignees: Peking University Founder Group Co., Ltd., Zhuhai Founder Tech. Hi-Density Electronic Co., Ltd., Zhuhai Founder PCB Development Co., Ltd.
    Inventors: Lanyuan Chen, Haode Li
  • Patent number: 9177093
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 3, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Patent number: 9122834
    Abstract: A system, method, and computer program product for using continuous parameter value updates to rapidly evaluate parameterized cells in a design tool. Embodiments display parameters and corresponding parameter values of parameterized cells in a circuit design in a GUI, adjust parameter values according to user input, evaluate the parameterized cell, and present results of the evaluating in the GUI during the displaying. Parameters influence circuit layout, circuit schematics, or simulation settings. Parameter values include current, minimum, maximum, and increment values. Parameterized cells may be individual cell instances, submaster cells, or master cells. Embodiments integrate validation tools and detect design rule check violations, assertion violations, invalid parameter values, and evaluation errors, and responsively generate user error alerts and selectively disallow further adjusting. Embodiments generate test circuits, each using a parameter value from a permutation of the adjusted parameter values.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 1, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Serena Chiang Caluya, Li-Chien Ting
  • Patent number: 9098664
    Abstract: A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a channel implementation area, corresponding to the substrate, for each of a plurality of signal channels, based on the channel priority assigned to the signal channel and based on the block implementation areas. The device may generate an integrated circuit design comprising the channel implementation area allocated for each of the plurality of signal channels.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: August 4, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Vivek Trivedi, Khalil Siddiqui
  • Patent number: 9082624
    Abstract: A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: David H. Allen, Douglas M. Dewanz, David P. Paulsen, John E. Sheets, II
  • Patent number: 9075932
    Abstract: Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punches for the muting layer, identify an area probe from the spacetiles, and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punches to form spacetiles for the routing layers, determine a via spacetile layer, identify spacetiles as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two muting layers. One of the two routing layers may be a tracked muting layer, and the other may be a trackless routing layer. The tracked muting may be gridded or gridless.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 7, 2015
    Assignee: Candence Design Systems, Inc.
    Inventor: Jeffrey S. Salowe
  • Patent number: 9038013
    Abstract: Methods and apparatuses for circuit design are described. In one embodiment, the method comprises determining a distribution of nets of a circuit, the distribution of the nets comprising numbers of blocks that each of the nets has in each of a plurality of partitions of the circuit in a partitioning solution, moving a first block of the circuit from a source partition to a destination partition to modify the partitioning solution, and updating the distribution of the nets after the moving.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: May 19, 2015
    Assignee: Synopsys, Inc.
    Inventors: Awartika Pandey, Drazen Borkovic, Kenneth S. McElvain
  • Patent number: 9032349
    Abstract: One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 12, 2015
    Assignee: Wistron Corp.
    Inventors: Wen-Hsiang Lee, Wen-Jui Kuo, Feng-Ling Lin, Hsiao Ming Wang, Lung-Ming Chan, Li-Ting Hung
  • Patent number: 9026975
    Abstract: A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-joong Song, Pil-un Ko, Gyu-hong Kim, Jong-hoon Jung
  • Patent number: 9026976
    Abstract: In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 9021407
    Abstract: A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: David H. Allen, Douglas M. Dewanz, David P. Paulsen, John E. Sheets, II
  • Patent number: 9015644
    Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventors: Wen-Hsiang Lee, Wen-Jui Kuo, Feng-Ling Lin, Hsiao Ming Wang, Lung-Ming Chan, Li-Ting Hung
  • Patent number: 9015645
    Abstract: Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration analysis on the design. In one implementation, an intelligent connectivity may be applied to the hierarchical extraction to achieve an approximate location of the connection points between the blocks of the design. In one example, the intelligent connectivity technique may utilize a coordinate grid related to the design to approximate the connection points between the blocks of the design.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 21, 2015
    Assignee: Oracle International Corporation
    Inventors: Vamshi Pampati, Tony Hoang, Mini Nanua
  • Publication number: 20150106778
    Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 16, 2015
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 9009645
    Abstract: Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Synopsys, Inc.
    Inventors: Aiqun Cao, Sanjay Dhar, Lin Yuan
  • Patent number: 9009646
    Abstract: A method for routing a design may comprise receiving a design for implementing in a target device, wherein the design includes an input/output (I/O) signal of a functional block, and wherein the functional block is assigned to a physical component of the target device; based on the design and on a routing resource graph representing the target device, calculating a route including the physical component and a physical pin of the target device; and assigning the physical pin of the target device to the I/O signal based on the calculated route.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Haneef Mohammed, Kyle Kearney