For Timing Patents (Class 716/134)
  • Patent number: 10936783
    Abstract: Aspects of the present disclosure address improved systems and methods for runtime efficient circuit placement location selection as described herein. An example embodiment includes identifying, for each route of the one or more routes that interconnect the terminals of a circuit design with the one or more pins of a first circuit element, a corresponding set of movement positions along said each route to generate a set of movement configurations for the first circuit element. The set of movement configurations is analyzed to generate a plurality of location clusters from the set of movement configurations, and for each location cluster of the plurality of location clusters, identifying one or more selected movement configurations within said each cluster. The one or more selected movement configurations for said each cluster to select an updated movement configuration.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Mark Chapman, Zhuo Li
  • Patent number: 10902167
    Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chaitanya Ravindra Peddawad, Kerim Kalafala, Alexander Joel Suess, Hemlata Gupta, Gregory Schaeffer
  • Patent number: 10826308
    Abstract: A charge/discharge control device and a battery apparatus respectively include a discharging-overcurrent-detection circuit which monitors a discharging overcurrent according to a discharging-overcurrent-reference voltage based on the voltage of a discharging-overcurrent-detection terminal, and the voltage of a discharge-reference FET having a drain and a gate connected to those of a charge control FET.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 3, 2020
    Assignee: ABLIC INC.
    Inventor: Fumihiko Maetani
  • Patent number: 10552055
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • Patent number: 10417365
    Abstract: An example circuit includes: a first clock gating circuit coupled between a first latch and a second latch and configured to provide a first gated clock signal based at least in part on an input clock signal. The first latch is configured to be activated in response to the first gated clock signal being at a first logic level to pass a data input. The second latch is configured to be activated in response to the input clock signal being at a second logic level to pass a first selection signal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 17, 2019
    Assignee: Ansys, Inc.
    Inventors: Ajay Singh Bisht, Allen Baker
  • Patent number: 10107855
    Abstract: Apparatuses, systems, and methods for detecting changes to an IC are disclosed. In an example implementation, an apparatus includes an electromagnetic (EM) sensor. A high-resolution analog-to-digital converter (ADC) is configured to quantize a segment of the EM signal of an IC measured by the EM sensor. The quantized segment of the EM signal is unique to process-voltage-temperature (PVT) characteristics exhibited by the IC. The apparatus also includes a processing circuit configured to prompt the high-resolution ADC, via a control signal, to produce the quantized segment of the EM signal. The processing circuit determines a first signature from the quantized segment and retrieves a baseline signature corresponding to the IC from a data storage circuit. In response to the first signature being different from the baseline signature, the processing circuit indicates that a change to the IC is detected.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 23, 2018
    Assignee: XILINX, INC.
    Inventors: John D. Corbett, Steven E. McNeil
  • Patent number: 10083267
    Abstract: An example circuit includes: a first clock gating circuit coupled between a first latch and a second latch and configured to provide a first gated clock signal based at least in part on an input clock signal. The first latch is configured to be activated in response to the first gated clock signal being at a first logic level to pass a data input. The second latch is configured to be activated in response to the input clock signal being at a second logic level to pass a first selection signal.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: September 25, 2018
    Assignee: Ansys, Inc.
    Inventors: Ajay Singh Bisht, Allen Baker
  • Patent number: 9853866
    Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
  • Patent number: 9576095
    Abstract: Methods for partial reconfiguration compatibility detection in an integrated circuit device are disclosed. A disclosed method includes storing a unique identifier that identifies a partial reconfiguration region of the integrated circuit device in a storage circuit. A control circuit may receive an input partial reconfiguration data that activates the operations of the partial reconfiguration region. The method further includes comparing the input partial reconfiguration data to the stored unique identifier prior to activating the operations of the partial reconfiguration region of the integrated circuit device. The input partial reconfiguration data may contain an associated identifier that is derived from the unique identifier during a design compilation operation of the integrated circuit device.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 21, 2017
    Assignee: Altera Corporation
    Inventors: Yin Chong Hew, Paul Mark Leventis
  • Patent number: 9513658
    Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: December 6, 2016
    Assignee: Apple Inc.
    Inventors: Harsha Krishnamurthy, Muthukumaravelu Velayoudame
  • Patent number: 9489482
    Abstract: Disclosed is a method for improving integrated circuit (IC) chip reliability. In the method, IC chips, which are manufactured according to a given IC chip design, are sorted into multiple different groups associated with different process windows in the process distribution for the design. Different operating voltages are assigned to the different groups, respectively, in order to optimize overall reliability of IC chips across the process distribution. That is, each group is associated with a specific process window, comprises a specific portion of the IC chips and is assigned a group-specific operating voltage that minimizes the fail rate of the specific portion of the IC chips and that, thereby optimizes the reliability of the specific portion of the IC chips. The group-specific operating voltage will be within minimum and maximum voltages associated with either the process distribution or the specific process window (e.g., following power-optimized selective voltage binning).
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeanne P. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
  • Patent number: 9171125
    Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Igor Arsovski, Jeanne P. Bickford, Mark W. Kuemerle
  • Publication number: 20150135154
    Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).
    Type: Application
    Filed: January 18, 2015
    Publication date: May 14, 2015
    Inventor: Ryan Fung
  • Patent number: 9032349
    Abstract: One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 12, 2015
    Assignee: Wistron Corp.
    Inventors: Wen-Hsiang Lee, Wen-Jui Kuo, Feng-Ling Lin, Hsiao Ming Wang, Lung-Ming Chan, Li-Ting Hung
  • Patent number: 9026966
    Abstract: The present patent document relates to a method and apparatus for more efficiently simulating a circuit design (DUT), making use of a hardware functional verification device such as a processor-based emulator. A set of linked databases are compiled for the DUT, one for hardware emulation (without timing information for the DUT) and one for software simulation (including timing information) that remain synchronized during runtime. The compiled design is run in a hardware emulator during an initialization/configuration phase and the state saved. The state is then swapped to a software simulator where timing information, such as SDF timing, may be honored during the second part of the run and the user's test bench stimuli applied to the design.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Naresh Ramachandran, G. B. Ashok, Ping-Sheng Tseng
  • Patent number: 9026964
    Abstract: A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 5, 2015
    Assignee: University of North Texas
    Inventors: Saraju P. Mohanty, Elias Kougianos, Geng Zheng
  • Patent number: 9026978
    Abstract: A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a first register occurrence. A reduced netlist spans the regional circuitry and the modeled external circuitry. Embodiments optimize the reduced netlist under design constraints applicable to the full circuit design. Changes to the original circuit design made by the optimization are tangibly saved as engineering change orders. The optimization process may be applied to other regions, including via parallel execution by multiple processors.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dongzi Liu, Yi Qian, Wanshuan Liu, Pinhong Chen, WenHsing Tsai, Yanhui Wang
  • Publication number: 20150121329
    Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Min FU, Yung-Fong LU, Chung-Hsing WANG
  • Patent number: 9015644
    Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventors: Wen-Hsiang Lee, Wen-Jui Kuo, Feng-Ling Lin, Hsiao Ming Wang, Lung-Ming Chan, Li-Ting Hung
  • Patent number: 9009645
    Abstract: Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Synopsys, Inc.
    Inventors: Aiqun Cao, Sanjay Dhar, Lin Yuan
  • Publication number: 20150100936
    Abstract: In some embodiments, in a method, a physical netlist of a placed IC chip design is received. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained. Weights to the register pairs are assigned based on the timing criticalities of the register pairs. Candidate registers that are in physical vicinity of a first cluster are identified. If a first candidate register in the candidate registers of the first cluster is in a second cluster, selecting the first candidate register as the first register to be added to the first cluster if sum of weights of other candidate registers in register pairs across the boundary of the first cluster and the first candidate register in one or more register pairs across a boundary of the second cluster is optimized.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 9, 2015
    Inventor: YI-LIN CHUANG
  • Patent number: 9003340
    Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 7, 2015
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 9003352
    Abstract: A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires the number of stages of input FFs of FF reception. A latency re-adjusting part obtains an optimum delay based on the above-mentioned necessary delay and input delay. A former-stage module analyzing part detects, based on the above-mentioned synthetic log or HDL, a state having a minimum total number of FFs. An FF insertion optimizing synthesis part subjects an entire circuit to high level synthesis again based on the above-mentioned optimum delay and an FF inserting position obtained based on the state having the minimum number of FFs, to thereby obtain optimized HDL.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryo Yamamoto, Noriyuki Minegishi
  • Patent number: 8997031
    Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shaojie Xu, Yukit Tang, Pao-Po Hou, Derek C. Tao, Annie-Li-Keow Lum
  • Patent number: 8990748
    Abstract: In one approach for improving timing in an electronic circuit design having a finite state machine (FSM), control bit logic is generated based on next state logic of the FSM that generates current state bits of the FSM. The control bit logic and a control state bit are added to operate in parallel with the next state logic and the current state bit registers, and the output signal from the control bit register replaces selected logic in logic downstream from the FSM and current state bit registers. If a worst case delay is improved with the design having the control bit logic and control state bit, the modified circuit design is saved for evaluating other possible timing improvements. Otherwise, the modification is discarded.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: March 24, 2015
    Assignee: Xilinx, Inc.
    Inventor: Reed P. Tidwell
  • Patent number: 8990750
    Abstract: Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 24, 2015
    Assignee: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Patent number: 8984469
    Abstract: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Atrenta, Inc.
    Inventors: Solaiman Rahim, Mohammad H. Movahed-Ezazi, Siddharth Guha, Vaibhav Jain
  • Patent number: 8984470
    Abstract: One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: March 17, 2015
    Assignee: Synopsys, Inc.
    Inventors: Abhijit Chakanakar, Tong Gao
  • Patent number: 8977999
    Abstract: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: March 10, 2015
    Assignee: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Patent number: 8977998
    Abstract: A method for using computing equipment to perform timing analysis on an integrated circuit design includes identifying a timing arc of the integrated circuit design. The timing arc may be a clock path or a data path in the integrated circuit design. A probability of the timing arc may be obtained and an aging effect for the timing arc may be calculated. The aging effect of the timing arc is calculated based on the probability. The timing arc may include maximum and minimum delays that are adjusted based at least partly on the calculated aging effect on the timing arc.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 10, 2015
    Assignee: Altera Corporation
    Inventors: Navid Azizi, Gordon Raymond Chiu, Ian Carlos Kuon, John Curtis Van Dyken
  • Patent number: 8977993
    Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Synopsys, Inc.
    Inventors: Qian-Ying Tang, Qiang Chen, Sridhar Tirumala
  • Patent number: 8977995
    Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: March 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sumit Arora, Oleg Levitsky, Amit Kumar, Sushobhit Singh
  • Patent number: 8972919
    Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hao Chen, Yi-Kan Cheng
  • Patent number: 8972920
    Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: March 3, 2015
    Assignee: Xilinx, Inc.
    Inventors: Grigor S. Gasparyan, Dinesh D. Gaitonde, Yau-Tsun S. Li
  • Patent number: 8972915
    Abstract: Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty™ file format, before being compatible with commercial STA tools.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: March 3, 2015
    Assignee: University of Southern California
    Inventors: Mallika Prakash, Peter A. Beerel
  • Patent number: 8966419
    Abstract: Systems and methods are disclosed for testing a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack, particularly where the defect is located in the inter-die data transfer path. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • Patent number: 8963620
    Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeanne P. S. Bickford, Eric A. Foreman, David J. Hathaway, Mark W. Kuemerle, Susan K. Lichtensteiger
  • Patent number: 8966432
    Abstract: Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Xilinx, Inc.
    Inventor: Matthew H. Klein
  • Patent number: 8966431
    Abstract: Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeanne P. Bickford, Howard B. Druckerman, Erik L. Hedberg, Joseph J. Oler, Jr.
  • Patent number: 8954915
    Abstract: Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yiu-Hing Chan, Mark D. Mayo, Shyam Ramji, Paul G. Villarrubia
  • Publication number: 20150040094
    Abstract: Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes by removing all nodes in the first set from the nodes that represent the IC components. The method identifies a set of edges that connect two nodes in the second set without encompassing a third node in the second set. The method assigns an event time to each node in the second set. The method assigns a cost function based on the event times of the nodes connected by each edge and the number of nodes in the first set encompassed by each edge. The method optimizes the cost function and places the components based on the cost function optimization.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 5, 2015
    Inventors: Andrew Caldwell, Steven Teig
  • Publication number: 20150040093
    Abstract: Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Patent number: 8949768
    Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 3, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Puneet Gupta, Andrew B. Kahng
  • Patent number: 8949765
    Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
  • Patent number: 8949764
    Abstract: Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Patent number: 8941430
    Abstract: One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Robert Palmer, John W. Poulton, Thomas Hastings Greer, III, William James Dally
  • Patent number: 8938702
    Abstract: A mechanism is provided in a data processing system for timing-driven routing for noise reduction in integrated circuit design. Responsive to performing timing driving routing on an integrated circuit design, the mechanism identifies a set of noise-critical nets in the integrated circuit design. The mechanism performs timing driven routing on the integrated circuit design with noise constraints based on the set of noise-critical nets.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Andre Hogan, Andrew D. Huber, Zhuo Li, Karsten Muuss, Sven Peyer, Christian Schulte, Gustavo E. Tellez
  • Patent number: 8935642
    Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
    Type: Grant
    Filed: December 15, 2012
    Date of Patent: January 13, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Bhardwaj, Oleg Levitsky, Dinesh Gupta
  • Patent number: 8935651
    Abstract: In one embodiment of the invention, a method of logic synthesis is disclosed. The method includes generating a plurality of design architecture alternatives for circuit logic of a data path cluster; saving the plurality of design architecture alternatives; and evaluating the plurality of design architecture alternatives in response to design constraints to select a preferred design architecture.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 13, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsuwei Ku, Samir Agrawal, Jean-Charles Giomi
  • Patent number: 8930870
    Abstract: Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lukas Daellenbach, Elmar Gaugler, Ralf Richter