Abstract: Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes.

Abstract: The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.

Abstract: A method includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method for designing a power distribution network (PDN) for a system implementing a target device includes computing a target PDN impedance value for the PDN. For each switching frequency of the target device where an effective PDN impedance value for the PDN is greater than the target PDN impedance value, one or more decoupling capacitors for one or more capacitor types are identified to add to the PDN to drive the effective PDN impedance value below the target PDN value. A selection of decoupling capacitors identified is refined to reduce one or more of a cost of the PDN and space required for implementing the PDN.

Abstract: A system, method and computer program product are provided for reducing a deactivation function utilizing an optimal reduction. In use, a deactivation function is identified. Additionally, reductions for the deactivation function are calculated. Further, an optimal reduction of the calculated reductions is determined. Moreover, the deactivation function is reduced, utilizing the optimal reduction.

Abstract: A power domain is automatically generated. A computer performs a function simulation process 9 for evaluating whether or not a designed circuit satisfies a specification, and a clustering process 10 which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A level shifter physical verification system identifies missing level shifters in a multi-voltage domain integrated circuit design. The system analyzes a physical layout design data file for design to identify domains and signals that cross domains, and connected nets of devices within the IC design having one or more missing level shifters.

Abstract: Various embodiments of methods and systems for heuristic determination and thermal analysis of component placement on a printed circuit board (“PCB”) for use in a portable computing device (“PCD”) are disclosed. It is an advantage of embodiments that thermal energy generating components, such as processors, may be heuristically selected and arranged on a selected PCB according to varying layouts and combinations and then evaluated for thermal dissipation efficiency under an assortment of use case scenarios. In this way, users of the system and method may quickly narrow down commercially feasible component layouts, identify the most efficient layouts and then heuristically modify the layouts to develop an optimal arrangement.

Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes.

Abstract: Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving a the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell.

Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.

Abstract: A power integrity analyzer according to an exemplary aspect of the invention includes a parameter inputting unit that inputs parameters to a power-supply current waveform which indicates a variation of a power-supply current value on a time axis of an element, a conversion unit that converts the power-supply current waveform which indicates a variation on the time axis determined by the parameter to a power-supply current spectrum which indicates a variation of the power-supply current value on a frequency axis, an allowable value information storage unit that stores an allowable power-supply voltage fluctuation value of the element, and an impedance calculating unit that calculates a target impedance spectrum on the device indicating the variation of impedance value on the frequency axis based on the power-supply current spectrum and the allowable power-supply voltage fluctuation value.

Abstract: Systems and techniques for optimizing a circuit design are described. When a selected gate is transformed during optimization, it causes a slack value at a pin of the transformed gate to change. The change in the slack value, called the delta-slack, is then propagated through a transitive fanin cone and a transitive fanout cone of the transformed gate to compute the new slack values at all the affected pins of the design. Some embodiments update slack values without propagating arrival and required times, and also without repeatedly evaluating timing arcs to compute gate delays. The updated slack values can be used to compute timing metrics. The timing metrics can be used to decide whether or not to commit the gate transformation to the circuit design.

Abstract: Design variable value sets for predetermined design variables are generated, and for each of the predetermined design variables, parameter value sets for predetermined parameters are generated. For each combination of them, circuit simulation is carried out to obtain a performance item value set for predetermined performance items. Then, for each of the design variable value sets, and further for each of the parameter value sets generated for a corresponding design variable value set, combinations of the design variable value set and parameter value set are identified, for which performance item values for all of the predetermined performance items are not less than performance item values obtained for a combination of the corresponding design variable value set and a corresponding parameter value set, and a yield rate is calculated by dividing the number of identified combinations by the number of parameter value sets generated for the corresponding design variable value set.

Abstract: Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow.

Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Abstract: It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply voltage and a rise in ground voltage. In the functional circuit of the semiconductor device and the display device, a power supply wiring and a ground wiring are formed in a comb-like arrangement, and the tips thereof are electrically connected with a first wiring, a second wiring, and a contact between the first wiring and the second wiring, thereby forming in a grid-like arrangement. The drop in power supply voltage and the rise in ground voltage can be decreased and the arrangement area can be decreased in the grid-like arrangement.

Abstract: In a particular embodiment, a method of generating an advanced gating cell clock tree includes determining a timing margin for a path between a clock gating cell and a digital data storage element such as a latch or flip flop. The circuit contains a clock source and when the timing margin for the path meets a predetermined threshold, the clock gating cell is automatically moved closer to the clock source. In a particular embodiment, the timing margin is automatically determined. A clock tree synthesis is performed to insert one or more buffers into the path and create an advanced gating cell clock tree.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Abstract: Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.

Abstract: A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results.

Abstract: Techniques are generally described for non-invasive, post-silicon characterization of—leakage power for devices of an integrated circuit (IC). A system of sparse leakage power equations may be developed for the devices (e.g. gates) within the IC to be solved using compressive sensing (CS) techniques. Input Vectors (IV) may be applied at input terminal of the IC, and power of the IC may be measured. The measurements may be used in conjunction with the set of sparse equations to determine leakage power values for individual devices, not directly accessible. Pre-processing and post-processing techniques may be employed to make the system of equations more sparse and further improve the efficiency of applying CS techniques to solve the equations. Example processing may include variable splitting, device grouping, IV and equation selection, measurement under elevated IC temperature, and bootstrapping. Other aspects may be disclosed and claimed.

Abstract: In an embodiment, the design flow is modified to avoid the flattening process but still accurately annotate the transistors with stress parameters. The location-based stress parameters may be generated, but may not be provided to the LVS tool. Instead, a hierarchical LVS process may be performed, black-boxing lower level blocks that already have stress parameter assignments, preserving hierarchy, etc. The output database from LVS thus includes a cross reference between layout devices and schematic devices, as well as locations of the schematic devices. The database may then be queried for the transistors in the non-flattened design, and the stress parameters may be assigned to the transistors based on the location-based stress parameters. In this fashion the stress parameters may be assigned to the desired transistors, permitting annotation of these parameters into the schematics, without flattening the design and doing unnecessary work on blocks to be skipped.

Abstract: Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

Abstract: One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.

Abstract: A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell.

Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure.

Abstract: A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values.

Abstract: An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.

Abstract: A method and system for reducing power consumption of an electronic circuit design using an EDA tool includes generating a look-up table (LUT) that stores a mapping between a type, a predetermined optimum power input transition time, and at least one characteristic corresponding to each digital logic element present in a cell library of the EDA tool. An input transition time of a first digital logic element is determined. Then, the first logic element is replaced with a second logic element if the input transition time and the predetermined optimum power input transition time of the first logic element are not equal. The second logic element may be replaced with a third logic element if a timing delay of the second logic element is greater than a timing delay of the first logic element.

Abstract: A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization.

Abstract: A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

Abstract: An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Abstract: A power supply circuit design system according to an exemplary aspect of the invention includes: a power supply voltage fluctuation deriving means for deriving a power supply voltage fluctuation characteristic as a voltage fluctuation characteristic in a semiconductor integrated circuit on the basis of design information about a power supply circuit for connecting the semiconductor integrated circuit and other components mounted on a substrate; a determination reference database including a power supply voltage fluctuation condition as a condition for which the power supply voltage fluctuation characteristic is allowed in the power supply circuit, and a change indicator for at least one of a circuit structure and operation of the semiconductor integrated circuit; a power supply voltage fluctuation determination means for comparing the power supply voltage fluctuation characteristic and the power supply voltage fluctuation condition, and determining whether the power supply voltage fluctuation characteristic s

Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.

Abstract: A computer software implemented method of automatically determining adequacy of an integrated circuit electrical power distribution and signal protection schemes, based on netlist data, which does not rely on other a-priori data. The method determines which nets are power supply nets, their connectivity to different types of power supplies. The method automatically traverses the nested block structure of the circuit, ascending and descending in block hierarchy as needed, and automatically determines (often based on an inspection of the power needs of the individual block devices) the type of power supply needed to power that block, power supply adequacy, and adequate protection of signal interfaces to other blocks. The method can present the analysis in a high level report, such as a graphical map, that can make root cause sources of power and power related signal interface problems immediately evident, and which suppresses most irrelevant details.

Abstract: In one embodiment, a configurable power switch cell methodology may include designing multiple power switch cells which may be assembled to form a set of power switches such as a power switch segment. The power switch cells may all be designed to occupy the same amount of integrated circuit area, in an embodiment. Accordingly, one cell may be readily replaced by another, even late in the design process, without disturbing the placement of surrounding circuitry. In an embodiment, the power switch cells may include the interconnect layers that connect between cells, and abutting the power switch cells may automatically connect the interconnect between cells. Accordingly, swapping one power switch cell for another may be accomplished by placing the cell. No routing work may be required.

Abstract: In one embodiment, a method is provided for analyzing a circuit design. For each sub-circuit of a plurality of sub-circuits specified in the circuit design, a logic level probability is determined for each output of the sub-circuit. The logic level probability indicates the probability that an output of the sub-circuit will have a first value in response to possible values of inputs to the sub-circuit. Each logic level probability is converted to a switching probability that indicates a probability that a switching event will occur at the respective output of the sub-circuit within a time period. The switching probability is stored in a memory.