Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract: A method for efficiently producing a design layout that includes several fills between and around nets of the design layout is described. The method of some embodiments first places a set of fills in the design layout. The method then performs a timing analysis on the design layout to find out the impact of the fills on the timing of the nets. The method identifies a region of the design layout in which to trim a set of fills in order to fix any timing violations of the nets. The method then trims the set of fills in the identified region. In some embodiments, the method employs different trimming strategies for trimming fills around different nets based on the characteristics of the nets.

Abstract: Methods and systems for determining timing constraint analysis of an integrated circuit (IC) may include defining a sequence of sample points for timing constraint analysis of an n×n matrix, each sample point corresponding to a timing arc of the IC that includes data and reference slews; initially simulating extreme sample points of the matrix, according to the sequence, by substituting timing constraints from liberty files of the IC type for time values of the data slews and conducting a binary search for optimized timing constraints; and interpolating other sample points, according to the sequence, each of the other sample points having a starting bisection point that results from linear interpolation of the timing constraint analysis from adjoining sample points, which were simulated.

Abstract: A dual-box location-based on-chip variation (DBLOCV) can be used in STA to significantly reduce pessimism. The DBLOCV analysis includes forming a backward bounding box and a forward bounding box for a cell of the design. A first intermediate maximum distance from the cell to corners of the backward bounding box can be calculated using the coordinates. A second intermediate maximum distance from the cell to corners of the forward bounding box can be calculated using the coordinates. A derate value can be determined from the derate table using the maximum distance of the first and second intermediate maximum distances. STA can be performed using the derate value. At least one timing report can be generated based on the STA.

Abstract: An integrated circuit having at least one array of circuit cells, each circuit cell having a plurality of transistors each performing a specified function, the transistors having predefined performance parameter margins for the specified function, the circuit cells designed by providing at least one operating condition for the circuit cell; providing a value of sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, which is defined by a semiconductor process that results in transistors having such transistor characteristics; providing an array of instances based upon the value of the sigma and using a design of experiments factorial calculation; providing a metric of interest by which to deter-nine pass/fail instances; extracting individual pass/fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.

Abstract: Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.

Abstract: A netlist generating apparatus including a memory configured to store logic design data and a processor configured to execute an operation. The operation including selecting paths with which names of instances after logic synthesis match names of modules before being uniquified during the logic synthesis by referring to violation data for paths of the instances and a correspondence table in which the modules are associated with paths of the instances, extracting a path with worst violation data from selected paths by comparing violation data of the selected paths, and adjusting a timing of the extracted path with the worst violation data and generating a netlist.

Abstract: Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode.

Abstract: A timing error removing method includes selecting a logic-level correction location and a first buffer to be inserted at the logic-level correction location, wherein the logic-level correction location and the first buffer are able to remove a timing error in a semiconductor integrated circuit to be designed; and searching for a vacant area in the semiconductor integrated circuit where the first buffer can be placed for the logic-level correction location, and if the vacant area is not found, further searching for a combination of a plurality of buffers smaller than the first buffer, the combination of the plurality of buffers being able to be placed in the semiconductor integrated circuit and being able to replace the first buffer in terms of a delay obtained as if the first buffer is inserted.

Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

Abstract: One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields.

Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.

Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing metric for a candidate sequential cell are compared with the corresponding non-timing metric and timing metric for the current best sequential cell. If a candidate sequential cell improves the timing metric, or maintains the timing metric and has better non-timing metric(s), then the candidate sequential cell is stored as the current best sequential cell. Once the process completes, the current best sequential cell is the optimized cell size for the sequential cell.

Abstract: An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals.

Abstract: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.

Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

Abstract: An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.

Abstract: A functional timing analysis method, executed in a computing device, comprises: step A: obtaining a circuit; step B: selecting a target delay time from a delay time set for a node in the circuit for verifying whether the target delay time is attainable by some input assignment; step C: generating a timed characteristic function associated with the selected target delay time for the node recursively from the timed characteristic functions associated with the corresponding delay times for its fanin nodes is generated as a target formula; step D: recursively translating the timed characteristic function into timed characteristic function clauses of the target formula by using an implication operator; step E: checking whether the target formula is satisfied by using a Boolean satisfiability solver; and step F: if the target formula is satisfied, the selected target delay time is attainable by some input assignment to the circuit.

Abstract: A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.

Abstract: A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Abstract: A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

Abstract: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit.

Abstract: Embodiments include a method for providing a local maximum operating voltage on an integrated circuit. The method includes determining a gate-to-contact reliability for each of the plurality of regions and calculating a local maximum voltage for each of the plurality of regions based on the gate-to-contact reliability. Based on a determination that the local maximum voltage in one of the plurality of regions is greater than a maximum voltage, the method includes setting the local maximum operating voltage to the maximum voltage. Based on a determination that the local maximum voltage in one of the plurality of regions is less than the maximum voltage, the method includes setting the local maximum operating voltage to the local maximum voltage.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of various hosts in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example implementations selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, and using probabilistic functions to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.

Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.

Abstract: A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.

Abstract: If there are a plurality of activation paths on which a signal propagates during a delay test, multiple-input cells receiving two or more activation paths are extracted by an extraction unit. For the extracted multiple-input cells, whether there is a possibility of occurrence of a multiple-input switching in a multiple-input cell is determined by a determination unit, based on an input timing to each signal multiple-input cell in the two or more activation paths. Then, an occurrence situation of a multiple-input switching is analyzed as one delay cause by an analysis unit, based on a determination result by the determination unit and a result of the delay test.

Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.

Abstract: Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations.

Abstract: Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

Abstract: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining multithreading characteristics of at least a portion the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, multithreading the at least a portion of the configuration based on the second user input, and retiming the multithreaded configuration.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function.

Abstract: Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.

Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Abstract: A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.

Abstract: A design tool can automatically improve timing of nets of a fully routed physical design solution. Nets of a netlist are evaluated against a plurality of re-routing criteria to identify the nets that satisfy at least one of the plurality of re-routing criteria. For each of the nets that satisfy at least one of the plurality of re-routing criteria: several operations are performed. The net is globally re-routed to determine a new global route for the net. Those of the nets that are within a given distance of the new global route are identified. The net is detail re-routed in accordance with the new global route without regard to those of the nets within the given distance of the new global route. Those of the nets within the given distance of the new global route are re-routed after completion of the detailed re-routing of the net.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree.

Abstract: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models.

Abstract: Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.