Pcb, Mcm Design Patents (Class 716/137)
  • Patent number: 10312192
    Abstract: An integrated circuit includes at least one first conductive feature and at least one second conductive feature. The second conductive feature has at least one extension portion, and the extension portion of the second conductive feature is protruded from the projection of the first conductive feature on the second conductive feature. The integrated circuit further includes at least one third conductive feature, and at least one first conductive via electrically connecting the third conductive feature and the extension portion of the second conductive feature.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen
  • Patent number: 10224314
    Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Won Duck Jung, Sung Ho Hyun, Ju Il Eom
  • Patent number: 10108765
    Abstract: There is provided a voltage drop simulation device including: a memory; and a processor coupled to the memory and the processor configured to: divide a conductive body in which a current to be supplied from a power source to elements arranged on a PCB flows into a plurality of meshes including at least one mesh whose size is different from other meshes, calculate voltage values of a plurality of measurement points set in the plurality of meshes, respectively, and calculate a voltage drop of each of the plurality of meshes by dividing, for each of the plurality of meshes treated as a target mesh, a difference between voltage values of a first measurement point included in the target mesh and a second measurement point included in an adjacent mesh that is adjacent to the target mesh by a distance between the first and second measurement points.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 23, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Taku Nobiki
  • Patent number: 10078719
    Abstract: Mechanisms for generating circuit paths are disclosed. A computing device obtains a nodal list that identifies a grid of nodes that is referenced to an area and that uniformly covers at least a portion of the area at a predetermined density. The computing device modifies the nodal list to identify a circuit path from a start node through a succession of neighbor nodes to an end node based on a waypoint list. For each of a plurality of iterations the computing device performs a bubble operation that includes identifying a first pair of nodes that are successive nodes in the circuit path and that are adjacent to a second pair of nodes out of the circuit path, and altering the circuit path to make the second pair of nodes part of the circuit path, such that the first pair of nodes are no longer successive nodes in the circuit path.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: September 18, 2018
    Assignee: Lockheed Martin Corporation
    Inventor: V. Edward Gold, Jr.
  • Patent number: 10007496
    Abstract: To provide dynamic data flow programming for digital signal processing, data flow graphs are constructed from graph libraries. The libraries provide redirection to relevant setup functions so that nodes of a graph table can be instantiated and associated memory can be allocated in dynamic working memory. The nodes of the graph table are modular and should conditions change, the data flow graph can be dynamically altered to change the parameters applied to these nodes thereby altering their functionality and adjusting the behavior of the data flow programming in accordance with the prevailing conditions.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: June 26, 2018
    Assignee: Raptor Oil Limited
    Inventors: Colin MacLean, Gordon Cowie
  • Patent number: 9961762
    Abstract: The present invention relates to a circuit board for COF (Chip on Film) package, which is capable of preventing an influence of coupling noise on a core block of an integrated circuit. The circuit board may include: a base film defined a core block region overlapping a predetermined location of a core block within an integrated circuit and having the same area as or larger area than the core block; first routing patterns formed on the base film; and a first block pattern covering the core block region. The first routing patterns may be formed outside the first block pattern at the same layer as the first block pattern.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: May 1, 2018
    Assignee: SILICON WORKS CO., LTD.
    Inventors: Ju Young Shin, Jung Bae Yun, Yong Jung Kwon, Jeung Hie Choi
  • Patent number: 9659134
    Abstract: A printed circuit board (PCB) layout method executed in a computing device obtains pins of a first electronic component that are connected to a second electronic component or third electronic components included in a T topology circuit. A model of the first electronic component is created according to the obtained pins and is modified to form extended nets of the first electronic component. Pin pairs and match groups are set. Wiring paths of the T topology circuit are determined according to the match groups. The wiring paths are output to an output device.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 23, 2017
    Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Jian-Ye Zhao
  • Patent number: 9514268
    Abstract: A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Ashok Mehta
  • Patent number: 9366723
    Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 9270715
    Abstract: A system and method for coordinating multiple-user edits of shared digital data. A coordinating device may receive commands to edit shared digital data from multiple independently operated user computers. The coordinating device may determine that two or more of the commands from respective user computers are mutually exclusive, redundant or otherwise conflict. The coordinating device may incorporate one of the multiple commands into a global command queue and may annul the other(s). The coordinating device may transmit the global commands to all user computers to be executed locally for implemented the same shared digital data thereon.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: February 23, 2016
    Assignee: Newrow, Inc.
    Inventor: Rony Zarom
  • Publication number: 20150135157
    Abstract: A circuit-design method for a PCB is provided. A first user input is obtained via a user interface of a layout tool, wherein the first user input indicates that an object of a circuit diagram of the PCB is selected in the user interface. A plurality of constraint settings corresponding to an attribute are obtained from a database according to the attribute of the object. The plurality of constraint settings are displayed in a window of the user interface. A second user input is obtained via the user interface, wherein the second user input indicates that one of the plurality of constraint settings is selected in the window. At least one constraint parameter corresponding to the selected constraint setting is assigned to the object, and a tag corresponding to the attribute of the object is attached to the object of the circuit diagram.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 14, 2015
    Applicant: Wistron Corp
    Inventors: Feng-Ling Lin, Ruey-Rong Chang, Wen-Jui Kuo
  • Patent number: 9032358
    Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 12, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Robert Won Chol Kim, Philip Michael Clovis, David Ian West
  • Publication number: 20150128102
    Abstract: A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input and a printed circuit board (PCB) layout based on the circuit. The method further includes generating a bill of material (BOM) for the circuit, and receiving a user selection of at least one of a computer-aided design (CAD) tool format and a PCB layout tool format. The method also includes receiving a user selection to include footprints for the components used in the schematic content or PCB layout and exporting at least one of the schematic content, and PCB layout as well as the PCB footprints to one or more files in accordance with the selected CAD and/or PCB layout tool format.
    Type: Application
    Filed: July 9, 2014
    Publication date: May 7, 2015
    Inventors: Jeff PERRY, Dien MAC, Howard CHEN, Satyanandakishore V. VANAPALLI, Gerold J. DHANABALAN, Tommy E. JEWELL, Khanh VO
  • Patent number: 9026982
    Abstract: An object of the present invention is to provide wiring board design system and wiring board design method to determine a component and a wiring pattern in real-time when designing a wiring on a circuit board. The wiring board design system provides a cloud service for a terminal which is used by users via a network. When to arrange components on the circuit board, while pushing out automatically wirings which are overlapped with the components on the arranging position, the wiring board design system secures a space on that can arrange the component. The wiring processing is performed automatically and the fine adjustment such as rotation, movement of arranged components is performed automatically if necessary. The processing for equalization is performed so as to be the equal wiring density on the circuit board.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 5, 2015
    Assignee: Simplify Design Automation, Inc.
    Inventor: Zen Z. Liao
  • Publication number: 20150121331
    Abstract: A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that satisfy the specified voltage drop. The method can also include determining, by selecting, in response to a specified thermal resistance associated with substrate wiring and insulating layers, from the first set, a second set of wiring cross-sectional areas and corresponding lengths that satisfy the specified thermal resistance. The method can also include selecting, from a set of placement areas corresponding to the second set of wiring cross-sectional areas and corresponding lengths, a heat sink placement area that is greater than a lower size for a placement area and less than an upper size for a placement area.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventor: Keiji Matsumoto
  • Patent number: 9015647
    Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Gerald Suiter, Henry Potts
  • Publication number: 20150092373
    Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) comprising a ball grid array (BGA) of BGA pads on one side of the PCB, arranged in a grid pattern; through-hole vias, including a via pad, arranged in said grid pattern electrically connected to said BGA pads; a solder mask covering the via pad with an opening; a solder pad within said opening electrically connected to said via pad; and a two-lead component attached to said solder pad.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: ALCATEL-LUCENT CANADA INC.
    Inventors: Alex CHAN, Paul J. BROWN
  • Patent number: 8990754
    Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: March 24, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
  • Patent number: 8990761
    Abstract: A method includes: with a setting frequency set as an operating frequency of an LSI, selecting a capacitor having a lowest resonant impedance and a resonant frequency close to the setting frequency with reference to a capacitor characteristic database and installing one or more capacitors, each being the selected capacitor, as high frequency decoupling capacitors, the number thereof corresponding to a value obtained by dividing the upper limit of the power feeding line impedance by a resonant impedance of the capacitor.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: March 24, 2015
    Assignee: NEC Corporation
    Inventor: Kazuhiro Kashiwakura
  • Patent number: 8984471
    Abstract: An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-yeol Jung, Sang-ho Lee, Jeong-nam Cheon, Seung-hun Park
  • Publication number: 20150062845
    Abstract: Electrical equipment 1 includes a chassis 2 that has a bottom portion 3 and side portions 4 and 5, a printed circuit board 10 that is stored in the chassis 2 such that one principal surface 10a faces an inner surface 3a of the portion 3, a sealing resin 20 that is filled in internal space S formed by the chassis 2 and the circuit board 10, embeds the circuit board 10, and a flow suppression portion 8 that decreases a drift velocity of the resin 20 pressed into the space S through the resin injection hole 11, and that is provided in at least part of region A from a position immediately below the hole 11 in the inner surface 3a to an inner surface 4a of a side portion 4 closest to the hole 11 out of the side portions 4 and 5.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventor: Tomoya Akashi
  • Patent number: 8966433
    Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventor: Akiyoshi Saitou
  • Patent number: 8943460
    Abstract: A control unit, e.g., for a motor vehicle, includes a circuit board, a high-impedance circuit component situated on the circuit board and having an impedance of 1 k? or higher in relation to ground of the control unit, and at least one conductive protection element electrically connected to ground and situated adjacent to the high-impedance circuit component. The protection element has a height within a protective distance from the high-impedance circuit component that is at least equal to the protective distance. A method for designing a circuit board of a control unit, and a computer program product for executing the method, include the steps of specifying a position of the high-impedance circuit component, and specifying a position of the protection element such that the protection element has a height within a protective distance from the high-impedance circuit component that is at least equal to the protective distance.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: January 27, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Huebl, Michael Keicher
  • Patent number: 8943459
    Abstract: A testing system for testing a layout of a power pin of a chipset on a circuit board includes a layout information obtaining module, a power pin sorting module, a transmission line sorting module, a transmission line length calculating module, and a report generating module. The layout information obtaining module obtains layout information of the printed circuit board. The power pin sorting module sorts the power pin from a number of pins of the chipset. The transmission line sorting module sorts transmission lines that are connected to the power pin and are located on outer layers of the printed circuit board. The transmission line length calculating module calculates a total length of the transmission lines sorted by the transmission line sorting module and compares the total length with a threshold length. The report generating module generates a testing report indicating whether or not the power pin is qualified.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 27, 2015
    Assignee: ScienBiziP Consulting (Shenzhen) Co., Ltd.
    Inventors: Yu-Hsu Lin, Guang-Feng Ou
  • Publication number: 20150022414
    Abstract: A method of designing a reflectarray including a substrate having a surface perpendicular to a predetermined axis, wherein elements are disposed on the substrate. The method obtains a reflection phase of the elements as a function of a design parameter such as element spacing, when a radio wave enters the arranged elements, and stores a relationship between the reflection phase and the design parameter in a memory. Here, the design parameter is equally set for the elements. The method repeatedly determines, for each of the elements, the design parameter of a specific element in accordance with the relationship. The function of the design parameter has a range of almost 360 degrees with respect to a range of the design parameter. The reflection phase is the continuous function of the element spacing such that two resonant points occur at which the reflection phase becomes zero.
    Type: Application
    Filed: December 3, 2012
    Publication date: January 22, 2015
    Applicant: NTT DOCOMO, INC.
    Inventors: Tamami Maruyama, Yasuhiro Oda, Hidetoshi Kayama, Ngoc Hao Tran, Jiyun Shen
  • Publication number: 20150014044
    Abstract: A method is used for designing a multilayered circuit substrate that generates a physical design layout. The physical design layout represents of at least one electrical circuit passing through a plurality of layers. Based on performance requirements of the electrical circuit, a maximum allowable stub length of a via in the electrical circuit is computed. The computer processor determines if a stub length of an existing via in the physical design layout of the electrical circuit is less than the maximum allowable stub length. If the computer determines that the stub length of the existing via is less than the maximum allowable stub length, the computer removes an external non-functional pad of the existing via from the physical design layout.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Eric R. Ao, Donald R. Dignam, Stephen J. Flint
  • Patent number: 8935644
    Abstract: A printed substrate design system includes: an EMI condition determination unit that compares an EMI characteristic derived by an EMI characteristic derivation unit with an EMI allowable condition, and determines whether the EMI characteristic of a printed substrate satisfies the EMI allowable condition; a substrate configuration change unit that changes an internal configuration of the printed substrate to obtain a changed configuration of the printed substrate in a case where the EMI condition determination unit has determined that the EMI allowable condition is not satisfied, and sets design information of the changed configuration of the printed substrate to design information for deriving the EMI characteristic in the EMI characteristic derivation unit; and an output unit that outputs a printed substrate configuration in a case where the EMI condition determination unit has determined the EMI allowable condition is satisfied.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 13, 2015
    Assignee: NEC Corporation
    Inventors: Masashi Ogawa, Ken Morishita
  • Publication number: 20150012904
    Abstract: A computer-based method for setting electrical specification of signal transmission lines of a printed circuit board (PCB) layout is provided. Data recorded in an electrical specification file is imported. The electrical specification file records a number of chips, pins of each chip, and electrical specification corresponding to each chip. The PCB layout is searched to find the chips and the pins recorded in the electrical specification file. The electrical specification of signal transmission lines connected to the found pins is set according to the electrical specification corresponding to each chip.
    Type: Application
    Filed: November 22, 2013
    Publication date: January 8, 2015
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHENG-HSIEN LEE, SHIN-TING YEN
  • Patent number: 8930869
    Abstract: A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 6, 2015
    Assignee: Fujitsu Limited
    Inventors: Ikuo Ohtsuka, Eiichi Konno, Takahiko Orita, Yoshitaka Nishio, Toshiyasu Sakata
  • Publication number: 20150001716
    Abstract: Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 1, 2015
    Inventors: Alex Chan, Paul James Brown
  • Publication number: 20140380262
    Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 25, 2014
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: MYUNG-SOO JANG, JAE-RIM LEE, JONG-WHA CHONG, JAE-HWAN KIM, BYUNG-GYU AHN, CHEOL-JON JANG
  • Publication number: 20140368292
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and usage, and design structures are disclosed herein. The method includes applying a first voltage polarity to an actuator of a Micro-Electro-Mechanical System (MEMS) structure to place the MEMS structure in a predetermined state for a first operating condition. The method further includes applying a second voltage polarity which is opposite from the first voltage polarity to the actuator of the MEMS structure during a subsequent operating condition.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: Ward A. Johnson, Jenifer E. Lary, Anthony K. Stamper, Kimball M. Watson, Pui L. Yee
  • Publication number: 20140351786
    Abstract: An information processing apparatus is configured to compute the shape of a conductive pattern to be formed on a board by a drawing apparatus that performs drawing on the board using conductive liquid droplets. The information processing apparatus includes an image data generation unit configured to generate image data in which dots each having a diameter determined according to a drawing condition of a conductive pattern by the drawing apparatus are arranged at respective positions which are indicated by data of a conductive pattern and at which conductive liquid droplets are to be landed.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Applicant: KABUSHIKI KAISHA ZUKEN
    Inventor: YASUYUKI WATANABE
  • Patent number: 8898613
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Publication number: 20140326495
    Abstract: A printed circuit board for carrying high frequency signals. Conducting structures of the printed circuit board are shaped within breakout regions to limit impedance discontinuities in the signal paths between vias and conductive traces within the printed circuit board. Values of parameters of traces or anti-pads, for example, may be adjusted to provide a desired impedance. The specific values selected as part of designing a printed circuit board may match the impedance of the breakout region to that of the via. The parameters for which values are selected may include the trace width, thickness, spacing, length over an anti-pad or angle of exit from the breakout region.
    Type: Application
    Filed: August 27, 2012
    Publication date: November 6, 2014
    Applicant: Amphenol Corporation
    Inventor: Jose Ricardo Paniagua
  • Patent number: 8881297
    Abstract: An access arbitration module includes a plurality of active component communication ports for communicating with a plurality of active components, and includes a passive component communication port for communicating with a passive component. The access arbitration module also includes switching logic defined to control transmission of access communication protocol signals between each of the plurality of active component communication ports and the passive component communication port, such that an authorized one of the plurality of active component communication ports is connected in communication with the passive component communication port at a given time, and such that non-authorized ones of the plurality of active component communication ports are prevented from communication with the passive component communication port at the given time.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 4, 2014
    Assignee: Brooks Automation, Inc.
    Inventors: Pablo Gonzalez, Gary Roy Watts
  • Publication number: 20140325469
    Abstract: First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Ikuo OHTSUKA, Toshiyasu SAKATA
  • Publication number: 20140310677
    Abstract: A board design aid device includes a calculating and correcting units. The calculating unit groups a plurality of layers in a multi-layer board into a plurality of pairs of layers based on design information of the multi-layer board, the plurality of layers being stacked and derives a difference of total amounts in respect to a board design element, each of the total amounts being related to each layer of a pair of layers of the plurality of pairs of layers, the board design element being related to a warp of the multi-layer board. The correcting units, based on the difference of the total amounts, corrects an amount of the board design element for at least one of layers among at least one of the plurality of the pairs of layers so that the difference of the total amounts of the board design element is maintained within a certain range.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 16, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Mami NAKADATE, Tetsuyuki Kubota, Shigeo ISHIKAWA
  • Patent number: 8863071
    Abstract: Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: October 14, 2014
    Assignee: Alcatel Lucent
    Inventors: Alex Chan, Paul James Brown
  • Patent number: 8863070
    Abstract: A thermal analysis apparatus calculates an area of a predetermined range including an electronic component mounted on a printed-circuit board. The thermal analysis apparatus counts the number of via holes included in the predetermined range of which the area is calculated. The thermal analysis apparatus calculates a first physical property value using the area calculated, the number of via holes counted, and a preset physical property value of a conductor. The thermal analysis apparatus generates a thermal analysis model subject to thermal analysis in which a preset physical property value is set in the electronic component and a heat release path having the first physical property value calculated is provided in the printed-circuit board so as to extend from the electronic component in a layer direction of the printed-circuit board.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Hideharu Matsushita
  • Patent number: 8863046
    Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: John Richard Dangler, Matthew Stephen Doyle
  • Patent number: 8856722
    Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: October 7, 2014
    Assignee: Nikon Corporation
    Inventors: Isao Sugaya, Takahiro Horikoshi, Kazuya Okamoto
  • Patent number: 8856718
    Abstract: A computer-implemented method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources include configurable interface blocks (CIBs) and wires of different types supported by the CIBs. The method includes identifying, from a representation of a PLD stored within a computer system, components of the PLD to be connected in a configuration of the PLD. A CIB associated with an identified PLD component is then selected. A wire type supported by the selected CIB is also selected. The number of wires of the selected type needed at the selected CIB to implement the PLD configuration and the number of wires of the selected type provided by the CIB are calculated. Signal congestion at the selected CIB is estimated from at least the needed number of wires and the provided number of wires.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 7, 2014
    Assignee: Lattice Semiconductor Corporation
    Inventor: Jun Zhao
  • Patent number: 8856721
    Abstract: A method for generating PCB inspection task data and inspecting a PCB is disclosed. The method by which Gerber data and CAD coordinate file generated at the time of PCB designing is matched to each other facilitates to generate a task data and allows a higher inspection accuracy. The task data generating method comprises generating a Gerber data comprising information for pads on the PCB, loading a CAD coordinate file comprising a coordinate of a component mounted on the pads, inferring a shape of lead and body of the component within a pad area by matching the Gerber data and CAD coordinate file, and then setting a pad area where a tip-end of the body locates as an inspection area.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 7, 2014
    Assignee: Koh Young Technology Inc.
    Inventors: Joong-Ki Jeong, Seung-Jun Lee
  • Patent number: 8856714
    Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Sun Hwang, Sung-Hee Yun, Jae-Hoon Jeong, Won-Cheol Lee, Tae-Heon Lee, Young-Hoe Cheon
  • Patent number: 8850382
    Abstract: An analysis apparatus for a printed circuit board. The analysis apparatus includes a processor that executes a process of rewriting physical property data of a wiring layer of a printed circuit board to a value. The value is based on physical property data of an electronic part having a heat-generating attribute. The electronic part is mounted on the portion of the wiring layer. The analysis apparatus converts the physical property data of the portion of the wiring layer that has the electronic part to physical property data of an insulating layer of the printed circuit board.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Hideharu Matsushita, Akira Ueda
  • Patent number: 8850381
    Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Subramanian Ganesan, Philip Henry Nils Anthony De Buren, Jinny Singh, David Abada
  • Patent number: 8839182
    Abstract: A method for checking signal transmission lines of a printed circuit board (PCB) layout includes determining differential pairs to be checked and dividing the differential pairs to be checked into a first group and a second group. A first reference distance between differential pairs belonging to the same group and a second reference distance between differential pairs belonging to different groups are set. A first box surrounding each line section of one to be checked signal differential line of the first group and a second box surrounding the first box are created. One first box surrounding each line section of the to be checked differential line of the second group is created. Whether or not in the first box and the second box there are differential lines which do not satisfy design standards is determined.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: September 16, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Ya-Ling Huang, Chia-Nan Pai, Shou-Kuo Hsu
  • Patent number: 8839174
    Abstract: Aspects of the invention are directed towards placing components within a layout design for a PCB. More specifically, various implementations of the invention provide methods and apparatuses that can dynamically adjust the shape or placement of component groups during an HGP process. With some implementations of the invention, an HGP process for planning the layout of a PCB is provided. Furthermore, component groups, which conflict, geographically, with either another component group or some other object within the layout design are allowed to be placed during the planning process. Subsequently, the placement locations for one or both of the conflicting component groups are adjusted to resolve the conflict. In some implementations, the geometric boundary, or footprint, of one or both of the component groups is adjusted to resolve the conflict.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Mentor Graphics Corporation
    Inventor: Gerald P. Suiter
  • Patent number: 8832637
    Abstract: Layout information indicating locations of at least components and conductive layers in a printed circuit board, and layouts of conductive wiring patterns on the respective conductive layers and vias which electrically connect between the conductive layers is obtained from a memory. With reference to the layout information, path information indicating a path of one signal line is generated. With reference to the layout information and path information, a divide portion where a path of a return current corresponding to a signal current of the signal line is divided are detected. With reference to the layout information and path information, information indicating a detour path of the return current in a neighborhood of the divide portion is generated.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 9, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshisato Sadamatsu, Shinichi Hama