Abstract: Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

Abstract: A thermal analysis apparatus calculates an area of a predetermined range including an electronic component mounted on a printed-circuit board. The thermal analysis apparatus counts the number of via holes included in the predetermined range of which the area is calculated. The thermal analysis apparatus calculates a first physical property value using the area calculated, the number of via holes counted, and a preset physical property value of a conductor. The thermal analysis apparatus generates a thermal analysis model subject to thermal analysis in which a preset physical property value is set in the electronic component and a heat release path having the first physical property value calculated is provided in the printed-circuit board so as to extend from the electronic component in a layer direction of the printed-circuit board.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: A computer-implemented method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources include configurable interface blocks (CIBs) and wires of different types supported by the CIBs. The method includes identifying, from a representation of a PLD stored within a computer system, components of the PLD to be connected in a configuration of the PLD. A CIB associated with an identified PLD component is then selected. A wire type supported by the selected CIB is also selected. The number of wires of the selected type needed at the selected CIB to implement the PLD configuration and the number of wires of the selected type provided by the CIB are calculated. Signal congestion at the selected CIB is estimated from at least the needed number of wires and the provided number of wires.

Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.

Abstract: A method for generating PCB inspection task data and inspecting a PCB is disclosed. The method by which Gerber data and CAD coordinate file generated at the time of PCB designing is matched to each other facilitates to generate a task data and allows a higher inspection accuracy. The task data generating method comprises generating a Gerber data comprising information for pads on the PCB, loading a CAD coordinate file comprising a coordinate of a component mounted on the pads, inferring a shape of lead and body of the component within a pad area by matching the Gerber data and CAD coordinate file, and then setting a pad area where a tip-end of the body locates as an inspection area.

Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.

Abstract: An analysis apparatus for a printed circuit board. The analysis apparatus includes a processor that executes a process of rewriting physical property data of a wiring layer of a printed circuit board to a value. The value is based on physical property data of an electronic part having a heat-generating attribute. The electronic part is mounted on the portion of the wiring layer. The analysis apparatus converts the physical property data of the portion of the wiring layer that has the electronic part to physical property data of an insulating layer of the printed circuit board.

Abstract: Aspects of the invention are directed towards placing components within a layout design for a PCB. More specifically, various implementations of the invention provide methods and apparatuses that can dynamically adjust the shape or placement of component groups during an HGP process. With some implementations of the invention, an HGP process for planning the layout of a PCB is provided. Furthermore, component groups, which conflict, geographically, with either another component group or some other object within the layout design are allowed to be placed during the planning process. Subsequently, the placement locations for one or both of the conflicting component groups are adjusted to resolve the conflict. In some implementations, the geometric boundary, or footprint, of one or both of the component groups is adjusted to resolve the conflict.

Abstract: A method for checking signal transmission lines of a printed circuit board (PCB) layout includes determining differential pairs to be checked and dividing the differential pairs to be checked into a first group and a second group. A first reference distance between differential pairs belonging to the same group and a second reference distance between differential pairs belonging to different groups are set. A first box surrounding each line section of one to be checked signal differential line of the first group and a second box surrounding the first box are created. One first box surrounding each line section of the to be checked differential line of the second group is created. Whether or not in the first box and the second box there are differential lines which do not satisfy design standards is determined.

Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

Abstract: Layout information indicating locations of at least components and conductive layers in a printed circuit board, and layouts of conductive wiring patterns on the respective conductive layers and vias which electrically connect between the conductive layers is obtained from a memory. With reference to the layout information, path information indicating a path of one signal line is generated. With reference to the layout information and path information, a divide portion where a path of a return current corresponding to a signal current of the signal line is divided are detected. With reference to the layout information and path information, information indicating a detour path of the return current in a neighborhood of the divide portion is generated.

Abstract: An object of the present invention is to provide wiring board design system and wiring board design method to determine a component and a wiring pattern in real-time when designing a wiring on a circuit board. The wiring board design system 1 provides a cloud service for a terminal 3 which is used by users via a network 4. When to arrange components on the circuit board, while pushing out automatically wirings which are overlapped with the components on the arranging position, the wiring board design system 1 secures a space on that can arrange the component. The wiring processing is performed automatically and the fine adjustment such as rotation, movement of arranged components is performed automatically if necessary. The processing for equalization is performed so as to be the equal wiring density on the circuit board.

Abstract: The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first keep out layer, and a reference layer are determined based on the stack-up parameters. The first keep-out layer is placed between the radio frequency layer having a first signal trace disposed thereon and the reference layer. A first keep-out region on the first keep-out layer is formed in corresponding to the first signal trace. Circuit layouts disposed inside the first keep-out region are removed. Consequently, the corresponding keep-out region may be automatically generated in accordance to the signal requirements of the signal trace while designing the circuit layout thereby increase circuit layout quality and efficiency thereof.

Abstract: Embodiments of the invention place surface-mount such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, between BGA pads.

Abstract: A via design method includes doing a simulation according to input data to obtain the impedance of the via of the reference printed circuit board (PCB). An optimal via model is determined according to a group of input data. Simulating is performed according to the thickness of a PCB to-be-designed and the optimal via model data, to obtain the impedance of a via of a PCB to be designed. The number of the anti-pads of the via of the PCB to be designed is recorded when the difference between the impedance of the via of the PCB to be designed and the impedance of the via model of the reference PCB does not fall within a preset range. An interval between each two adjacent anti-pads of the via of the PCB to designed is determined according to the recorded number and the thickness of the PCB to be designed.

Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.

Abstract: A wiring-design support device supports wiring design of a printed circuit board. The processor executes a process that includes holding, in the memory, wiring information including information relating to a plurality of signal wires to be wired in parallel between two components on the printed circuit board, generating a wiring route illustrating a wiring area where the plurality of signal wires are wired between the two components and displaying the wiring route on a display unit based on the wiring information held in the holding. And the processor generates, upon or after the wiring route generated, a detailed wiring where each of the plurality of signal wires is wired along the wiring route based on the wiring route and a wiring rule included in the wiring information, and displaying the detailed wiring on the display unit along with the wiring route.

Abstract: A method for assembling an electrical circuit includes measuring actual values of components of a given type that are held in a stock, and storing the measured actual values in a computerized stock-record. An actual property of an electrical circuit under assembly is determined. Based on the determined actual property, and on a specified response of the circuit, a required value is calculated for a set of one or more of the components of the given type. Responsively to the calculated required value, the stock-record is searched, and a set of one or more of the components is selected from the stock and assembled into the circuit.

Abstract: A via design method includes doing a simulation according to input data to obtain the impedance of the via of the reference printed circuit board (PCB). An optimal via model is determined according to a group of input data. Simulating is performed according to the thickness of a PCB to-be-designed and the optimal via model data, to obtain the impedance of a via of a PCB to be designed. The number of the anti-pads of the via of the PCB to be designed is recorded when the difference between the impedance of the via of the PCB to be designed and the impedance of the via model of the reference PCB does not fall within a preset range. An interval between each two adjacent anti-pads of the via of the PCB to designed is determined according to the recorded number and the thickness of the PCB to be designed.

Abstract: In a method for viewing relevant circuits of a signal on a circuit design diagram of a printed circuit board (PCB), a circuit design diagram and a circuit testing program of the PCB are read from a storage system. A state of each signal of the PCB on the circuit design diagram is determined. Accordingly, sub circuit design diagrams of the signal are obtained from the circuit design diagram and stored into the storage device. When a testing instruction is selected from the circuit testing program, a signal of the PCB is determined. Sub circuit design diagrams of the determined signal are retrieved from the storage device and displayed on a display device.

Abstract: A method of manufacturing a semiconductor device on the basis of changed design layout data. The method decides a functional relationship between layout parameters based on layout data and the electrical characteristic of a plurality of semiconductor elements. Candidates of the values of the layout parameters are extracted from design layout data so as to decrease the difference between a target electrical characteristic and a predicted electrical characteristic. A specific value from the candidate values of the layout parameters is selected and the design layout data is changed based on the specific selected value.

Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: To obtain a band pass delta sigma modulator (excluding ?0?±(?/2)×n; n is an integer being 1 or greater) for a desired frequency by replacing z in a z domain model of a low pass delta-sigma modulator with z? below: z?=fcnv(z,?0), wherein fcnv(z, ?0) is a function in which the absolute value of fcnv(z, ?0) is always 1 for any z and ?0, ?0=2?×(f0/fs), fs is a sampling frequency, and f0 is a center frequency of a quantization noise stop band of the band pass delta-sigma modulator.

Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract: A wiring design support apparatus includes: an input device with which input data about a wiring design content in a multilayered printed circuit board is input; a storage device includes a stab length limitation value table and a back drill application table stored therein, wherein the stab length limitation value table includes set data of a limitation value about a stab length of a through hole of the printed circuit board, and the back drill application table includes set data of information about whether a conductor of a stab of the printed circuit board can be removed or not; and a processor configured to determine, based on the stab length limitation value table and the back drill application table, whether a wiring design of the input data is appropriate.

Abstract: A wiring design support apparatus includes: an input device with which input data about a wiring design content in a multilayered printed circuit board is input; a storage device includes a stab length limitation value table and a back drill application table stored therein, wherein the stab length limitation value table includes set data of a limitation value about a stab length of a through hole of the printed circuit board, and the back drill application table includes set data of information about whether a conductor of a stab of the printed circuit board can be removed or not; and a processor configured to determine, based on the stab length limitation value table and the back drill application table, whether a wiring design of the input data is appropriate.

Abstract: A method for producing an electrical circuit includes providing a substrate having a first pattern of features and defining a second pattern comprising a net of interconnected circuit elements. Different respective transformation rules are specified for different ones of the circuit elements. The second pattern is modified by applying the respective transformation rules to the circuit elements so as to align the circuit elements with the features in the first pattern, and the modified second pattern is applied to the substrate.

Abstract: A signal transmission line check method to be executed by a computing device is described. A to-be-checked signal transmission line group in a displayed printed circuit board (PCB) layout is determined. Whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout is checked according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines. The signal transmission lines that do not satisfy design standards are determined when not all of the to-be-checked signal transmission lines are laid out in a same layer. A related computing device is also disclosed.

Abstract: Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed at the same time by transmitting and receiving the circuit design information relating to the printed boards and the layout design information relating to the printed boards between the circuits and layouts relating to the printed boards.

Abstract: In a generation method, the computer detects a contact between a pin data group of a first connection destination included in three-dimensional shape data and a pin data group of a first connection source included in three-dimensional shape data of a connector, and determines first contact information that indicates combinations of pin data items of the pin data group of the first connection destination and respective pin data items of the pin data group of the first connection source. Furthermore, the computer detects a contact between a pin data group of a second connection destination and a pin data group of a second connection source, and determines second contact information that indicates combinations of pin data items of the pin data group of the second connection destination and respective pin data items of the pin data group of the second connection source, and generates a connection relationship data group.

Abstract: A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

Abstract: A signal transmission line check method to be executed by a computing device is described. A to-be-checked signal transmission line group in a displayed printed circuit board (PCB) layout is determined. Whether all signal transmission lines of the to-be-checked signal transmission line group are laid out in a same layer of the displayed PCB layout is checked according to an input serial number of a chipset and layer properties of the to-be-checked signal transmission lines. The signal transmission lines that do not satisfy design standards are determined when not all of the to-be-checked signal transmission lines are laid out in a same layer. A related computing device is also disclosed.

Abstract: In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied.

Abstract: A technique for routing signal traces in an electronic package design includes extracting near-end and far-end crosstalk values for traces and vias from a model of the electronic package design. The extracted values are then length-normalized and the normalized values are allocated to coupling factors of a cost-function. A first bus routing for the electronic package design is performed to provide a first routed design. Length segments from the first routed design are extracted and inserted in the cost-function. Crosstalk for each bus net is accumulated using the cost-function. In response to the accumulated crosstalk being less than a determined limit, the first routed design is saved. In response to the accumulated crosstalk being greater than the determined limit, an additional bus routing for the electronic package design is performed.

Abstract: In a method for checking wiring diagrams, one element is selected from a first printed circuit board (PCB) file. An element corresponding to the selected element in a second PCB file is searched according to information of the selected element, then the information is recorded into a different element list of the first PCB file, when the second PCB file does not have a corresponding element. The information is recorded into a same element list, when the second PCB file has a corresponding element and the corresponding element has the same information with the element in the first PCB file. The second PCB file and the same element list are compared to locate elements which are included in the second PCB file but not included in the same element list, and the information of the located elements is recorded into a different element list of the second PCB file.

Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.

Abstract: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: Disclosed is a method of designing a power feeding system achieving critical coupling at a desired resonance frequency without adjusting a size or a distance of a coil, and thus obtain high transmission efficiency over broad band. The method includes designing impedances of the power feeding and the power receiving unit to be small as a resonance frequency between the power feeding helical coil and the power receiving helical coil becomes small by adjusting impedances of the DC/AC converter and the AC/DC converter.

Abstract: A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Abstract: Capturing interconnectivity data for one or more multi-pin devices in the design of emulator circuit boards is automated using a translator that extracts relevant information, from a text-based input/output (I/O) definition file. The I/O definition file contains textual descriptions of I/O connectivity information for the various devices created by partitioning the design for application on the emulator circuit board, undefined connector interface entries, and design-specific information. The translator parses through the I/O definition file extracting the I/O connectivity and design-specific information, and retrieves connector interface definitions for the undefined connector interface entries using vendor data.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for terminal metal connector inspection. In some embodiments, a computer-implemented method for identifying a set of critical terminal metal connectors (TMCs) in an integrated circuit (IC) layout includes: identifying a group of necessary terminal metal connectors (TMCs) in the IC layout to form a first portion of the set of critical TMCs; forming a rule including a limit on a number of redundant connections that can be noncompliant between each terminal metal connector (TMC) and a connecting surface in the IC layout without impacting a circuit parameter; and inspecting at least one of the IC layout or the connecting surface to identify each TMC that violates the rule, wherein each identified TMC that violates the rule forms a second portion of the set of critical TMCs.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: A circuit board includes a first circuit area, a first processing unit and a conductive pattern. The first circuit area includes a plurality of first electrically contacts. The first processing unit, which includes a ball grid array (BGA) substrate, is disposed on the first circuit area and is electrically connected to the first electrically contacts. The BGA substrate has a plurality of solder balls and a bypass circuit. The conductive pattern is electrically connected to the first electrically contacts.

Abstract: Layout information indicating a layout of circuits on a print circuit board is obtained. With reference to the layout information, a connection portion, which electrically connects a ground pattern of the print circuit board and an external ground of the print circuit board, is specified, and a pin, which is included in a connector laid out on the print circuit board and is connected to the ground pattern, is identified. Then, a discharge route between the pin and connection portion is determined.

Abstract: A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.