Abstract: The conductive film has a wiring pattern which, with respect to the frequencies and intensities of moire obtained by applying a human visual response characteristic to the frequency information and intensity information of moire calculated from peak frequencies and peak intensities of the two-dimensional Fourier spectrums of the transmittance image data of the wiring pattern and the transmittance image data of a pixel array pattern, causes the sum of intensities of moire each corresponding to frequencies of moire falling within a frequency range predetermined depending on the visual response characteristic to be less than or equal to a predetermined value. The conductive film allows suppression of moire and significant improvement in visibility.

Abstract: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle pattern. A substrate image is calculated, based on using the simulated reticle pattern in an optical lithographic process to form the substrate image. A system for OPC is also disclosed.

Abstract: A route technique includes: receiving an input specifying a plurality of semiconductor device components and their logical connections; determining route information pertaining to a plurality of routes that connect in one or more metal layers the semiconductor device components according to their logical connections, the determination being based at least in part on a plurality of predefined tracks associated with a metal layer; and outputting at least a portion of the route information. A first portion of the plurality of predefined tracks corresponds to a first color and a second portion of the plurality of predefined tracks corresponds to a second color.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.

Abstract: Aspects of the invention relate to techniques for mask rule checking based on curvature information. The curvature information comprises convex curvature information and concave curvature information. The convex curvature information for a vertex of a mask feature may comprise a convex curvature value derived based on the size of a circle that passes through the vertex, is tangent to an edge and does not cross any other edges. The concave curvature information for the vertex may comprise a concave curvature value derived based on the size of a circle that is tangent to two edges that form the vertex and does not cross any other edges, and of which distance from the vertex measured from the nearest point is no more than a predetermined number. The generated curvature information is compared with threshold curvature information to determine mask rule violations.

Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract: Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.

Abstract: The present invention relates to methods and systems for designing gauge patterns that are extremely sensitive to parameter variation, and thus robust against random and repetitive measurement errors in calibration of a lithographic process utilized to image a target design having a plurality of features. The method may include identifying most sensitive line width/pitch combination with optimal assist feature placement which leads to most sensitive CD (or other lithography response parameter) changes against lithography process parameter variations, such as wavefront aberration parameter variation. The method may also include designing gauges which have more than one test patterns, such that a combined response of the gauge can be tailored to generate a certain response to wavefront-related or other lithographic process parameters. The sensitivity against parameter variation leads to robust performance against random measurement error and/or any other measurement error.

Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.

Abstract: Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, the substrate having a first feature and a second feature underlying the resist layer, the method comprising: simulating a first partial image using interaction of the incident radiation and the first feature without using interaction of the incident radiation and the second feature; simulating a second partial image using the interaction of the incident radiation and of the second feature without using the interaction of the incident radiation and the first feature; computing the image formed within the resist layer from the first partial image, and the second partial image; wherein the interaction of the incident radiation and the first feature is different from the interaction of the incident radiation and the second feature.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A semiconductor inspection apparatus identifies regions of a reticle or semiconductor wafer appropriate for cell-to-cell inspection by analyzing a semiconductor design database. Appropriate regions can be identified in a region map for use by offline inspection tools.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.

Abstract: A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process is disclosed. The method includes defining an initial H-mask and an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask and vertical critical features in the V-mask; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask.

Abstract: Various embodiments include approaches for calibrating a model for a lithographic printing process. Some embodiments include a computer-implemented method for calibrating a model for a lithographic printing process. Some approaches include: identifying parameters for a model of the lithographic printing process; assembling a population of design content including potentially printable features that can be printed by the lithographic printing process; preparing at least one matrix expressing a similarity between the potentially printable features in terms of the parameters for the model; determining a manifold of smaller dimensionality than the parameters for the model which exhibit maximum variation in similarity within the at least one matrix; and selecting a sample dataset of the potentially printable features from the manifold.

Abstract: There is provided a method comprising: examining the location of one or more feature(s) of the one or more component(s) of a circuit arrangement to determine the displacement of the location of said one or more associated communication contact(s) with respect to a designed location for the communication contact(s), and providing corrective communication path layout data of said circuit arrangement based upon the said displacement(s).

Abstract: Among other things, one or more systems and techniques for width bias adjustment for a design layout are provided. During fabrication, characteristics of a component can change, such as size, width, position, etc., from how a design layout represents such components. Accordingly, a width bias table is used to identify a width bias value that can be applied between a first polygon and a second polygon to compensate for a characteristic change associated with at least one of the first polygon and the second polygon during fabrication. The width bias value is used during RC extraction to determine an electrical characteristic adjustment, such as an additional capacitance or resistance associated with the width bias value, for at least one of the first polygon and the second polygon. In this way, RC extraction, during a design phase, can take into account electrical characteristic changes that occur during fabrication.

Abstract: An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.

Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.

Abstract: A method of lithography by radiation having critical dimensions of the order of some ten nanometers makes it possible to carry out the correction of the proximity effects by joint optimization of the dose modulation and geometric corrections. Accordingly, a deconvolution of the pattern to be etched is carried out by an iterative procedure modeling the interactions of the radiation with the resined support by a joint probability distribution. Advantageously, when the support exposure tool is of formed-beam type, the pattern to be etched is split into contrasted levels and then the deconvolved image is vectorized and fractured before carrying out the exposure step. In an advantageous embodiment, the method is applied to at least two character cells which are exposed in a multi-pass cells projection method.

Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.

Abstract: Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape wavefront in the lithographic projection apparatus, enabling aberration control of the overall imaging process.

Abstract: The preset invention provides methods, systems and computer program product for selection of an optimum set of patterns to calibrate a lithography model so that the model can predict imaging performance of a lithography apparatus/system more accurately and reliably without being prohibitively expensive in terms of using computational and metrology resources and time. The method is based on modeling sensitivity of the calibration patterns to measurement noise. In one aspect of the present invention, a method is disclosed, comprising: identifying a model of at least a portion of a lithographic process; identifying a set of patterns for calibrating the model; and, estimating measurement noise associated with the set of patterns.

Abstract: A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

Abstract: Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Conventional edge adjustment values for the edge fragments are first derived from edge placement error values. Neighbor-aware edge adjustment values for the edge fragments are then computed based on the edge placement error values, the conventional edge adjustment values and edge fragment correlation information. The computation comprises: calculating pseudo edge placement error values by subtracting neighboring edge movement contribution values from the edge placement error values and calculating the neighbor-aware edge adjustment values based on the pseudo edge placement error values. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.

Abstract: A method of decomposing a layout for triple pattern lithography generates a first conflict graph from the layout. The method generates a second conflict graph from the first conflict graph, and identifies loops in the second conflict graph as decomposition violations.

Abstract: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.

Abstract: Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients.

Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.

Abstract: Methodologies and an apparatus enabling an improvement of a manufacturing yield of an IC design are disclosed. Embodiments include: determining a portion of a layout of an IC design, the portion including a first pattern including a plurality of design connections; determining a function performed by the first pattern based, at least in part, on the design connections; and selecting, by a processor, a second pattern based on the function.

Abstract: In accordance with one aspect of this invention, a pattern inspection method includes acquiring optical images regarding figure patterns arranged in each of frame regions, for each of the plurality of frame regions; measuring linewidth dimensions of the figure patterns, for each of the frame regions; operating an average value of each linewidth dimension shift between linewidth dimensions of figure patterns in a reference image corresponding to the frame region concerned and the linewidth dimensions of the figure patterns in the optical image, for each of the frame regions; extracting a specific frame from the frame regions by comparing the average value of the frame region concerned, with average values of frame regions around the frame region concerned, for each of the frame regions; and inspecting the specific frame for dimensional defects of linewidth dimensions.

Abstract: An inspection data generator generates inspection data used to inspect a pattern transferred onto the same material layer using exposure processes. An input part of the generator receives first layout data for a mask used in a first exposure process and second layout data for a mask used in a second exposure process, and receives a measured value of a misalignment between a first transfer pattern actually transferred onto the material layer in the first exposure process and a second transfer pattern actually transferred onto the material layer in the second exposure process. A processor unit generates the inspection data by shifting the first layout data and the second layout data from each other by an amount corresponding to the measured value and then combining the first layout data with the second layout data. An output part outputs the inspection data to inspect the pattern transferred onto the material layer.

Abstract: An inspection region of a mask is virtually divided by stripes, and a pattern on a position error correcting unit is also virtually divided by stripes. Then, a stage is moved such that all the stripes of both the mask and the position error correcting unit are continuously scanned, so that optical images of these stripes are acquired. Fluctuation values of position coordinates of the patterns formed on the position error correcting unit are acquired from the optical images of the position error correcting unit. Based upon the fluctuation values, fluctuation values of the position coordinates of the respective patterns in the inspection region of the mask are obtained so that the position coordinates are corrected. Thereafter, a map is generated from the fluctuation values of the position coordinates of the respective patterns in the inspection region of the mask.

Abstract: An integrated design-for-manufacturing (DFM) platform is provided. The integrated DFM platform an automatic warning and verification system; an automatic data feedback and feed forward system; an automatic intellectual property (IP) library management system; and a data management system integrated under a same platform.

Abstract: Candidate layout patterns can be assessed using a sparse pattern dictionary of known design layout patterns by determining sparse coefficients for each candidate pattern, reconstructing the respective candidate pattern, and determining reconstruction error. Any pattern with reconstruction error over a threshold value can be flagged. Compressive sampling can be employed, such as by projecting each candidate pattern onto a random line or a random matrix. The dictionary can be built by determining sparse coefficients of known patterns and respective basis function sets using matching pursuit, variants of SVD, and/or other techniques.

Abstract: Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

Abstract: A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

Abstract: A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

Abstract: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first simulation tool, performing a V/I test on a network through a second simulation tool, determining whether a mismatch exists based upon a result of the V/I test and modifying a connection trace of the network to generate a second layout.

Abstract: Among other things, techniques for balancing mask loading are provided for herein. In some embodiments, one or more windows are defined within a layout. Based upon polygons comprised within respective windows, a localized mask loading is computed for the layout. In some embodiments, a global mask loading is also computed for the layout. Using the localized mask loading and the global mask loading, if computed, a loading effect of a plurality of mask pattern schemes is evaluated to identify a mask pattern scheme having a desired loading effect.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.

Abstract: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating the shape of the pattern is automatically generated within a minimum time by the analysis using the CAD image obtained by conversion from CAD data, an CAD image creation unit that creates the CAD image by converting the CAD data into an image format includes an image-quantizing width determining section, a brightness information providing section, and a pattern shape deformation processing section; the imaging recipe being created using the CAD image created by the CAD image creation unit.