Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count.

Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

Abstract: A method and system arrangement for controlling and determining mask operation activities. Upon obtaining chip physical layout design data and running resolution enhancement technology on the chip physical layout design to generate mask features which may include any sub-resolution assist features, a placement sensitivity metric is determined for each of the generated mask features or edge fragments. In one alternative embodiment an edge placement sensitivity metric is determined for each edge of the generated mask features or edge fragments. The determined sensitivity metrics for each feature are classified and applied to subsequent mask operational activities such as post processing, write exposure and mask repair.

Abstract: Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.

Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Abstract: Embodiments of the disclosure include identifying circuit elements for selective inclusion in speed-push processing and related circuit systems, apparatus, and computer-readable media. A method for altering a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied to identify at least one of the plurality of cells as having performance margin. The speed-push mask is altered such that the at least one of the plurality of cells having performance margin may be fabricated as a non-speed-pushed cell. Additionally, a method for creating a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to identify at least one of the plurality of cells below a performance threshold. A speed-push mask is created such that the at least one of the plurality of cells below the performance threshold may be fabricated as a speed-pushed cell.

Abstract: A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.

Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.

Abstract: An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells.

Abstract: The present invention provides a generation method of generating data for a mask pattern to be used for an exposure apparatus including a projection optical system for projecting a mask pattern including a main pattern and auxiliary pattern onto a substrate, including a step of setting a generation condition under which the auxiliary pattern is generated, and a step of determining whether a value of an evaluation function describing an index which indicates a quality of an image of the mask pattern calculated, wherein if it is determined that the value of the evaluation function falls outside a tolerance range, the generation condition is changed to set a new generation condition.

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract: The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.

Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

Abstract: A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration.

Abstract: A method for making a photomask layout is disclosed. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract: A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.

Abstract: A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination.

Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

Abstract: A method for designating TT and TB regions utilizing designated TS regions, without fully generating TT and TB features, and thereafter fabricating TS regions utilizing the designated TT and TB regions, is disclosed. Embodiments include: determining a TS having a placement and shape, the TS shape having a first horizontal dimension and a first vertical dimension; determining an active region including the TS; determining an extended TS including the TS and an extension portion in the horizontal and vertical directions, adjacent each edge of the TS; and determining a TB region based on the active region and the extended TS.

Abstract: Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Abstract: The present invention provides a computer-readable recording medium recording a program for causing a computer to execute a method of determining a pattern of a mask and an effective light source distribution with which the mask is illuminated, both of which are used for an exposure apparatus including an illumination optical system which illuminates a mask with light from a light source and a projection optical system which projects a pattern of the mask onto a substrate.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.

Abstract: A method of making pattern data of a photomask pattern includes: the processes of adding, to each of first cells, information of the first cell higher than the first cell on the basis of a hierarchical structure; selecting, from the first cells included in one level of the hierarchical structure, the first cell identical to one of the first cells included in a level higher than the one level and the first cell placed inside two or more of the first cells included in a level immediately higher than the one level, and forming a cell group with the selected first cells; making pattern data of the first cells not included in the cell group in consideration of the optical proximity effect and forming a fourth cell group with second cells including the pattern data; and replacing the first cells with the corresponding second cells in input data.

Abstract: Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method includes providing a circuit design layout that has a plurality of element patterns. A first library of problematic sections is provided. An initial circuit section and an additional circuit section within the circuit design layout are determined to match problematic sections in the first library, and the initial and additional circuit sections have overlapping peripheral boundaries. A second library of replacement sections is provided. The replacement sections correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections to form the final circuit layout. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced thereby.

Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Abstract: A computer-implemented method for polygon recovery from a +1/?1 description of a plurality of polygons includes receiving, by a computer, a set of data comprising the +1/?1 description of the plurality of polygons, the +1/?1 description comprising a plurality of corners; determining a 4-directional data structure, a Mm value, and a Mp value for each of the plurality of corners; and recovering the polygons by assigning each of the plurality of corners to one of the plurality of polygons based on the 4-directional data structure, the Mm value, and the Mp value for each of the plurality of corners, and, for each of the plurality of polygons, determining an order of the polygon's respective corners.

Abstract: Embodiments relate to polygon recovery from a +1/?1 description of a plurality of polygons of a very large scale integrated (VLSI) mask for production of a VLSI semiconductor device. An aspect includes receiving a set of data comprising the +1/?1 description of the plurality of polygons of the VLSI mask, the +1/?1 description comprising a plurality of corners. Another aspect includes determining a 4-directional data structure, a Mm value comprising a first limit value, and a Mp value comprising a second limit value for each of the plurality of corners. Another aspect includes recovering the plurality of polygons from the set of data by assigning each of the plurality of corners to a single polygon based on the 4-directional data structure, the Mm value, and the Mp value of each of the plurality of corners, and determining an order of the respective corners of each polygon.

Abstract: A segmented mask includes a set of cell structures, wherein each cell structure includes a set of features having an unresolvable segmentation pitch along a first direction, wherein the unresolvable segmentation pitch along the first direction is smaller than the illumination of the lithography printing tool, wherein the plurality of cell structures have a pitch along a second direction perpendicular to the first direction, wherein the unresolvable segmentation pitch is suitable for generating a printed pattern for shifting the best focus position of the lithography tool by a selected amount to achieve a selected level of focus sensitivity.

Abstract: A method and system check a double patterning layout in abutting cells and switch the pattern in one of the cells if the edge patterns in each cell are in the same mask. The method includes receiving layout data having patterns in abutting cells, changing a designated mask in one cell if the edge patterns are in the same mask, adjusting cell edge spacings at a shared edge according to a minimum spacing rule and a G1-rule, and outputting a presentation of the layout data.

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract: An image of a mask pattern is overlaid on an image of a mask blank annotated with the center location and dimensions of each measured mask defect. Design clips centered at the measured defects are generated with lateral dimensions less than allowable movement of the mask pattern over the mask blank. Each design clip is converted into a binary image including pixels corresponding to defect-activating regions and pixels corresponding to defect-hiding regions. Each pixel region representing the defect-activating region is expanded by laterally biasing peripheries by one half of the lateral extent of the defect located within the corresponding design clip. Biased design clips are logically compiled pixel by pixel to determine an optimal pattern shift vector representing the amount of pattern shift.

Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

Abstract: A method for correcting topography proximity effects (TPE) for an integrated circuit (IC) design is described. This method includes dividing the IC design into a plurality of levels (z-direction). Each level can be decomposed into one or more elementary geometries. These elementary geometries can be top view geometries, cross-sectional geometries, half-plane geometries, geometries with single slope sides, and/or geometries with multiple slope sides. The one or more elementary geometries can be compared to primitives in a library. A transfer matrix can be generated using the matching primitives and the elementary geometries. A disturbance matrix can be calculated based on the transfer matrix. This disturbance matrix can advantageously capture a spectrum of a reflective electric field from a spectrum of an incident electric field. Wave propagation through a photoresist layer can be performed using the disturbance matrix for the plurality of levels.

Abstract: A two-level matching technique is described. A system can generate a set of index patterns based on a set of library patterns in a pattern library. The pattern library can include patterns that are expected to have problems during manufacturing. Next, the system can use a fast matching process to check if a first-level pattern clip potentially matches one or more index patterns from the set of index patterns. If so, the system can use a detailed matching process to match a second-level pattern clip with library patterns that correspond to the one or more index patterns. Otherwise, the system can report that the first-level pattern clip does not match any library pattern in the pattern library.

Abstract: Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The stored metal fill data is loaded into the placement and routing database after the at least one change is implemented to the layout data. A check is performed for an existence of one or more violations associated with the metal fill data due to implementing the at least one change to the layout data in the placement and routing database. A correction procedure is performed on the metal fill data when one or more violations exist.

Abstract: Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes associated with the marker forms the DP loop and displays the marker in the design layout.

Abstract: A method for improving a lithographic process for imaging a design layout onto a substrate using a lithographic projection apparatus comprising a patterning device, wherein the patterning device deforms from a first state to a second state, the method comprising: determining a deformation of the patterning device from the first state to the second state; determining a compensatory design layout from the design layout and the deformation; wherein the compensatory design layout is such that when the compensatory design layout is generated on the patterning device in the first state, the deformation of the patterning device deforms the compensatory design layout to the design layout.

Abstract: A method for separating features in a target layout into different mask layouts for use in a photolithographic process. Features of a target layer are searched for features having a predefined shape. In one embodiment, portions of the feature having the predefined shape divided into two or more sub-features and at least one sub-feature are not considered when separating the features into two or more mask layouts. In another embodiment, features having a predefined shape are cut to form two or more sub-features and all features and sub-features are considered when separating the features of the target layout into the two or more mask layouts.

Abstract: Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, context and visible portions. An inverse lithography process is then performed on the core portion of the re-correction region while taking into account effects from the context portion of the re-correction region to generate a first modified re-correction region. A traditional OPC process is then performed on the core and context portions of the first modified re-correction region while taking into account effects from the visible portion of the first modified re-correction region to generate a second modified re-correction region.

Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.